1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4; Use a 64-bit value with lo bits that can be represented as an inline constant 5; GCN-LABEL: {{^}}i64_imm_inline_lo: 6; GCN: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], 5 7; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VGPR]]: 8define void @i64_imm_inline_lo(i64 addrspace(1) *%out) { 9entry: 10 store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005 11 ret void 12} 13 14; Use a 64-bit value with hi bits that can be represented as an inline constant 15; GCN-LABEL: {{^}}i64_imm_inline_hi: 16; GCN: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], 5 17; GCN: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]] 18define void @i64_imm_inline_hi(i64 addrspace(1) *%out) { 19entry: 20 store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678 21 ret void 22} 23 24; GCN-LABEL: {{^}}store_imm_neg_0.0_i64: 25; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 26; GCN-DAG: v_bfrev_b32_e32 v[[HI_VREG:[0-9]+]], 1{{$}} 27; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 28define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) { 29 store i64 -9223372036854775808, i64 addrspace(1) *%out 30 ret void 31} 32 33; GCN-LABEL: {{^}}store_inline_imm_neg_0.0_i32: 34; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} 35; GCN: buffer_store_dword [[REG]] 36define void @store_inline_imm_neg_0.0_i32(i32 addrspace(1)* %out) { 37 store i32 -2147483648, i32 addrspace(1)* %out 38 ret void 39} 40 41; GCN-LABEL: {{^}}store_inline_imm_0.0_f32: 42; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} 43; GCN: buffer_store_dword [[REG]] 44define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) { 45 store float 0.0, float addrspace(1)* %out 46 ret void 47} 48 49; GCN-LABEL: {{^}}store_imm_neg_0.0_f32: 50; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} 51; GCN: buffer_store_dword [[REG]] 52define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) { 53 store float -0.0, float addrspace(1)* %out 54 ret void 55} 56 57; GCN-LABEL: {{^}}store_inline_imm_0.5_f32: 58; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}} 59; GCN: buffer_store_dword [[REG]] 60define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) { 61 store float 0.5, float addrspace(1)* %out 62 ret void 63} 64 65; GCN-LABEL: {{^}}store_inline_imm_m_0.5_f32: 66; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}} 67; GCN: buffer_store_dword [[REG]] 68define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) { 69 store float -0.5, float addrspace(1)* %out 70 ret void 71} 72 73; GCN-LABEL: {{^}}store_inline_imm_1.0_f32: 74; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}} 75; GCN: buffer_store_dword [[REG]] 76define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) { 77 store float 1.0, float addrspace(1)* %out 78 ret void 79} 80 81; GCN-LABEL: {{^}}store_inline_imm_m_1.0_f32: 82; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}} 83; GCN: buffer_store_dword [[REG]] 84define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) { 85 store float -1.0, float addrspace(1)* %out 86 ret void 87} 88 89; GCN-LABEL: {{^}}store_inline_imm_2.0_f32: 90; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}} 91; GCN: buffer_store_dword [[REG]] 92define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) { 93 store float 2.0, float addrspace(1)* %out 94 ret void 95} 96 97; GCN-LABEL: {{^}}store_inline_imm_m_2.0_f32: 98; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}} 99; GCN: buffer_store_dword [[REG]] 100define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) { 101 store float -2.0, float addrspace(1)* %out 102 ret void 103} 104 105; GCN-LABEL: {{^}}store_inline_imm_4.0_f32: 106; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}} 107; GCN: buffer_store_dword [[REG]] 108define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) { 109 store float 4.0, float addrspace(1)* %out 110 ret void 111} 112 113; GCN-LABEL: {{^}}store_inline_imm_m_4.0_f32: 114; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}} 115; GCN: buffer_store_dword [[REG]] 116define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) { 117 store float -4.0, float addrspace(1)* %out 118 ret void 119} 120 121 122; GCN-LABEL: {{^}}store_inline_imm_inv_2pi_f32: 123; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e22f983{{$}} 124; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0.15915494{{$}} 125; GCN: buffer_store_dword [[REG]] 126define void @store_inline_imm_inv_2pi_f32(float addrspace(1)* %out) { 127 store float 0x3FC45F3060000000, float addrspace(1)* %out 128 ret void 129} 130 131; GCN-LABEL: {{^}}store_inline_imm_m_inv_2pi_f32: 132; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbe22f983{{$}} 133; GCN: buffer_store_dword [[REG]] 134define void @store_inline_imm_m_inv_2pi_f32(float addrspace(1)* %out) { 135 store float 0xBFC45F3060000000, float addrspace(1)* %out 136 ret void 137} 138 139; GCN-LABEL: {{^}}store_literal_imm_f32: 140; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000 141; GCN: buffer_store_dword [[REG]] 142define void @store_literal_imm_f32(float addrspace(1)* %out) { 143 store float 4096.0, float addrspace(1)* %out 144 ret void 145} 146 147; GCN-LABEL: {{^}}add_inline_imm_0.0_f32: 148; GCN: s_load_dword [[VAL:s[0-9]+]] 149; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 0{{$}} 150; GCN: buffer_store_dword [[REG]] 151define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) { 152 %y = fadd float %x, 0.0 153 store float %y, float addrspace(1)* %out 154 ret void 155} 156 157; GCN-LABEL: {{^}}add_inline_imm_0.5_f32: 158; GCN: s_load_dword [[VAL:s[0-9]+]] 159; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 0.5{{$}} 160; GCN: buffer_store_dword [[REG]] 161define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) { 162 %y = fadd float %x, 0.5 163 store float %y, float addrspace(1)* %out 164 ret void 165} 166 167; GCN-LABEL: {{^}}add_inline_imm_neg_0.5_f32: 168; GCN: s_load_dword [[VAL:s[0-9]+]] 169; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], -0.5{{$}} 170; GCN: buffer_store_dword [[REG]] 171define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) { 172 %y = fadd float %x, -0.5 173 store float %y, float addrspace(1)* %out 174 ret void 175} 176 177; GCN-LABEL: {{^}}add_inline_imm_1.0_f32: 178; GCN: s_load_dword [[VAL:s[0-9]+]] 179; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 1.0{{$}} 180; GCN: buffer_store_dword [[REG]] 181define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) { 182 %y = fadd float %x, 1.0 183 store float %y, float addrspace(1)* %out 184 ret void 185} 186 187; GCN-LABEL: {{^}}add_inline_imm_neg_1.0_f32: 188; GCN: s_load_dword [[VAL:s[0-9]+]] 189; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], -1.0{{$}} 190; GCN: buffer_store_dword [[REG]] 191define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) { 192 %y = fadd float %x, -1.0 193 store float %y, float addrspace(1)* %out 194 ret void 195} 196 197; GCN-LABEL: {{^}}add_inline_imm_2.0_f32: 198; GCN: s_load_dword [[VAL:s[0-9]+]] 199; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 2.0{{$}} 200; GCN: buffer_store_dword [[REG]] 201define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) { 202 %y = fadd float %x, 2.0 203 store float %y, float addrspace(1)* %out 204 ret void 205} 206 207; GCN-LABEL: {{^}}add_inline_imm_neg_2.0_f32: 208; GCN: s_load_dword [[VAL:s[0-9]+]] 209; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], -2.0{{$}} 210; GCN: buffer_store_dword [[REG]] 211define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) { 212 %y = fadd float %x, -2.0 213 store float %y, float addrspace(1)* %out 214 ret void 215} 216 217; GCN-LABEL: {{^}}add_inline_imm_4.0_f32: 218; GCN: s_load_dword [[VAL:s[0-9]+]] 219; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 4.0{{$}} 220; GCN: buffer_store_dword [[REG]] 221define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) { 222 %y = fadd float %x, 4.0 223 store float %y, float addrspace(1)* %out 224 ret void 225} 226 227; GCN-LABEL: {{^}}add_inline_imm_neg_4.0_f32: 228; GCN: s_load_dword [[VAL:s[0-9]+]] 229; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], -4.0{{$}} 230; GCN: buffer_store_dword [[REG]] 231define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) { 232 %y = fadd float %x, -4.0 233 store float %y, float addrspace(1)* %out 234 ret void 235} 236 237; GCN-LABEL: {{^}}commute_add_inline_imm_0.5_f32: 238; GCN: buffer_load_dword [[VAL:v[0-9]+]] 239; GCN: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]] 240; GCN: buffer_store_dword [[REG]] 241define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 242 %x = load float, float addrspace(1)* %in 243 %y = fadd float %x, 0.5 244 store float %y, float addrspace(1)* %out 245 ret void 246} 247 248; GCN-LABEL: {{^}}commute_add_literal_f32: 249; GCN: buffer_load_dword [[VAL:v[0-9]+]] 250; GCN: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]] 251; GCN: buffer_store_dword [[REG]] 252define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 253 %x = load float, float addrspace(1)* %in 254 %y = fadd float %x, 1024.0 255 store float %y, float addrspace(1)* %out 256 ret void 257} 258 259; GCN-LABEL: {{^}}add_inline_imm_1_f32: 260; GCN: s_load_dword [[VAL:s[0-9]+]] 261; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 1{{$}} 262; GCN: buffer_store_dword [[REG]] 263define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) { 264 %y = fadd float %x, 0x36a0000000000000 265 store float %y, float addrspace(1)* %out 266 ret void 267} 268 269; GCN-LABEL: {{^}}add_inline_imm_2_f32: 270; GCN: s_load_dword [[VAL:s[0-9]+]] 271; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 2{{$}} 272; GCN: buffer_store_dword [[REG]] 273define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) { 274 %y = fadd float %x, 0x36b0000000000000 275 store float %y, float addrspace(1)* %out 276 ret void 277} 278 279; GCN-LABEL: {{^}}add_inline_imm_16_f32: 280; GCN: s_load_dword [[VAL:s[0-9]+]] 281; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 16 282; GCN: buffer_store_dword [[REG]] 283define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) { 284 %y = fadd float %x, 0x36e0000000000000 285 store float %y, float addrspace(1)* %out 286 ret void 287} 288 289; GCN-LABEL: {{^}}add_inline_imm_neg_1_f32: 290; GCN: s_load_dword [[VAL:s[0-9]+]] 291; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], -1{{$}} 292; GCN: buffer_store_dword [[REG]] 293define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) { 294 %y = fadd float %x, 0xffffffffe0000000 295 store float %y, float addrspace(1)* %out 296 ret void 297} 298 299; GCN-LABEL: {{^}}add_inline_imm_neg_2_f32: 300; GCN: s_load_dword [[VAL:s[0-9]+]] 301; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], -2{{$}} 302; GCN: buffer_store_dword [[REG]] 303define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) { 304 %y = fadd float %x, 0xffffffffc0000000 305 store float %y, float addrspace(1)* %out 306 ret void 307} 308 309; GCN-LABEL: {{^}}add_inline_imm_neg_16_f32: 310; GCN: s_load_dword [[VAL:s[0-9]+]] 311; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], -16 312; GCN: buffer_store_dword [[REG]] 313define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) { 314 %y = fadd float %x, 0xfffffffe00000000 315 store float %y, float addrspace(1)* %out 316 ret void 317} 318 319; GCN-LABEL: {{^}}add_inline_imm_63_f32: 320; GCN: s_load_dword [[VAL:s[0-9]+]] 321; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 63 322; GCN: buffer_store_dword [[REG]] 323define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) { 324 %y = fadd float %x, 0x36ff800000000000 325 store float %y, float addrspace(1)* %out 326 ret void 327} 328 329; GCN-LABEL: {{^}}add_inline_imm_64_f32: 330; GCN: s_load_dword [[VAL:s[0-9]+]] 331; GCN: v_add_f32_e64 [[REG:v[0-9]+]], [[VAL]], 64 332; GCN: buffer_store_dword [[REG]] 333define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) { 334 %y = fadd float %x, 0x3700000000000000 335 store float %y, float addrspace(1)* %out 336 ret void 337} 338 339 340; GCN-LABEL: {{^}}add_inline_imm_0.0_f64: 341; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 342; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 343; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0{{$}} 344; GCN: buffer_store_dwordx2 [[REG]] 345define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) { 346 %y = fadd double %x, 0.0 347 store double %y, double addrspace(1)* %out 348 ret void 349} 350 351; GCN-LABEL: {{^}}add_inline_imm_0.5_f64: 352; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 353; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 354; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.5 355; GCN: buffer_store_dwordx2 [[REG]] 356define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) { 357 %y = fadd double %x, 0.5 358 store double %y, double addrspace(1)* %out 359 ret void 360} 361 362; GCN-LABEL: {{^}}add_inline_imm_neg_0.5_f64: 363; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 364; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 365; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -0.5 366; GCN: buffer_store_dwordx2 [[REG]] 367define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) { 368 %y = fadd double %x, -0.5 369 store double %y, double addrspace(1)* %out 370 ret void 371} 372 373; GCN-LABEL: {{^}}add_inline_imm_1.0_f64: 374; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 375; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 376; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1.0 377; GCN: buffer_store_dwordx2 [[REG]] 378define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) { 379 %y = fadd double %x, 1.0 380 store double %y, double addrspace(1)* %out 381 ret void 382} 383 384; GCN-LABEL: {{^}}add_inline_imm_neg_1.0_f64: 385; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 386; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 387; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -1.0 388; GCN: buffer_store_dwordx2 [[REG]] 389define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) { 390 %y = fadd double %x, -1.0 391 store double %y, double addrspace(1)* %out 392 ret void 393} 394 395; GCN-LABEL: {{^}}add_inline_imm_2.0_f64: 396; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 397; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 398; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 2.0 399; GCN: buffer_store_dwordx2 [[REG]] 400define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) { 401 %y = fadd double %x, 2.0 402 store double %y, double addrspace(1)* %out 403 ret void 404} 405 406; GCN-LABEL: {{^}}add_inline_imm_neg_2.0_f64: 407; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 408; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 409; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -2.0 410; GCN: buffer_store_dwordx2 [[REG]] 411define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) { 412 %y = fadd double %x, -2.0 413 store double %y, double addrspace(1)* %out 414 ret void 415} 416 417; GCN-LABEL: {{^}}add_inline_imm_4.0_f64: 418; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 419; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 420; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 4.0 421; GCN: buffer_store_dwordx2 [[REG]] 422define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) { 423 %y = fadd double %x, 4.0 424 store double %y, double addrspace(1)* %out 425 ret void 426} 427 428; GCN-LABEL: {{^}}add_inline_imm_neg_4.0_f64: 429; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 430; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 431; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -4.0 432; GCN: buffer_store_dwordx2 [[REG]] 433define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) { 434 %y = fadd double %x, -4.0 435 store double %y, double addrspace(1)* %out 436 ret void 437} 438 439; GCN-LABEL: {{^}}add_inline_imm_inv_2pi_f64: 440; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 441; SI-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0x6dc9c882 442; SI-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fc45f30 443; SI: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 444 445; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 446; VI: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.15915494{{$}} 447; VI: buffer_store_dwordx2 [[REG]] 448define void @add_inline_imm_inv_2pi_f64(double addrspace(1)* %out, double %x) { 449 %y = fadd double %x, 0x3fc45f306dc9c882 450 store double %y, double addrspace(1)* %out 451 ret void 452} 453 454; GCN-LABEL: {{^}}add_m_inv_2pi_f64: 455; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0x6dc9c882 456; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfc45f30 457; GCN: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 458define void @add_m_inv_2pi_f64(double addrspace(1)* %out, double %x) { 459 %y = fadd double %x, 0xbfc45f306dc9c882 460 store double %y, double addrspace(1)* %out 461 ret void 462} 463 464; GCN-LABEL: {{^}}add_inline_imm_1_f64: 465; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 466; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 467; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1{{$}} 468; GCN: buffer_store_dwordx2 [[REG]] 469define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) { 470 %y = fadd double %x, 0x0000000000000001 471 store double %y, double addrspace(1)* %out 472 ret void 473} 474 475; GCN-LABEL: {{^}}add_inline_imm_2_f64: 476; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 477; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 478; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 2{{$}} 479; GCN: buffer_store_dwordx2 [[REG]] 480define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) { 481 %y = fadd double %x, 0x0000000000000002 482 store double %y, double addrspace(1)* %out 483 ret void 484} 485 486; GCN-LABEL: {{^}}add_inline_imm_16_f64: 487; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 488; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 489; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 16 490; GCN: buffer_store_dwordx2 [[REG]] 491define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) { 492 %y = fadd double %x, 0x0000000000000010 493 store double %y, double addrspace(1)* %out 494 ret void 495} 496 497; GCN-LABEL: {{^}}add_inline_imm_neg_1_f64: 498; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 499; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 500; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -1 501; GCN: buffer_store_dwordx2 [[REG]] 502define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) { 503 %y = fadd double %x, 0xffffffffffffffff 504 store double %y, double addrspace(1)* %out 505 ret void 506} 507 508; GCN-LABEL: {{^}}add_inline_imm_neg_2_f64: 509; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 510; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 511; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -2 512; GCN: buffer_store_dwordx2 [[REG]] 513define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) { 514 %y = fadd double %x, 0xfffffffffffffffe 515 store double %y, double addrspace(1)* %out 516 ret void 517} 518 519; GCN-LABEL: {{^}}add_inline_imm_neg_16_f64: 520; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 521; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 522; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -16 523; GCN: buffer_store_dwordx2 [[REG]] 524define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) { 525 %y = fadd double %x, 0xfffffffffffffff0 526 store double %y, double addrspace(1)* %out 527 ret void 528} 529 530; GCN-LABEL: {{^}}add_inline_imm_63_f64: 531; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 532; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 533; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 63 534; GCN: buffer_store_dwordx2 [[REG]] 535define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) { 536 %y = fadd double %x, 0x000000000000003F 537 store double %y, double addrspace(1)* %out 538 ret void 539} 540 541; GCN-LABEL: {{^}}add_inline_imm_64_f64: 542; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb 543; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c 544; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 64 545; GCN: buffer_store_dwordx2 [[REG]] 546define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) { 547 %y = fadd double %x, 0x0000000000000040 548 store double %y, double addrspace(1)* %out 549 ret void 550} 551 552 553; GCN-LABEL: {{^}}store_inline_imm_0.0_f64: 554; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0 555; GCN: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], v[[LO_VREG]]{{$}} 556; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 557define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) { 558 store double 0.0, double addrspace(1)* %out 559 ret void 560} 561 562 563; GCN-LABEL: {{^}}store_literal_imm_neg_0.0_f64: 564; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 565; GCN-DAG: v_bfrev_b32_e32 v[[HI_VREG:[0-9]+]], 1{{$}} 566; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 567define void @store_literal_imm_neg_0.0_f64(double addrspace(1)* %out) { 568 store double -0.0, double addrspace(1)* %out 569 ret void 570} 571 572; GCN-LABEL: {{^}}store_inline_imm_0.5_f64: 573; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 574; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fe00000 575; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 576define void @store_inline_imm_0.5_f64(double addrspace(1)* %out) { 577 store double 0.5, double addrspace(1)* %out 578 ret void 579} 580 581; GCN-LABEL: {{^}}store_inline_imm_m_0.5_f64: 582; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 583; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfe00000 584; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 585define void @store_inline_imm_m_0.5_f64(double addrspace(1)* %out) { 586 store double -0.5, double addrspace(1)* %out 587 ret void 588} 589 590; GCN-LABEL: {{^}}store_inline_imm_1.0_f64: 591; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 592; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3ff00000 593; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 594define void @store_inline_imm_1.0_f64(double addrspace(1)* %out) { 595 store double 1.0, double addrspace(1)* %out 596 ret void 597} 598 599; GCN-LABEL: {{^}}store_inline_imm_m_1.0_f64: 600; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 601; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbff00000 602; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 603define void @store_inline_imm_m_1.0_f64(double addrspace(1)* %out) { 604 store double -1.0, double addrspace(1)* %out 605 ret void 606} 607 608; GCN-LABEL: {{^}}store_inline_imm_2.0_f64: 609; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 610; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 2.0 611; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 612define void @store_inline_imm_2.0_f64(double addrspace(1)* %out) { 613 store double 2.0, double addrspace(1)* %out 614 ret void 615} 616 617; GCN-LABEL: {{^}}store_inline_imm_m_2.0_f64: 618; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 619; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], -2.0 620; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 621define void @store_inline_imm_m_2.0_f64(double addrspace(1)* %out) { 622 store double -2.0, double addrspace(1)* %out 623 ret void 624} 625 626; GCN-LABEL: {{^}}store_inline_imm_4.0_f64: 627; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 628; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40100000 629; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 630define void @store_inline_imm_4.0_f64(double addrspace(1)* %out) { 631 store double 4.0, double addrspace(1)* %out 632 ret void 633} 634 635; GCN-LABEL: {{^}}store_inline_imm_m_4.0_f64: 636; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 637; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xc0100000 638; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 639define void @store_inline_imm_m_4.0_f64(double addrspace(1)* %out) { 640 store double -4.0, double addrspace(1)* %out 641 ret void 642} 643 644; GCN-LABEL: {{^}}store_inv_2pi_f64: 645; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0x6dc9c882 646; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fc45f30 647; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 648define void @store_inv_2pi_f64(double addrspace(1)* %out) { 649 store double 0x3fc45f306dc9c882, double addrspace(1)* %out 650 ret void 651} 652 653; GCN-LABEL: {{^}}store_inline_imm_m_inv_2pi_f64: 654; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0x6dc9c882 655; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfc45f30 656; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 657define void @store_inline_imm_m_inv_2pi_f64(double addrspace(1)* %out) { 658 store double 0xbfc45f306dc9c882, double addrspace(1)* %out 659 ret void 660} 661 662; GCN-LABEL: {{^}}store_literal_imm_f64: 663; GCN-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} 664; GCN-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40b00000 665; GCN: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} 666define void @store_literal_imm_f64(double addrspace(1)* %out) { 667 store double 4096.0, double addrspace(1)* %out 668 ret void 669} 670