1; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
2
3target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
4target triple = "amdgcn--amdpal"
5
6; The first image store and the second image load use the same descriptor and
7; the same coordinate. Check that they do not get swapped by the machine
8; instruction scheduler.
9
10; GCN-LABEL: {{^}}_amdgpu_cs_main:
11; GCN: image_load
12; GCN: image_store
13; GCN: image_load
14; GCN: image_store
15
16define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <3 x i32> inreg %arg3, i32 inreg %arg4, <3 x i32> %arg5) local_unnamed_addr #0 {
17.entry:
18  %tmp = call i64 @llvm.amdgcn.s.getpc() #1
19  %tmp6 = bitcast i64 %tmp to <2 x i32>
20  %.0.vec.insert = insertelement <2 x i32> undef, i32 %arg2, i32 0
21  %.4.vec.insert = shufflevector <2 x i32> %.0.vec.insert, <2 x i32> %tmp6, <2 x i32> <i32 0, i32 3>
22  %tmp7 = bitcast <2 x i32> %.4.vec.insert to i64
23  %tmp8 = inttoptr i64 %tmp7 to [4294967295 x i8] addrspace(2)*
24  %tmp9 = add <3 x i32> %arg3, %arg5
25  %tmp10 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(2)* %tmp8, i64 0, i64 32
26  %tmp11 = bitcast i8 addrspace(2)* %tmp10 to <8 x i32> addrspace(2)*, !amdgpu.uniform !0
27  %tmp12 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp11, align 16
28  %tmp13 = shufflevector <3 x i32> %tmp9, <3 x i32> undef, <2 x i32> <i32 0, i32 1>
29  %tmp14 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp13, <8 x i32> %tmp12, i32 15, i1 false, i1 false, i1 false, i1 false) #0
30  %tmp15 = inttoptr i64 %tmp7 to <8 x i32> addrspace(2)*
31  %tmp16 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp15, align 16
32  call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %tmp14, <2 x i32> %tmp13, <8 x i32> %tmp16, i32 15, i1 false, i1 false, i1 false, i1 false) #0
33  %tmp17 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp15, align 16
34  %tmp18 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp13, <8 x i32> %tmp17, i32 15, i1 false, i1 false, i1 false, i1 false) #0
35  %tmp19 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(2)* %tmp8, i64 0, i64 64
36  %tmp20 = bitcast i8 addrspace(2)* %tmp19 to <8 x i32> addrspace(2)*, !amdgpu.uniform !0
37  %tmp21 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp20, align 16
38  call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %tmp18, <2 x i32> %tmp13, <8 x i32> %tmp21, i32 15, i1 false, i1 false, i1 false, i1 false) #0
39  ret void
40}
41
42; Function Attrs: nounwind readnone speculatable
43declare i64 @llvm.amdgcn.s.getpc() #1
44
45; Function Attrs: nounwind readonly
46declare <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
47
48; Function Attrs: nounwind writeonly
49declare void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float>, <2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #3
50
51attributes #0 = { nounwind }
52attributes #1 = { nounwind readnone speculatable }
53attributes #2 = { nounwind readonly }
54attributes #3 = { nounwind writeonly }
55
56!0 = !{}
57