1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
4; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-UNPACKED %s
5
6define amdgpu_ps void @load_1d_f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) {
7; GFX9-LABEL: load_1d_f16_tfe_dmask0:
8; GFX9:       ; %bb.0:
9; GFX9-NEXT:    v_mov_b32_e32 v1, 0
10; GFX9-NEXT:    s_mov_b32 s11, s9
11; GFX9-NEXT:    s_mov_b32 s10, s8
12; GFX9-NEXT:    s_mov_b32 s9, s7
13; GFX9-NEXT:    s_mov_b32 s8, s6
14; GFX9-NEXT:    s_mov_b32 s7, s5
15; GFX9-NEXT:    s_mov_b32 s6, s4
16; GFX9-NEXT:    s_mov_b32 s5, s3
17; GFX9-NEXT:    s_mov_b32 s4, s2
18; GFX9-NEXT:    v_mov_b32_e32 v2, v1
19; GFX9-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
20; GFX9-NEXT:    s_waitcnt vmcnt(0)
21; GFX9-NEXT:    global_store_short v[0:1], v1, off
22; GFX9-NEXT:    global_store_dword v[0:1], v2, off
23; GFX9-NEXT:    s_endpgm
24;
25; GFX10-LABEL: load_1d_f16_tfe_dmask0:
26; GFX10:       ; %bb.0:
27; GFX10-NEXT:    v_mov_b32_e32 v1, 0
28; GFX10-NEXT:    s_mov_b32 s11, s9
29; GFX10-NEXT:    s_mov_b32 s10, s8
30; GFX10-NEXT:    s_mov_b32 s9, s7
31; GFX10-NEXT:    s_mov_b32 s8, s6
32; GFX10-NEXT:    s_mov_b32 s7, s5
33; GFX10-NEXT:    s_mov_b32 s6, s4
34; GFX10-NEXT:    s_mov_b32 s5, s3
35; GFX10-NEXT:    s_mov_b32 s4, s2
36; GFX10-NEXT:    v_mov_b32_e32 v2, v1
37; GFX10-NEXT:    ; implicit-def: $vcc_hi
38; GFX10-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
39; GFX10-NEXT:    s_waitcnt vmcnt(0)
40; GFX10-NEXT:    global_store_short v[0:1], v1, off
41; GFX10-NEXT:    global_store_dword v[0:1], v2, off
42; GFX10-NEXT:    s_endpgm
43;
44; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask0:
45; GFX8-UNPACKED:       ; %bb.0:
46; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v1, 0
47; GFX8-UNPACKED-NEXT:    s_mov_b32 s11, s9
48; GFX8-UNPACKED-NEXT:    s_mov_b32 s10, s8
49; GFX8-UNPACKED-NEXT:    s_mov_b32 s9, s7
50; GFX8-UNPACKED-NEXT:    s_mov_b32 s8, s6
51; GFX8-UNPACKED-NEXT:    s_mov_b32 s7, s5
52; GFX8-UNPACKED-NEXT:    s_mov_b32 s6, s4
53; GFX8-UNPACKED-NEXT:    s_mov_b32 s5, s3
54; GFX8-UNPACKED-NEXT:    s_mov_b32 s4, s2
55; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v2, v1
56; GFX8-UNPACKED-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
57; GFX8-UNPACKED-NEXT:    s_waitcnt vmcnt(0)
58; GFX8-UNPACKED-NEXT:    flat_store_short v[0:1], v1
59; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v2
60; GFX8-UNPACKED-NEXT:    s_endpgm
61  %v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
62  %v.data = extractvalue { half, i32 } %v, 0
63  %v.err = extractvalue { half, i32 } %v, 1
64  store volatile half %v.data, half addrspace(1)* undef
65  store volatile i32 %v.err, i32 addrspace(1)* undef
66  ret void
67}
68
69define amdgpu_ps void @load_1d_f16_tfe_dmask1(<8 x i32> inreg %rsrc, i32 %s) {
70; GFX9-LABEL: load_1d_f16_tfe_dmask1:
71; GFX9:       ; %bb.0:
72; GFX9-NEXT:    v_mov_b32_e32 v1, 0
73; GFX9-NEXT:    s_mov_b32 s11, s9
74; GFX9-NEXT:    s_mov_b32 s10, s8
75; GFX9-NEXT:    s_mov_b32 s9, s7
76; GFX9-NEXT:    s_mov_b32 s8, s6
77; GFX9-NEXT:    s_mov_b32 s7, s5
78; GFX9-NEXT:    s_mov_b32 s6, s4
79; GFX9-NEXT:    s_mov_b32 s5, s3
80; GFX9-NEXT:    s_mov_b32 s4, s2
81; GFX9-NEXT:    v_mov_b32_e32 v2, v1
82; GFX9-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
83; GFX9-NEXT:    s_waitcnt vmcnt(0)
84; GFX9-NEXT:    global_store_short v[0:1], v1, off
85; GFX9-NEXT:    global_store_dword v[0:1], v2, off
86; GFX9-NEXT:    s_endpgm
87;
88; GFX10-LABEL: load_1d_f16_tfe_dmask1:
89; GFX10:       ; %bb.0:
90; GFX10-NEXT:    v_mov_b32_e32 v1, 0
91; GFX10-NEXT:    s_mov_b32 s11, s9
92; GFX10-NEXT:    s_mov_b32 s10, s8
93; GFX10-NEXT:    s_mov_b32 s9, s7
94; GFX10-NEXT:    s_mov_b32 s8, s6
95; GFX10-NEXT:    s_mov_b32 s7, s5
96; GFX10-NEXT:    s_mov_b32 s6, s4
97; GFX10-NEXT:    s_mov_b32 s5, s3
98; GFX10-NEXT:    s_mov_b32 s4, s2
99; GFX10-NEXT:    v_mov_b32_e32 v2, v1
100; GFX10-NEXT:    ; implicit-def: $vcc_hi
101; GFX10-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
102; GFX10-NEXT:    s_waitcnt vmcnt(0)
103; GFX10-NEXT:    global_store_short v[0:1], v1, off
104; GFX10-NEXT:    global_store_dword v[0:1], v2, off
105; GFX10-NEXT:    s_endpgm
106;
107; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask1:
108; GFX8-UNPACKED:       ; %bb.0:
109; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v1, 0
110; GFX8-UNPACKED-NEXT:    s_mov_b32 s11, s9
111; GFX8-UNPACKED-NEXT:    s_mov_b32 s10, s8
112; GFX8-UNPACKED-NEXT:    s_mov_b32 s9, s7
113; GFX8-UNPACKED-NEXT:    s_mov_b32 s8, s6
114; GFX8-UNPACKED-NEXT:    s_mov_b32 s7, s5
115; GFX8-UNPACKED-NEXT:    s_mov_b32 s6, s4
116; GFX8-UNPACKED-NEXT:    s_mov_b32 s5, s3
117; GFX8-UNPACKED-NEXT:    s_mov_b32 s4, s2
118; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v2, v1
119; GFX8-UNPACKED-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
120; GFX8-UNPACKED-NEXT:    s_waitcnt vmcnt(0)
121; GFX8-UNPACKED-NEXT:    flat_store_short v[0:1], v1
122; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v2
123; GFX8-UNPACKED-NEXT:    s_endpgm
124  %v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
125  %v.data = extractvalue { half, i32 } %v, 0
126  %v.err = extractvalue { half, i32 } %v, 1
127  store volatile half %v.data, half addrspace(1)* undef
128  store volatile i32 %v.err, i32 addrspace(1)* undef
129  ret void
130}
131
132define amdgpu_ps void @load_1d_v2f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) {
133; GFX9-LABEL: load_1d_v2f16_tfe_dmask0:
134; GFX9:       ; %bb.0:
135; GFX9-NEXT:    v_mov_b32_e32 v1, 0
136; GFX9-NEXT:    s_mov_b32 s11, s9
137; GFX9-NEXT:    s_mov_b32 s10, s8
138; GFX9-NEXT:    s_mov_b32 s9, s7
139; GFX9-NEXT:    s_mov_b32 s8, s6
140; GFX9-NEXT:    s_mov_b32 s7, s5
141; GFX9-NEXT:    s_mov_b32 s6, s4
142; GFX9-NEXT:    s_mov_b32 s5, s3
143; GFX9-NEXT:    s_mov_b32 s4, s2
144; GFX9-NEXT:    v_mov_b32_e32 v2, v1
145; GFX9-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
146; GFX9-NEXT:    s_waitcnt vmcnt(0)
147; GFX9-NEXT:    global_store_dword v[0:1], v1, off
148; GFX9-NEXT:    global_store_dword v[0:1], v2, off
149; GFX9-NEXT:    s_endpgm
150;
151; GFX10-LABEL: load_1d_v2f16_tfe_dmask0:
152; GFX10:       ; %bb.0:
153; GFX10-NEXT:    v_mov_b32_e32 v1, 0
154; GFX10-NEXT:    s_mov_b32 s11, s9
155; GFX10-NEXT:    s_mov_b32 s10, s8
156; GFX10-NEXT:    s_mov_b32 s9, s7
157; GFX10-NEXT:    s_mov_b32 s8, s6
158; GFX10-NEXT:    s_mov_b32 s7, s5
159; GFX10-NEXT:    s_mov_b32 s6, s4
160; GFX10-NEXT:    s_mov_b32 s5, s3
161; GFX10-NEXT:    s_mov_b32 s4, s2
162; GFX10-NEXT:    v_mov_b32_e32 v2, v1
163; GFX10-NEXT:    ; implicit-def: $vcc_hi
164; GFX10-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
165; GFX10-NEXT:    s_waitcnt vmcnt(0)
166; GFX10-NEXT:    global_store_dword v[0:1], v1, off
167; GFX10-NEXT:    global_store_dword v[0:1], v2, off
168; GFX10-NEXT:    s_endpgm
169;
170; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask0:
171; GFX8-UNPACKED:       ; %bb.0:
172; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v1, 0
173; GFX8-UNPACKED-NEXT:    s_mov_b32 s11, s9
174; GFX8-UNPACKED-NEXT:    s_mov_b32 s10, s8
175; GFX8-UNPACKED-NEXT:    s_mov_b32 s9, s7
176; GFX8-UNPACKED-NEXT:    s_mov_b32 s8, s6
177; GFX8-UNPACKED-NEXT:    s_mov_b32 s7, s5
178; GFX8-UNPACKED-NEXT:    s_mov_b32 s6, s4
179; GFX8-UNPACKED-NEXT:    s_mov_b32 s5, s3
180; GFX8-UNPACKED-NEXT:    s_mov_b32 s4, s2
181; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v2, v1
182; GFX8-UNPACKED-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
183; GFX8-UNPACKED-NEXT:    s_waitcnt vmcnt(0)
184; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v1
185; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v2
186; GFX8-UNPACKED-NEXT:    s_endpgm
187  %v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
188  %v.data = extractvalue { <2 x half>, i32 } %v, 0
189  %v.err = extractvalue { <2 x half>, i32 } %v, 1
190  store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
191  store volatile i32 %v.err, i32 addrspace(1)* undef
192  ret void
193}
194
195define amdgpu_ps void @load_1d_v2f16_tfe_dmask1(<8 x i32> inreg %rsrc, i32 %s) {
196; GFX9-LABEL: load_1d_v2f16_tfe_dmask1:
197; GFX9:       ; %bb.0:
198; GFX9-NEXT:    v_mov_b32_e32 v1, 0
199; GFX9-NEXT:    s_mov_b32 s11, s9
200; GFX9-NEXT:    s_mov_b32 s10, s8
201; GFX9-NEXT:    s_mov_b32 s9, s7
202; GFX9-NEXT:    s_mov_b32 s8, s6
203; GFX9-NEXT:    s_mov_b32 s7, s5
204; GFX9-NEXT:    s_mov_b32 s6, s4
205; GFX9-NEXT:    s_mov_b32 s5, s3
206; GFX9-NEXT:    s_mov_b32 s4, s2
207; GFX9-NEXT:    v_mov_b32_e32 v2, v1
208; GFX9-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
209; GFX9-NEXT:    s_waitcnt vmcnt(0)
210; GFX9-NEXT:    global_store_dword v[0:1], v1, off
211; GFX9-NEXT:    global_store_dword v[0:1], v2, off
212; GFX9-NEXT:    s_endpgm
213;
214; GFX10-LABEL: load_1d_v2f16_tfe_dmask1:
215; GFX10:       ; %bb.0:
216; GFX10-NEXT:    v_mov_b32_e32 v1, 0
217; GFX10-NEXT:    s_mov_b32 s11, s9
218; GFX10-NEXT:    s_mov_b32 s10, s8
219; GFX10-NEXT:    s_mov_b32 s9, s7
220; GFX10-NEXT:    s_mov_b32 s8, s6
221; GFX10-NEXT:    s_mov_b32 s7, s5
222; GFX10-NEXT:    s_mov_b32 s6, s4
223; GFX10-NEXT:    s_mov_b32 s5, s3
224; GFX10-NEXT:    s_mov_b32 s4, s2
225; GFX10-NEXT:    v_mov_b32_e32 v2, v1
226; GFX10-NEXT:    ; implicit-def: $vcc_hi
227; GFX10-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
228; GFX10-NEXT:    s_waitcnt vmcnt(0)
229; GFX10-NEXT:    global_store_dword v[0:1], v1, off
230; GFX10-NEXT:    global_store_dword v[0:1], v2, off
231; GFX10-NEXT:    s_endpgm
232;
233; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask1:
234; GFX8-UNPACKED:       ; %bb.0:
235; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v1, 0
236; GFX8-UNPACKED-NEXT:    s_mov_b32 s11, s9
237; GFX8-UNPACKED-NEXT:    s_mov_b32 s10, s8
238; GFX8-UNPACKED-NEXT:    s_mov_b32 s9, s7
239; GFX8-UNPACKED-NEXT:    s_mov_b32 s8, s6
240; GFX8-UNPACKED-NEXT:    s_mov_b32 s7, s5
241; GFX8-UNPACKED-NEXT:    s_mov_b32 s6, s4
242; GFX8-UNPACKED-NEXT:    s_mov_b32 s5, s3
243; GFX8-UNPACKED-NEXT:    s_mov_b32 s4, s2
244; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v2, v1
245; GFX8-UNPACKED-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
246; GFX8-UNPACKED-NEXT:    s_waitcnt vmcnt(0)
247; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v1
248; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v2
249; GFX8-UNPACKED-NEXT:    s_endpgm
250  %v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
251  %v.data = extractvalue { <2 x half>, i32 } %v, 0
252  %v.err = extractvalue { <2 x half>, i32 } %v, 1
253  store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
254  store volatile i32 %v.err, i32 addrspace(1)* undef
255  ret void
256}
257
258define amdgpu_ps void @load_1d_v2f16_tfe_dmask3(<8 x i32> inreg %rsrc, i32 %s) {
259; GFX9-LABEL: load_1d_v2f16_tfe_dmask3:
260; GFX9:       ; %bb.0:
261; GFX9-NEXT:    v_mov_b32_e32 v1, 0
262; GFX9-NEXT:    s_mov_b32 s11, s9
263; GFX9-NEXT:    s_mov_b32 s10, s8
264; GFX9-NEXT:    s_mov_b32 s9, s7
265; GFX9-NEXT:    s_mov_b32 s8, s6
266; GFX9-NEXT:    s_mov_b32 s7, s5
267; GFX9-NEXT:    s_mov_b32 s6, s4
268; GFX9-NEXT:    s_mov_b32 s5, s3
269; GFX9-NEXT:    s_mov_b32 s4, s2
270; GFX9-NEXT:    v_mov_b32_e32 v2, v1
271; GFX9-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x3 unorm tfe d16
272; GFX9-NEXT:    s_waitcnt vmcnt(0)
273; GFX9-NEXT:    global_store_dword v[0:1], v1, off
274; GFX9-NEXT:    global_store_dword v[0:1], v2, off
275; GFX9-NEXT:    s_endpgm
276;
277; GFX10-LABEL: load_1d_v2f16_tfe_dmask3:
278; GFX10:       ; %bb.0:
279; GFX10-NEXT:    v_mov_b32_e32 v1, 0
280; GFX10-NEXT:    s_mov_b32 s11, s9
281; GFX10-NEXT:    s_mov_b32 s10, s8
282; GFX10-NEXT:    s_mov_b32 s9, s7
283; GFX10-NEXT:    s_mov_b32 s8, s6
284; GFX10-NEXT:    s_mov_b32 s7, s5
285; GFX10-NEXT:    s_mov_b32 s6, s4
286; GFX10-NEXT:    s_mov_b32 s5, s3
287; GFX10-NEXT:    s_mov_b32 s4, s2
288; GFX10-NEXT:    v_mov_b32_e32 v2, v1
289; GFX10-NEXT:    ; implicit-def: $vcc_hi
290; GFX10-NEXT:    image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16
291; GFX10-NEXT:    s_waitcnt vmcnt(0)
292; GFX10-NEXT:    global_store_dword v[0:1], v1, off
293; GFX10-NEXT:    global_store_dword v[0:1], v2, off
294; GFX10-NEXT:    s_endpgm
295;
296; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask3:
297; GFX8-UNPACKED:       ; %bb.0:
298; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v1, 0
299; GFX8-UNPACKED-NEXT:    s_mov_b32 s11, s9
300; GFX8-UNPACKED-NEXT:    s_mov_b32 s10, s8
301; GFX8-UNPACKED-NEXT:    s_mov_b32 s9, s7
302; GFX8-UNPACKED-NEXT:    s_mov_b32 s8, s6
303; GFX8-UNPACKED-NEXT:    s_mov_b32 s7, s5
304; GFX8-UNPACKED-NEXT:    s_mov_b32 s6, s4
305; GFX8-UNPACKED-NEXT:    s_mov_b32 s5, s3
306; GFX8-UNPACKED-NEXT:    s_mov_b32 s4, s2
307; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v2, v1
308; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v3, v1
309; GFX8-UNPACKED-NEXT:    image_load v[1:3], v0, s[4:11] dmask:0x3 unorm tfe d16
310; GFX8-UNPACKED-NEXT:    s_waitcnt vmcnt(0)
311; GFX8-UNPACKED-NEXT:    v_lshlrev_b32_e32 v0, 16, v2
312; GFX8-UNPACKED-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
313; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v0
314; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v3
315; GFX8-UNPACKED-NEXT:    s_endpgm
316  %v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 3, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
317  %v.data = extractvalue { <2 x half>, i32 } %v, 0
318  %v.err = extractvalue { <2 x half>, i32 } %v, 1
319  store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
320  store volatile i32 %v.err, i32 addrspace(1)* undef
321  ret void
322}
323
324; define amdgpu_ps void @load_1d_v3f16_tfe_dmask7(<8 x i32> inreg %rsrc, i32 %s) {
325;   %v = call { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
326;   %v.data = extractvalue { <3 x half>, i32 } %v, 0
327;   %v.err = extractvalue { <3 x half>, i32 } %v, 1
328;   store volatile <3 x half> %v.data, <3 x half> addrspace(1)* undef
329;   store volatile i32 %v.err, i32 addrspace(1)* undef
330;   ret void
331; }
332
333define amdgpu_ps void @load_1d_v4f16_tfe_dmask15(<8 x i32> inreg %rsrc, i32 %s) {
334; GFX9-LABEL: load_1d_v4f16_tfe_dmask15:
335; GFX9:       ; %bb.0:
336; GFX9-NEXT:    v_mov_b32_e32 v1, 0
337; GFX9-NEXT:    s_mov_b32 s11, s9
338; GFX9-NEXT:    s_mov_b32 s10, s8
339; GFX9-NEXT:    s_mov_b32 s9, s7
340; GFX9-NEXT:    s_mov_b32 s8, s6
341; GFX9-NEXT:    s_mov_b32 s7, s5
342; GFX9-NEXT:    s_mov_b32 s6, s4
343; GFX9-NEXT:    s_mov_b32 s5, s3
344; GFX9-NEXT:    s_mov_b32 s4, s2
345; GFX9-NEXT:    v_mov_b32_e32 v2, v1
346; GFX9-NEXT:    v_mov_b32_e32 v3, v1
347; GFX9-NEXT:    image_load v[1:3], v0, s[4:11] dmask:0xf unorm tfe d16
348; GFX9-NEXT:    s_waitcnt vmcnt(0)
349; GFX9-NEXT:    global_store_dwordx2 v[0:1], v[1:2], off
350; GFX9-NEXT:    global_store_dword v[0:1], v3, off
351; GFX9-NEXT:    s_endpgm
352;
353; GFX10-LABEL: load_1d_v4f16_tfe_dmask15:
354; GFX10:       ; %bb.0:
355; GFX10-NEXT:    v_mov_b32_e32 v1, 0
356; GFX10-NEXT:    s_mov_b32 s11, s9
357; GFX10-NEXT:    s_mov_b32 s10, s8
358; GFX10-NEXT:    s_mov_b32 s9, s7
359; GFX10-NEXT:    s_mov_b32 s8, s6
360; GFX10-NEXT:    s_mov_b32 s7, s5
361; GFX10-NEXT:    s_mov_b32 s6, s4
362; GFX10-NEXT:    s_mov_b32 s5, s3
363; GFX10-NEXT:    s_mov_b32 s4, s2
364; GFX10-NEXT:    v_mov_b32_e32 v2, v1
365; GFX10-NEXT:    v_mov_b32_e32 v3, v1
366; GFX10-NEXT:    ; implicit-def: $vcc_hi
367; GFX10-NEXT:    image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16
368; GFX10-NEXT:    s_waitcnt vmcnt(0)
369; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[1:2], off
370; GFX10-NEXT:    global_store_dword v[0:1], v3, off
371; GFX10-NEXT:    s_endpgm
372;
373; GFX8-UNPACKED-LABEL: load_1d_v4f16_tfe_dmask15:
374; GFX8-UNPACKED:       ; %bb.0:
375; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v1, 0
376; GFX8-UNPACKED-NEXT:    s_mov_b32 s11, s9
377; GFX8-UNPACKED-NEXT:    s_mov_b32 s10, s8
378; GFX8-UNPACKED-NEXT:    s_mov_b32 s9, s7
379; GFX8-UNPACKED-NEXT:    s_mov_b32 s8, s6
380; GFX8-UNPACKED-NEXT:    s_mov_b32 s7, s5
381; GFX8-UNPACKED-NEXT:    s_mov_b32 s6, s4
382; GFX8-UNPACKED-NEXT:    s_mov_b32 s5, s3
383; GFX8-UNPACKED-NEXT:    s_mov_b32 s4, s2
384; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v2, v1
385; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v3, v1
386; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v4, v1
387; GFX8-UNPACKED-NEXT:    v_mov_b32_e32 v5, v1
388; GFX8-UNPACKED-NEXT:    image_load v[1:5], v0, s[4:11] dmask:0xf unorm tfe d16
389; GFX8-UNPACKED-NEXT:    s_waitcnt vmcnt(0)
390; GFX8-UNPACKED-NEXT:    v_lshlrev_b32_e32 v0, 16, v4
391; GFX8-UNPACKED-NEXT:    v_lshlrev_b32_e32 v4, 16, v2
392; GFX8-UNPACKED-NEXT:    v_or_b32_sdwa v2, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
393; GFX8-UNPACKED-NEXT:    v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
394; GFX8-UNPACKED-NEXT:    flat_store_dwordx2 v[0:1], v[1:2]
395; GFX8-UNPACKED-NEXT:    flat_store_dword v[0:1], v5
396; GFX8-UNPACKED-NEXT:    s_endpgm
397  %v = call { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
398  %v.data = extractvalue { <4 x half>, i32 } %v, 0
399  %v.err = extractvalue { <4 x half>, i32 } %v, 1
400  store volatile <4 x half> %v.data, <4 x half> addrspace(1)* undef
401  store volatile i32 %v.err, i32 addrspace(1)* undef
402  ret void
403}
404
405declare { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
406declare { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
407declare { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
408declare { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
409
410attributes #0 = { nounwind readonly }
411