1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s
4
5define amdgpu_kernel void @udiv32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
6; GFX9-LABEL: udiv32_invariant_denom:
7; GFX9:       ; %bb.0: ; %bb
8; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
9; GFX9-NEXT:    s_mov_b64 s[2:3], 0
10; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
11; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
12; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s4
13; GFX9-NEXT:    s_sub_i32 s5, 0, s4
14; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
15; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
16; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
17; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v0
18; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
19; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
20; GFX9-NEXT:    v_mov_b32_e32 v1, 0
21; GFX9-NEXT:  BB0_1: ; %bb3
22; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
23; GFX9-NEXT:    v_mul_lo_u32 v2, s3, v0
24; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
25; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
26; GFX9-NEXT:    v_mul_lo_u32 v3, s5, v2
27; GFX9-NEXT:    v_not_b32_e32 v5, v2
28; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v5
29; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
30; GFX9-NEXT:    v_add_u32_e32 v3, s2, v3
31; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
32; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
33; GFX9-NEXT:    v_add_u32_e32 v4, s2, v5
34; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
35; GFX9-NEXT:    s_add_u32 s2, s2, 1
36; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
37; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
38; GFX9-NEXT:    s_addc_u32 s3, s3, 0
39; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
40; GFX9-NEXT:    global_store_dword v1, v2, s[0:1]
41; GFX9-NEXT:    s_add_u32 s0, s0, 4
42; GFX9-NEXT:    s_addc_u32 s1, s1, 0
43; GFX9-NEXT:    s_cmpk_eq_i32 s2, 0x400
44; GFX9-NEXT:    s_cbranch_scc0 BB0_1
45; GFX9-NEXT:  ; %bb.2: ; %bb2
46; GFX9-NEXT:    s_endpgm
47;
48; GFX10-LABEL: udiv32_invariant_denom:
49; GFX10:       ; %bb.0: ; %bb
50; GFX10-NEXT:    s_load_dword s4, s[0:1], 0x2c
51; GFX10-NEXT:    s_mov_b64 s[2:3], 0
52; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
53; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
54; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s4
55; GFX10-NEXT:    s_sub_i32 s5, 0, s4
56; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
57; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
58; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
59; GFX10-NEXT:    v_mul_lo_u32 v1, s5, v0
60; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
61; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
62; GFX10-NEXT:    v_mov_b32_e32 v1, 0
63; GFX10-NEXT:  BB0_1: ; %bb3
64; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
65; GFX10-NEXT:    v_mul_lo_u32 v2, s3, v0
66; GFX10-NEXT:    v_mul_hi_u32 v3, s2, v0
67; GFX10-NEXT:    v_add_nc_u32_e32 v2, v3, v2
68; GFX10-NEXT:    v_not_b32_e32 v3, v2
69; GFX10-NEXT:    v_mul_lo_u32 v4, s5, v2
70; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v2
71; GFX10-NEXT:    v_mul_lo_u32 v3, s4, v3
72; GFX10-NEXT:    v_add_nc_u32_e32 v4, s2, v4
73; GFX10-NEXT:    v_add_nc_u32_e32 v3, s2, v3
74; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v4
75; GFX10-NEXT:    s_add_u32 s2, s2, 1
76; GFX10-NEXT:    s_addc_u32 s3, s3, 0
77; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo
78; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
79; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v2
80; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v3
81; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
82; GFX10-NEXT:    global_store_dword v1, v2, s[0:1]
83; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
84; GFX10-NEXT:    s_add_u32 s0, s0, 4
85; GFX10-NEXT:    s_addc_u32 s1, s1, 0
86; GFX10-NEXT:    s_cmpk_eq_i32 s2, 0x400
87; GFX10-NEXT:    s_cbranch_scc0 BB0_1
88; GFX10-NEXT:  ; %bb.2: ; %bb2
89; GFX10-NEXT:    s_endpgm
90bb:
91  br label %bb3
92
93bb2:                                              ; preds = %bb3
94  ret void
95
96bb3:                                              ; preds = %bb3, %bb
97  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
98  %tmp4 = udiv i32 %tmp, %arg1
99  %tmp5 = zext i32 %tmp to i64
100  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
101  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
102  %tmp7 = add nuw nsw i32 %tmp, 1
103  %tmp8 = icmp eq i32 %tmp7, 1024
104  br i1 %tmp8, label %bb2, label %bb3
105}
106
107define amdgpu_kernel void @urem32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
108; GFX9-LABEL: urem32_invariant_denom:
109; GFX9:       ; %bb.0: ; %bb
110; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
111; GFX9-NEXT:    s_mov_b64 s[2:3], 0
112; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
113; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
114; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s4
115; GFX9-NEXT:    s_sub_i32 s5, 0, s4
116; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
117; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
118; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
119; GFX9-NEXT:    v_mul_lo_u32 v1, s5, v0
120; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
121; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
122; GFX9-NEXT:    v_mov_b32_e32 v1, 0
123; GFX9-NEXT:  BB1_1: ; %bb3
124; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
125; GFX9-NEXT:    v_mul_lo_u32 v2, s3, v0
126; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v0
127; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
128; GFX9-NEXT:    v_mul_lo_u32 v3, s5, v2
129; GFX9-NEXT:    v_not_b32_e32 v2, v2
130; GFX9-NEXT:    v_mul_lo_u32 v2, s4, v2
131; GFX9-NEXT:    v_add_u32_e32 v3, s2, v3
132; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3
133; GFX9-NEXT:    v_add_u32_e32 v2, s2, v2
134; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
135; GFX9-NEXT:    s_add_u32 s2, s2, 1
136; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v2
137; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v2
138; GFX9-NEXT:    s_addc_u32 s3, s3, 0
139; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
140; GFX9-NEXT:    global_store_dword v1, v2, s[0:1]
141; GFX9-NEXT:    s_add_u32 s0, s0, 4
142; GFX9-NEXT:    s_addc_u32 s1, s1, 0
143; GFX9-NEXT:    s_cmpk_eq_i32 s2, 0x400
144; GFX9-NEXT:    s_cbranch_scc0 BB1_1
145; GFX9-NEXT:  ; %bb.2: ; %bb2
146; GFX9-NEXT:    s_endpgm
147;
148; GFX10-LABEL: urem32_invariant_denom:
149; GFX10:       ; %bb.0: ; %bb
150; GFX10-NEXT:    s_load_dword s4, s[0:1], 0x2c
151; GFX10-NEXT:    s_mov_b64 s[2:3], 0
152; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
153; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
154; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s4
155; GFX10-NEXT:    s_sub_i32 s5, 0, s4
156; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
157; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
158; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
159; GFX10-NEXT:    v_mul_lo_u32 v1, s5, v0
160; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
161; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
162; GFX10-NEXT:    v_mov_b32_e32 v1, 0
163; GFX10-NEXT:  BB1_1: ; %bb3
164; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
165; GFX10-NEXT:    v_mul_lo_u32 v2, s3, v0
166; GFX10-NEXT:    v_mul_hi_u32 v3, s2, v0
167; GFX10-NEXT:    v_add_nc_u32_e32 v2, v3, v2
168; GFX10-NEXT:    v_not_b32_e32 v3, v2
169; GFX10-NEXT:    v_mul_lo_u32 v2, s5, v2
170; GFX10-NEXT:    v_mul_lo_u32 v3, s4, v3
171; GFX10-NEXT:    v_add_nc_u32_e32 v2, s2, v2
172; GFX10-NEXT:    v_add_nc_u32_e32 v3, s2, v3
173; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v2
174; GFX10-NEXT:    s_add_u32 s2, s2, 1
175; GFX10-NEXT:    s_addc_u32 s3, s3, 0
176; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
177; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v2
178; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v2
179; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
180; GFX10-NEXT:    global_store_dword v1, v2, s[0:1]
181; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
182; GFX10-NEXT:    s_add_u32 s0, s0, 4
183; GFX10-NEXT:    s_addc_u32 s1, s1, 0
184; GFX10-NEXT:    s_cmpk_eq_i32 s2, 0x400
185; GFX10-NEXT:    s_cbranch_scc0 BB1_1
186; GFX10-NEXT:  ; %bb.2: ; %bb2
187; GFX10-NEXT:    s_endpgm
188bb:
189  br label %bb3
190
191bb2:                                              ; preds = %bb3
192  ret void
193
194bb3:                                              ; preds = %bb3, %bb
195  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
196  %tmp4 = urem i32 %tmp, %arg1
197  %tmp5 = zext i32 %tmp to i64
198  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
199  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
200  %tmp7 = add nuw nsw i32 %tmp, 1
201  %tmp8 = icmp eq i32 %tmp7, 1024
202  br i1 %tmp8, label %bb2, label %bb3
203}
204
205define amdgpu_kernel void @sdiv32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
206; GFX9-LABEL: sdiv32_invariant_denom:
207; GFX9:       ; %bb.0: ; %bb
208; GFX9-NEXT:    s_load_dword s3, s[0:1], 0x2c
209; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
210; GFX9-NEXT:    s_ashr_i32 s2, s3, 31
211; GFX9-NEXT:    s_add_i32 s3, s3, s2
212; GFX9-NEXT:    s_xor_b32 s3, s3, s2
213; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
214; GFX9-NEXT:    s_sub_i32 s4, 0, s3
215; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
216; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
217; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
218; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
219; GFX9-NEXT:    v_mul_lo_u32 v1, s4, v0
220; GFX9-NEXT:    s_mov_b32 s4, 0
221; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
222; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
223; GFX9-NEXT:    v_mov_b32_e32 v1, 0
224; GFX9-NEXT:  BB2_1: ; %bb3
225; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
226; GFX9-NEXT:    v_mul_hi_u32 v2, s4, v0
227; GFX9-NEXT:    v_mul_lo_u32 v3, v2, s3
228; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
229; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3
230; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
231; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
232; GFX9-NEXT:    v_subrev_u32_e32 v4, s3, v3
233; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
234; GFX9-NEXT:    v_add_u32_e32 v4, 1, v2
235; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
236; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
237; GFX9-NEXT:    v_xor_b32_e32 v2, s2, v2
238; GFX9-NEXT:    s_add_i32 s4, s4, 1
239; GFX9-NEXT:    v_subrev_u32_e32 v2, s2, v2
240; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
241; GFX9-NEXT:    global_store_dword v1, v2, s[0:1]
242; GFX9-NEXT:    s_add_u32 s0, s0, 4
243; GFX9-NEXT:    s_addc_u32 s1, s1, 0
244; GFX9-NEXT:    s_cmpk_eq_i32 s4, 0x400
245; GFX9-NEXT:    s_cbranch_scc0 BB2_1
246; GFX9-NEXT:  ; %bb.2: ; %bb2
247; GFX9-NEXT:    s_endpgm
248;
249; GFX10-LABEL: sdiv32_invariant_denom:
250; GFX10:       ; %bb.0: ; %bb
251; GFX10-NEXT:    s_load_dword s3, s[0:1], 0x2c
252; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
253; GFX10-NEXT:    s_ashr_i32 s2, s3, 31
254; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
255; GFX10-NEXT:    s_add_i32 s3, s3, s2
256; GFX10-NEXT:    s_xor_b32 s3, s3, s2
257; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s3
258; GFX10-NEXT:    s_sub_i32 s4, 0, s3
259; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
260; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
261; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
262; GFX10-NEXT:    v_mul_lo_u32 v1, s4, v0
263; GFX10-NEXT:    s_mov_b32 s4, 0
264; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
265; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
266; GFX10-NEXT:    v_mov_b32_e32 v1, 0
267; GFX10-NEXT:  BB2_1: ; %bb3
268; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
269; GFX10-NEXT:    v_mul_hi_u32 v2, s4, v0
270; GFX10-NEXT:    v_mul_lo_u32 v3, v2, s3
271; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v2
272; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s4, v3
273; GFX10-NEXT:    s_add_i32 s4, s4, 1
274; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, s3, v3
275; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s3, v3
276; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
277; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
278; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v2
279; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s3, v3
280; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
281; GFX10-NEXT:    v_xor_b32_e32 v2, s2, v2
282; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s2, v2
283; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
284; GFX10-NEXT:    global_store_dword v1, v2, s[0:1]
285; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
286; GFX10-NEXT:    s_add_u32 s0, s0, 4
287; GFX10-NEXT:    s_addc_u32 s1, s1, 0
288; GFX10-NEXT:    s_cmpk_eq_i32 s4, 0x400
289; GFX10-NEXT:    s_cbranch_scc0 BB2_1
290; GFX10-NEXT:  ; %bb.2: ; %bb2
291; GFX10-NEXT:    s_endpgm
292bb:
293  br label %bb3
294
295bb2:                                              ; preds = %bb3
296  ret void
297
298bb3:                                              ; preds = %bb3, %bb
299  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
300  %tmp4 = sdiv i32 %tmp, %arg1
301  %tmp5 = zext i32 %tmp to i64
302  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
303  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
304  %tmp7 = add nuw nsw i32 %tmp, 1
305  %tmp8 = icmp eq i32 %tmp7, 1024
306  br i1 %tmp8, label %bb2, label %bb3
307}
308
309define amdgpu_kernel void @srem32_invariant_denom(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
310; GFX9-LABEL: srem32_invariant_denom:
311; GFX9:       ; %bb.0: ; %bb
312; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
313; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
314; GFX9-NEXT:    s_ashr_i32 s3, s2, 31
315; GFX9-NEXT:    s_add_i32 s2, s2, s3
316; GFX9-NEXT:    s_xor_b32 s2, s2, s3
317; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s2
318; GFX9-NEXT:    s_sub_i32 s3, 0, s2
319; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
320; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0
321; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
322; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
323; GFX9-NEXT:    v_mul_lo_u32 v1, s3, v0
324; GFX9-NEXT:    s_mov_b32 s3, 0
325; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v1
326; GFX9-NEXT:    v_add_u32_e32 v0, v0, v1
327; GFX9-NEXT:    v_mov_b32_e32 v1, 0
328; GFX9-NEXT:  BB3_1: ; %bb3
329; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
330; GFX9-NEXT:    v_mul_hi_u32 v2, s3, v0
331; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s2
332; GFX9-NEXT:    v_sub_u32_e32 v2, s3, v2
333; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v2
334; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
335; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
336; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v2
337; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
338; GFX9-NEXT:    s_add_i32 s3, s3, 1
339; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
340; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
341; GFX9-NEXT:    global_store_dword v1, v2, s[0:1]
342; GFX9-NEXT:    s_add_u32 s0, s0, 4
343; GFX9-NEXT:    s_addc_u32 s1, s1, 0
344; GFX9-NEXT:    s_cmpk_eq_i32 s3, 0x400
345; GFX9-NEXT:    s_cbranch_scc0 BB3_1
346; GFX9-NEXT:  ; %bb.2: ; %bb2
347; GFX9-NEXT:    s_endpgm
348;
349; GFX10-LABEL: srem32_invariant_denom:
350; GFX10:       ; %bb.0: ; %bb
351; GFX10-NEXT:    s_load_dword s2, s[0:1], 0x2c
352; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
353; GFX10-NEXT:    s_ashr_i32 s3, s2, 31
354; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
355; GFX10-NEXT:    s_add_i32 s2, s2, s3
356; GFX10-NEXT:    s_xor_b32 s2, s2, s3
357; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s2
358; GFX10-NEXT:    s_sub_i32 s3, 0, s2
359; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0
360; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
361; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
362; GFX10-NEXT:    v_mul_lo_u32 v1, s3, v0
363; GFX10-NEXT:    s_mov_b32 s3, 0
364; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1
365; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1
366; GFX10-NEXT:    v_mov_b32_e32 v1, 0
367; GFX10-NEXT:  BB3_1: ; %bb3
368; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
369; GFX10-NEXT:    v_mul_hi_u32 v2, s3, v0
370; GFX10-NEXT:    v_mul_lo_u32 v2, v2, s2
371; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s3, v2
372; GFX10-NEXT:    s_add_i32 s3, s3, 1
373; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s2, v2
374; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v2
375; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
376; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s2, v2
377; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v2
378; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
379; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
380; GFX10-NEXT:    global_store_dword v1, v2, s[0:1]
381; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
382; GFX10-NEXT:    s_add_u32 s0, s0, 4
383; GFX10-NEXT:    s_addc_u32 s1, s1, 0
384; GFX10-NEXT:    s_cmpk_eq_i32 s3, 0x400
385; GFX10-NEXT:    s_cbranch_scc0 BB3_1
386; GFX10-NEXT:  ; %bb.2: ; %bb2
387; GFX10-NEXT:    s_endpgm
388bb:
389  br label %bb3
390
391bb2:                                              ; preds = %bb3
392  ret void
393
394bb3:                                              ; preds = %bb3, %bb
395  %tmp = phi i32 [ 0, %bb ], [ %tmp7, %bb3 ]
396  %tmp4 = srem i32 %tmp, %arg1
397  %tmp5 = zext i32 %tmp to i64
398  %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp5
399  store i32 %tmp4, i32 addrspace(1)* %tmp6, align 4
400  %tmp7 = add nuw nsw i32 %tmp, 1
401  %tmp8 = icmp eq i32 %tmp7, 1024
402  br i1 %tmp8, label %bb2, label %bb3
403}
404
405define amdgpu_kernel void @udiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
406; GFX9-LABEL: udiv16_invariant_denom:
407; GFX9:       ; %bb.0: ; %bb
408; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
409; GFX9-NEXT:    s_mov_b32 s4, 0xffff
410; GFX9-NEXT:    v_mov_b32_e32 v1, 0
411; GFX9-NEXT:    s_movk_i32 s5, 0x400
412; GFX9-NEXT:    v_mov_b32_e32 v4, 0
413; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
414; GFX9-NEXT:    s_and_b32 s2, s4, s2
415; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s2
416; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
417; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v2
418; GFX9-NEXT:  BB4_1: ; %bb3
419; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
420; GFX9-NEXT:    v_and_b32_e32 v0, s4, v4
421; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v0
422; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[0:1]
423; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
424; GFX9-NEXT:    v_mov_b32_e32 v7, s3
425; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s2, v5
426; GFX9-NEXT:    v_mul_f32_e32 v0, v8, v3
427; GFX9-NEXT:    v_trunc_f32_e32 v0, v0
428; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
429; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v0
430; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
431; GFX9-NEXT:    v_mad_f32 v0, -v0, v2, v8
432; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s5, v4
433; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v0|, v2
434; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
435; GFX9-NEXT:    v_addc_co_u32_e64 v0, s[0:1], 0, v7, s[0:1]
436; GFX9-NEXT:    global_store_short v[5:6], v0, off
437; GFX9-NEXT:    s_cbranch_vccz BB4_1
438; GFX9-NEXT:  ; %bb.2: ; %bb2
439; GFX9-NEXT:    s_endpgm
440;
441; GFX10-LABEL: udiv16_invariant_denom:
442; GFX10:       ; %bb.0: ; %bb
443; GFX10-NEXT:    s_clause 0x1
444; GFX10-NEXT:    s_load_dword s4, s[0:1], 0x2c
445; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
446; GFX10-NEXT:    s_mov_b32 s1, 0xffff
447; GFX10-NEXT:    v_mov_b32_e32 v1, 0
448; GFX10-NEXT:    v_mov_b32_e32 v4, 0
449; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
450; GFX10-NEXT:    s_and_b32 s0, s1, s4
451; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s0
452; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v2
453; GFX10-NEXT:  BB4_1: ; %bb3
454; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
455; GFX10-NEXT:    v_and_b32_e32 v0, s1, v4
456; GFX10-NEXT:    v_add_nc_u16 v4, v4, 1
457; GFX10-NEXT:    v_cvt_f32_u32_e32 v7, v0
458; GFX10-NEXT:    v_lshlrev_b64 v[5:6], 1, v[0:1]
459; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
460; GFX10-NEXT:    v_mul_f32_e32 v0, v7, v3
461; GFX10-NEXT:    v_add_co_u32 v5, s0, s2, v5
462; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
463; GFX10-NEXT:    v_trunc_f32_e32 v0, v0
464; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
465; GFX10-NEXT:    v_mad_f32 v7, -v0, v2, v7
466; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0
467; GFX10-NEXT:    v_cmp_ge_f32_e64 s0, |v7|, v2
468; GFX10-NEXT:    v_add_co_ci_u32_e64 v0, s0, 0, v0, s0
469; GFX10-NEXT:    global_store_short v[5:6], v0, off
470; GFX10-NEXT:    s_cbranch_vccz BB4_1
471; GFX10-NEXT:  ; %bb.2: ; %bb2
472; GFX10-NEXT:    s_endpgm
473bb:
474  br label %bb3
475
476bb2:                                              ; preds = %bb3
477  ret void
478
479bb3:                                              ; preds = %bb3, %bb
480  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
481  %tmp4 = udiv i16 %tmp, %arg1
482  %tmp5 = zext i16 %tmp to i64
483  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
484  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
485  %tmp7 = add nuw nsw i16 %tmp, 1
486  %tmp8 = icmp eq i16 %tmp7, 1024
487  br i1 %tmp8, label %bb2, label %bb3
488}
489
490define amdgpu_kernel void @urem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
491; GFX9-LABEL: urem16_invariant_denom:
492; GFX9:       ; %bb.0: ; %bb
493; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
494; GFX9-NEXT:    s_mov_b32 s6, 0xffff
495; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
496; GFX9-NEXT:    v_mov_b32_e32 v1, 0
497; GFX9-NEXT:    s_movk_i32 s8, 0x400
498; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
499; GFX9-NEXT:    s_and_b32 s7, s6, s2
500; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s7
501; GFX9-NEXT:    v_mov_b32_e32 v4, 0
502; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v2
503; GFX9-NEXT:  BB5_1: ; %bb3
504; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
505; GFX9-NEXT:    v_and_b32_e32 v0, s6, v4
506; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v0
507; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[0:1]
508; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
509; GFX9-NEXT:    v_mov_b32_e32 v7, s5
510; GFX9-NEXT:    v_mul_f32_e32 v9, v8, v3
511; GFX9-NEXT:    v_trunc_f32_e32 v9, v9
512; GFX9-NEXT:    v_cvt_u32_f32_e32 v10, v9
513; GFX9-NEXT:    v_mad_f32 v8, -v9, v2, v8
514; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v8|, v2
515; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s8, v4
516; GFX9-NEXT:    v_addc_co_u32_e64 v8, s[2:3], 0, v10, s[2:3]
517; GFX9-NEXT:    v_mul_lo_u32 v8, v8, s7
518; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s4, v5
519; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
520; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
521; GFX9-NEXT:    v_sub_u32_e32 v0, v0, v8
522; GFX9-NEXT:    global_store_short v[5:6], v0, off
523; GFX9-NEXT:    s_cbranch_vccz BB5_1
524; GFX9-NEXT:  ; %bb.2: ; %bb2
525; GFX9-NEXT:    s_endpgm
526;
527; GFX10-LABEL: urem16_invariant_denom:
528; GFX10:       ; %bb.0: ; %bb
529; GFX10-NEXT:    s_clause 0x1
530; GFX10-NEXT:    s_load_dword s4, s[0:1], 0x2c
531; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
532; GFX10-NEXT:    s_mov_b32 s1, 0xffff
533; GFX10-NEXT:    v_mov_b32_e32 v1, 0
534; GFX10-NEXT:    v_mov_b32_e32 v4, 0
535; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
536; GFX10-NEXT:    s_and_b32 s4, s1, s4
537; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s4
538; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v2
539; GFX10-NEXT:  BB5_1: ; %bb3
540; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
541; GFX10-NEXT:    v_and_b32_e32 v0, s1, v4
542; GFX10-NEXT:    v_add_nc_u16 v4, v4, 1
543; GFX10-NEXT:    v_cvt_f32_u32_e32 v7, v0
544; GFX10-NEXT:    v_lshlrev_b64 v[5:6], 1, v[0:1]
545; GFX10-NEXT:    v_mul_f32_e32 v8, v7, v3
546; GFX10-NEXT:    v_add_co_u32 v5, s0, s2, v5
547; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
548; GFX10-NEXT:    v_trunc_f32_e32 v8, v8
549; GFX10-NEXT:    v_mad_f32 v7, -v8, v2, v7
550; GFX10-NEXT:    v_cvt_u32_f32_e32 v8, v8
551; GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v7|, v2
552; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
553; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
554; GFX10-NEXT:    v_mul_lo_u32 v7, v7, s4
555; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
556; GFX10-NEXT:    v_sub_nc_u32_e32 v0, v0, v7
557; GFX10-NEXT:    global_store_short v[5:6], v0, off
558; GFX10-NEXT:    s_cbranch_vccz BB5_1
559; GFX10-NEXT:  ; %bb.2: ; %bb2
560; GFX10-NEXT:    s_endpgm
561bb:
562  br label %bb3
563
564bb2:                                              ; preds = %bb3
565  ret void
566
567bb3:                                              ; preds = %bb3, %bb
568  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
569  %tmp4 = urem i16 %tmp, %arg1
570  %tmp5 = zext i16 %tmp to i64
571  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
572  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
573  %tmp7 = add nuw nsw i16 %tmp, 1
574  %tmp8 = icmp eq i16 %tmp7, 1024
575  br i1 %tmp8, label %bb2, label %bb3
576}
577
578define amdgpu_kernel void @sdiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
579; GFX9-LABEL: sdiv16_invariant_denom:
580; GFX9:       ; %bb.0: ; %bb
581; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
582; GFX9-NEXT:    v_mov_b32_e32 v1, 0
583; GFX9-NEXT:    s_movk_i32 s5, 0x400
584; GFX9-NEXT:    v_mov_b32_e32 v4, 0
585; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
586; GFX9-NEXT:    s_sext_i32_i16 s4, s2
587; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s4
588; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
589; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v2
590; GFX9-NEXT:  BB6_1: ; %bb3
591; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
592; GFX9-NEXT:    v_bfe_i32 v5, v4, 0, 16
593; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v4
594; GFX9-NEXT:    v_cvt_f32_i32_e32 v9, v5
595; GFX9-NEXT:    v_xor_b32_e32 v8, s4, v5
596; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[0:1]
597; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
598; GFX9-NEXT:    v_mov_b32_e32 v7, s3
599; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s2, v5
600; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1]
601; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v3
602; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
603; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 30, v8
604; GFX9-NEXT:    v_cvt_i32_f32_e32 v8, v7
605; GFX9-NEXT:    v_mad_f32 v7, -v7, v2, v9
606; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
607; GFX9-NEXT:    v_or_b32_e32 v0, 1, v0
608; GFX9-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v7|, |v2|
609; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s5, v4
610; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, v0, s[0:1]
611; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
612; GFX9-NEXT:    v_add_u32_e32 v0, v8, v0
613; GFX9-NEXT:    global_store_short v[5:6], v0, off
614; GFX9-NEXT:    s_cbranch_vccz BB6_1
615; GFX9-NEXT:  ; %bb.2: ; %bb2
616; GFX9-NEXT:    s_endpgm
617;
618; GFX10-LABEL: sdiv16_invariant_denom:
619; GFX10:       ; %bb.0: ; %bb
620; GFX10-NEXT:    s_clause 0x1
621; GFX10-NEXT:    s_load_dword s4, s[0:1], 0x2c
622; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
623; GFX10-NEXT:    v_mov_b32_e32 v1, 0
624; GFX10-NEXT:    v_mov_b32_e32 v4, 0
625; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
626; GFX10-NEXT:    s_sext_i32_i16 s4, s4
627; GFX10-NEXT:    v_cvt_f32_i32_e32 v2, s4
628; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v2
629; GFX10-NEXT:  BB6_1: ; %bb3
630; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
631; GFX10-NEXT:    v_bfe_i32 v5, v4, 0, 16
632; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v4
633; GFX10-NEXT:    v_add_nc_u16 v4, v4, 1
634; GFX10-NEXT:    v_cvt_f32_i32_e32 v7, v5
635; GFX10-NEXT:    v_xor_b32_e32 v8, s4, v5
636; GFX10-NEXT:    v_lshlrev_b64 v[5:6], 1, v[0:1]
637; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
638; GFX10-NEXT:    v_mul_f32_e32 v0, v7, v3
639; GFX10-NEXT:    v_ashrrev_i32_e32 v8, 30, v8
640; GFX10-NEXT:    v_add_co_u32 v5, s0, s2, v5
641; GFX10-NEXT:    v_trunc_f32_e32 v0, v0
642; GFX10-NEXT:    v_or_b32_e32 v8, 1, v8
643; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
644; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
645; GFX10-NEXT:    v_mad_f32 v7, -v0, v2, v7
646; GFX10-NEXT:    v_cvt_i32_f32_e32 v0, v0
647; GFX10-NEXT:    v_cmp_ge_f32_e64 s1, |v7|, |v2|
648; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, v8, s1
649; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v7
650; GFX10-NEXT:    global_store_short v[5:6], v0, off
651; GFX10-NEXT:    s_cbranch_vccz BB6_1
652; GFX10-NEXT:  ; %bb.2: ; %bb2
653; GFX10-NEXT:    s_endpgm
654bb:
655  br label %bb3
656
657bb2:                                              ; preds = %bb3
658  ret void
659
660bb3:                                              ; preds = %bb3, %bb
661  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
662  %tmp4 = sdiv i16 %tmp, %arg1
663  %tmp5 = zext i16 %tmp to i64
664  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
665  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
666  %tmp7 = add nuw nsw i16 %tmp, 1
667  %tmp8 = icmp eq i16 %tmp7, 1024
668  br i1 %tmp8, label %bb2, label %bb3
669}
670
671define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
672; GFX9-LABEL: srem16_invariant_denom:
673; GFX9:       ; %bb.0: ; %bb
674; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
675; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
676; GFX9-NEXT:    v_mov_b32_e32 v1, 0
677; GFX9-NEXT:    s_movk_i32 s7, 0x400
678; GFX9-NEXT:    v_mov_b32_e32 v4, 0
679; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
680; GFX9-NEXT:    s_sext_i32_i16 s6, s2
681; GFX9-NEXT:    v_cvt_f32_i32_e32 v2, s6
682; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v2
683; GFX9-NEXT:  BB7_1: ; %bb3
684; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
685; GFX9-NEXT:    v_bfe_i32 v7, v4, 0, 16
686; GFX9-NEXT:    v_cvt_f32_i32_e32 v10, v7
687; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v4
688; GFX9-NEXT:    v_xor_b32_e32 v9, s6, v7
689; GFX9-NEXT:    v_lshlrev_b64 v[5:6], 1, v[0:1]
690; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 30, v9
691; GFX9-NEXT:    v_mul_f32_e32 v9, v10, v3
692; GFX9-NEXT:    v_trunc_f32_e32 v9, v9
693; GFX9-NEXT:    v_cvt_i32_f32_e32 v11, v9
694; GFX9-NEXT:    v_mad_f32 v9, -v9, v2, v10
695; GFX9-NEXT:    v_or_b32_e32 v0, 1, v0
696; GFX9-NEXT:    v_cmp_ge_f32_e64 s[2:3], |v9|, |v2|
697; GFX9-NEXT:    v_cndmask_b32_e64 v0, 0, v0, s[2:3]
698; GFX9-NEXT:    v_add_u32_e32 v0, v11, v0
699; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s6
700; GFX9-NEXT:    v_add_u16_e32 v4, 1, v4
701; GFX9-NEXT:    v_mov_b32_e32 v8, s5
702; GFX9-NEXT:    v_cmp_eq_u16_e32 vcc, s7, v4
703; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], s4, v5
704; GFX9-NEXT:    s_and_b64 vcc, exec, vcc
705; GFX9-NEXT:    v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1]
706; GFX9-NEXT:    v_sub_u32_e32 v0, v7, v0
707; GFX9-NEXT:    global_store_short v[5:6], v0, off
708; GFX9-NEXT:    s_cbranch_vccz BB7_1
709; GFX9-NEXT:  ; %bb.2: ; %bb2
710; GFX9-NEXT:    s_endpgm
711;
712; GFX10-LABEL: srem16_invariant_denom:
713; GFX10:       ; %bb.0: ; %bb
714; GFX10-NEXT:    s_clause 0x1
715; GFX10-NEXT:    s_load_dword s4, s[0:1], 0x2c
716; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
717; GFX10-NEXT:    v_mov_b32_e32 v1, 0
718; GFX10-NEXT:    v_mov_b32_e32 v4, 0
719; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
720; GFX10-NEXT:    s_sext_i32_i16 s1, s4
721; GFX10-NEXT:    v_cvt_f32_i32_e32 v2, s1
722; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v2
723; GFX10-NEXT:  BB7_1: ; %bb3
724; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
725; GFX10-NEXT:    v_bfe_i32 v7, v4, 0, 16
726; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v4
727; GFX10-NEXT:    v_add_nc_u16 v4, v4, 1
728; GFX10-NEXT:    v_cvt_f32_i32_e32 v5, v7
729; GFX10-NEXT:    v_xor_b32_e32 v6, s1, v7
730; GFX10-NEXT:    v_mul_f32_e32 v8, v5, v3
731; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 30, v6
732; GFX10-NEXT:    v_trunc_f32_e32 v8, v8
733; GFX10-NEXT:    v_or_b32_e32 v6, 1, v6
734; GFX10-NEXT:    v_mad_f32 v5, -v8, v2, v5
735; GFX10-NEXT:    v_cvt_i32_f32_e32 v8, v8
736; GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v5|, |v2|
737; GFX10-NEXT:    v_cndmask_b32_e32 v9, 0, v6, vcc_lo
738; GFX10-NEXT:    v_lshlrev_b64 v[5:6], 1, v[0:1]
739; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
740; GFX10-NEXT:    v_add_nc_u32_e32 v0, v8, v9
741; GFX10-NEXT:    v_add_co_u32 v5, s0, s2, v5
742; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
743; GFX10-NEXT:    v_mul_lo_u32 v0, v0, s1
744; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
745; GFX10-NEXT:    v_sub_nc_u32_e32 v0, v7, v0
746; GFX10-NEXT:    global_store_short v[5:6], v0, off
747; GFX10-NEXT:    s_cbranch_vccz BB7_1
748; GFX10-NEXT:  ; %bb.2: ; %bb2
749; GFX10-NEXT:    s_endpgm
750bb:
751  br label %bb3
752
753bb2:                                              ; preds = %bb3
754  ret void
755
756bb3:                                              ; preds = %bb3, %bb
757  %tmp = phi i16 [ 0, %bb ], [ %tmp7, %bb3 ]
758  %tmp4 = srem i16 %tmp, %arg1
759  %tmp5 = zext i16 %tmp to i64
760  %tmp6 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %tmp5
761  store i16 %tmp4, i16 addrspace(1)* %tmp6, align 2
762  %tmp7 = add nuw nsw i16 %tmp, 1
763  %tmp8 = icmp eq i16 %tmp7, 1024
764  br i1 %tmp8, label %bb2, label %bb3
765}
766