1; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3
4; SI-LABEL: {{^}}i1_copy_from_loop:
5;
6; SI: [[LOOP:BB0_[0-9]+]]:  ; %Flow1
7; SI:   s_or_b64 exec, exec, [[EXIT_MASK:s\[[0-9]+:[0-9]+\]]]
8; SI:   ; %Flow
9; SI:  s_and_b64 [[ACCUM_MASK:s\[[0-9]+:[0-9]+\]]], [[CC_MASK:s\[[0-9]+:[0-9]+\]]], exec
10; SI:  s_or_b64  [[I1_VALUE:s\[[0-9]+:[0-9]+\]]], s[6:7], [[ACCUM_MASK]]
11; SI:  s_cbranch_execz [[FOR_END_LABEL:BB0_[0-9]+]]
12
13; SI: ; %for.body
14; SI:      v_cmp_lt_u32_e64  [[CC_MASK]], s{{[0-9]+}}, 4
15
16; SI: [[FOR_END_LABEL]]
17; SI:      s_or_b64 exec, exec, [[EXIT_MASK]]
18; SI:      s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[I1_VALUE]]
19; SI:      s_cbranch_execz [[EXIT:BB0_[0-9]+]]
20; SI: [[EXIT]]
21; SI-NEXT: s_endpgm
22
23define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) {
24entry:
25  br label %for.body
26
27for.body:
28  %i = phi i32 [0, %entry], [%i.inc, %end.loop]
29  %cc = icmp ult i32 %i, 4
30  br i1 %cc, label %mid.loop, label %for.end
31
32mid.loop:
33  %v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %tid, i32 %i, i1 false, i1 false)
34  %cc2 = fcmp oge float %v, 0.0
35  br i1 %cc2, label %end.loop, label %for.end
36
37end.loop:
38  %i.inc = add i32 %i, 1
39  br label %for.body
40
41for.end:
42  br i1 %cc, label %if, label %end
43
44if:
45  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float undef, float undef, float undef, i1 true, i1 true)
46  br label %end
47
48end:
49  ret void
50}
51
52declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
53declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
54
55attributes #0 = { nounwind readonly }
56attributes #1 = { nounwind inaccessiblememonly }
57