1; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SIVI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-atomic-optimizations=false -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SIVI %s 3; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-atomic-optimizations=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s 4 5; GCN-LABEL: {{^}}atomic_add_i32_offset: 6; SIVI: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 7; GFX9: global_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 8define amdgpu_kernel void @atomic_add_i32_offset(i32 addrspace(1)* %out, i32 %in) { 9entry: 10 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 11 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 12 ret void 13} 14 15; GCN-LABEL: {{^}}atomic_add_i32_max_neg_offset: 16; GFX9: global_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off offset:-4096{{$}} 17define amdgpu_kernel void @atomic_add_i32_max_neg_offset(i32 addrspace(1)* %out, i32 %in) { 18entry: 19 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 -1024 20 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 21 ret void 22} 23 24; GCN-LABEL: {{^}}atomic_add_i32_soffset: 25; SIVI: s_mov_b32 [[SREG:s[0-9]+]], 0x8ca0 26; SIVI: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], [[SREG]]{{$}} 27 28; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, 0x8000, 29; GFX9-NEXT: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 30; GFX9: global_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off offset:3232{{$}} 31define amdgpu_kernel void @atomic_add_i32_soffset(i32 addrspace(1)* %out, i32 %in) { 32entry: 33 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 9000 34 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 35 ret void 36} 37 38; GCN-LABEL: {{^}}atomic_add_i32_huge_offset: 39; SI-DAG: v_mov_b32_e32 v[[PTRLO:[0-9]+]], 0xdeac 40; SI-DAG: v_mov_b32_e32 v[[PTRHI:[0-9]+]], 0xabcd 41; SI: buffer_atomic_add v{{[0-9]+}}, v{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 42 43; VI: flat_atomic_add 44 45; GFX9: v_mov_b32_e32 [[HIGH_K:v[0-9]+]], 0xabcd 46; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, 0xd000, 47; GFX9-NEXT: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, [[HIGH_K]], v{{[0-9]+}}, vcc 48; GFX9: global_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off offset:3756{{$}} 49define amdgpu_kernel void @atomic_add_i32_huge_offset(i32 addrspace(1)* %out, i32 %in) { 50entry: 51 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 47224239175595 52 53 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 54 ret void 55} 56 57; GCN-LABEL: {{^}}atomic_add_i32_ret_offset: 58; SIVI: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 59; SIVI: buffer_store_dword [[RET]] 60 61; GFX9: global_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 62define amdgpu_kernel void @atomic_add_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 63entry: 64 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 65 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 66 store i32 %val, i32 addrspace(1)* %out2 67 ret void 68} 69 70; GCN-LABEL: {{^}}atomic_add_i32_addr64_offset: 71; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 72; VI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 73; GFX9: global_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 74define amdgpu_kernel void @atomic_add_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 75entry: 76 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 77 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 78 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 79 ret void 80} 81 82; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64_offset: 83; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 84; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 85; SIVI: buffer_store_dword [[RET]] 86 87; GFX9: global_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 88; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] 89define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 90entry: 91 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 92 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 93 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst 94 store i32 %val, i32 addrspace(1)* %out2 95 ret void 96} 97 98; GCN-LABEL: {{^}}atomic_add_i32: 99; SIVI: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 100; GFX9: global_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off{{$}} 101define amdgpu_kernel void @atomic_add_i32(i32 addrspace(1)* %out, i32 %in) { 102entry: 103 %val = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst 104 ret void 105} 106 107; GCN-LABEL: {{^}}atomic_add_i32_ret: 108; SIVI: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 109; SIVI: buffer_store_dword [[RET]] 110 111; GFX9: global_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 112; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] 113define amdgpu_kernel void @atomic_add_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 114entry: 115 %val = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst 116 store i32 %val, i32 addrspace(1)* %out2 117 ret void 118} 119 120; GCN-LABEL: {{^}}atomic_add_i32_addr64: 121; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 122; VI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 123; GFX9: global_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 124define amdgpu_kernel void @atomic_add_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 125entry: 126 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 127 %val = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst 128 ret void 129} 130 131; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64: 132; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 133; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 134; SIVI: buffer_store_dword [[RET]] 135 136; GFX9: global_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 137define amdgpu_kernel void @atomic_add_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 138entry: 139 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 140 %val = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst 141 store i32 %val, i32 addrspace(1)* %out2 142 ret void 143} 144 145; GCN-LABEL: {{^}}atomic_and_i32_offset: 146; SIVI: buffer_atomic_and v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 147 148; GFX9: global_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 149define amdgpu_kernel void @atomic_and_i32_offset(i32 addrspace(1)* %out, i32 %in) { 150entry: 151 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 152 %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst 153 ret void 154} 155 156; GCN-LABEL: {{^}}atomic_and_i32_ret_offset: 157; SIVI: buffer_atomic_and [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 158; SIVI: buffer_store_dword [[RET]] 159 160; GFX9: global_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 161define amdgpu_kernel void @atomic_and_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 162entry: 163 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 164 %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst 165 store i32 %val, i32 addrspace(1)* %out2 166 ret void 167} 168 169; GCN-LABEL: {{^}}atomic_and_i32_addr64_offset: 170; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 171; VI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 172 173; GFX9: global_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 174define amdgpu_kernel void @atomic_and_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 175entry: 176 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 177 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 178 %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst 179 ret void 180} 181 182; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64_offset: 183; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 184; VI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 185; SIVI: buffer_store_dword [[RET]] 186 187; GFX9: global_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 188define amdgpu_kernel void @atomic_and_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 189entry: 190 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 191 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 192 %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst 193 store i32 %val, i32 addrspace(1)* %out2 194 ret void 195} 196 197; GCN-LABEL: {{^}}atomic_and_i32: 198; SIVI: buffer_atomic_and v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 199 200; GFX9: global_atomic_and v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off{{$}} 201define amdgpu_kernel void @atomic_and_i32(i32 addrspace(1)* %out, i32 %in) { 202entry: 203 %val = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst 204 ret void 205} 206 207; GCN-LABEL: {{^}}atomic_and_i32_ret: 208; SIVI: buffer_atomic_and [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 209; SIVI: buffer_store_dword [[RET]] 210 211; GFX9: global_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 212define amdgpu_kernel void @atomic_and_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 213entry: 214 %val = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst 215 store i32 %val, i32 addrspace(1)* %out2 216 ret void 217} 218 219; GCN-LABEL: {{^}}atomic_and_i32_addr64: 220; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 221; VI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 222 223; GFX9: global_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 224define amdgpu_kernel void @atomic_and_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 225entry: 226 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 227 %val = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst 228 ret void 229} 230 231; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64: 232; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 233; VI: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 234; SIVI: buffer_store_dword [[RET]] 235 236; GFX9: global_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 237define amdgpu_kernel void @atomic_and_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 238entry: 239 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 240 %val = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst 241 store i32 %val, i32 addrspace(1)* %out2 242 ret void 243} 244 245; GCN-LABEL: {{^}}atomic_sub_i32_offset: 246; SIVI: buffer_atomic_sub v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 247 248; GFX9: global_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 249define amdgpu_kernel void @atomic_sub_i32_offset(i32 addrspace(1)* %out, i32 %in) { 250entry: 251 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 252 %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst 253 ret void 254} 255 256; GCN-LABEL: {{^}}atomic_sub_i32_ret_offset: 257; SIVI: buffer_atomic_sub [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 258; SIVI: buffer_store_dword [[RET]] 259 260; GFX9: global_atomic_sub v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 261define amdgpu_kernel void @atomic_sub_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 262entry: 263 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 264 %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst 265 store i32 %val, i32 addrspace(1)* %out2 266 ret void 267} 268 269; GCN-LABEL: {{^}}atomic_sub_i32_addr64_offset: 270; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 271; VI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 272 273; GFX9: global_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 274define amdgpu_kernel void @atomic_sub_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 275entry: 276 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 277 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 278 %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst 279 ret void 280} 281 282; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset: 283; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 284; VI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 285; SIVI: buffer_store_dword [[RET]] 286 287; GFX9: global_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 288define amdgpu_kernel void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 289entry: 290 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 291 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 292 %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst 293 store i32 %val, i32 addrspace(1)* %out2 294 ret void 295} 296 297; GCN-LABEL: {{^}}atomic_sub_i32: 298; SIVI: buffer_atomic_sub v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 299 300; GFX9: global_atomic_sub v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off{{$}} 301define amdgpu_kernel void @atomic_sub_i32(i32 addrspace(1)* %out, i32 %in) { 302entry: 303 %val = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst 304 ret void 305} 306 307; GCN-LABEL: {{^}}atomic_sub_i32_ret: 308; SIVI: buffer_atomic_sub [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 309; SIVI: buffer_store_dword [[RET]] 310 311; GFX9: global_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 312define amdgpu_kernel void @atomic_sub_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 313entry: 314 %val = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst 315 store i32 %val, i32 addrspace(1)* %out2 316 ret void 317} 318 319; GCN-LABEL: {{^}}atomic_sub_i32_addr64: 320; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 321; VI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 322 323; GFX9: global_atomic_sub v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off{{$}} 324define amdgpu_kernel void @atomic_sub_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 325entry: 326 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 327 %val = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst 328 ret void 329} 330 331; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64: 332; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 333; VI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 334; SIVI: buffer_store_dword [[RET]] 335 336; GFX9: global_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 337define amdgpu_kernel void @atomic_sub_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 338entry: 339 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 340 %val = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst 341 store i32 %val, i32 addrspace(1)* %out2 342 ret void 343} 344 345; GCN-LABEL: {{^}}atomic_max_i32_offset: 346; SIVI: buffer_atomic_smax v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 347 348; GFX9: global_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 349define amdgpu_kernel void @atomic_max_i32_offset(i32 addrspace(1)* %out, i32 %in) { 350entry: 351 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 352 %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst 353 ret void 354} 355 356; GCN-LABEL: {{^}}atomic_max_i32_ret_offset: 357; SIVI: buffer_atomic_smax [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 358; SIVI: buffer_store_dword [[RET]] 359 360; GFX9: global_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 361define amdgpu_kernel void @atomic_max_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 362entry: 363 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 364 %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst 365 store i32 %val, i32 addrspace(1)* %out2 366 ret void 367} 368 369; GCN-LABEL: {{^}}atomic_max_i32_addr64_offset: 370; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 371; VI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 372 373; GFX9: global_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 374define amdgpu_kernel void @atomic_max_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 375entry: 376 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 377 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 378 %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst 379 ret void 380} 381 382; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64_offset: 383; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 384; VI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 385; SIVI: buffer_store_dword [[RET]] 386 387; GFX9: global_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 388define amdgpu_kernel void @atomic_max_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 389entry: 390 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 391 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 392 %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst 393 store i32 %val, i32 addrspace(1)* %out2 394 ret void 395} 396 397; GCN-LABEL: {{^}}atomic_max_i32: 398; SIVI: buffer_atomic_smax v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 399 400; GFX9: global_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 401define amdgpu_kernel void @atomic_max_i32(i32 addrspace(1)* %out, i32 %in) { 402entry: 403 %val = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst 404 ret void 405} 406 407; GCN-LABEL: {{^}}atomic_max_i32_ret: 408; SIVI: buffer_atomic_smax [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 409; SIVI: buffer_store_dword [[RET]] 410 411; GFX9: global_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 412define amdgpu_kernel void @atomic_max_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 413entry: 414 %val = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst 415 store i32 %val, i32 addrspace(1)* %out2 416 ret void 417} 418 419; GCN-LABEL: {{^}}atomic_max_i32_addr64: 420; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 421; VI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 422 423; GFX9: global_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 424define amdgpu_kernel void @atomic_max_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 425entry: 426 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 427 %val = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst 428 ret void 429} 430 431; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64: 432; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 433; VI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 434; SIVI: buffer_store_dword [[RET]] 435 436; GFX9: global_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 437define amdgpu_kernel void @atomic_max_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 438entry: 439 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 440 %val = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst 441 store i32 %val, i32 addrspace(1)* %out2 442 ret void 443} 444 445; GCN-LABEL: {{^}}atomic_umax_i32_offset: 446; SIVI: buffer_atomic_umax v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 447 448; GFX9: global_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 449define amdgpu_kernel void @atomic_umax_i32_offset(i32 addrspace(1)* %out, i32 %in) { 450entry: 451 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 452 %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst 453 ret void 454} 455 456; GCN-LABEL: {{^}}atomic_umax_i32_ret_offset: 457; SIVI: buffer_atomic_umax [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 458; SIVI: buffer_store_dword [[RET]] 459 460; GFX9: global_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 461define amdgpu_kernel void @atomic_umax_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 462entry: 463 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 464 %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst 465 store i32 %val, i32 addrspace(1)* %out2 466 ret void 467} 468 469; GCN-LABEL: {{^}}atomic_umax_i32_addr64_offset: 470; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 471; VI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 472; GFX9: global_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 473define amdgpu_kernel void @atomic_umax_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 474entry: 475 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 476 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 477 %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst 478 ret void 479} 480 481; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset: 482; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 483; VI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 484; SIVI: buffer_store_dword [[RET]] 485 486; GFX9: global_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 487define amdgpu_kernel void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 488entry: 489 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 490 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 491 %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst 492 store i32 %val, i32 addrspace(1)* %out2 493 ret void 494} 495 496; GCN-LABEL: {{^}}atomic_umax_i32: 497; SIVI: buffer_atomic_umax v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 498 499; GFX9: global_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 500define amdgpu_kernel void @atomic_umax_i32(i32 addrspace(1)* %out, i32 %in) { 501entry: 502 %val = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst 503 ret void 504} 505 506; GCN-LABEL: {{^}}atomic_umax_i32_ret: 507; SIVI: buffer_atomic_umax [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 508; SIVI: buffer_store_dword [[RET]] 509 510; GFX9: global_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 511define amdgpu_kernel void @atomic_umax_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 512entry: 513 %val = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst 514 store i32 %val, i32 addrspace(1)* %out2 515 ret void 516} 517 518; GCN-LABEL: {{^}}atomic_umax_i32_addr64: 519; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 520; VI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 521; GFX9: global_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 522define amdgpu_kernel void @atomic_umax_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 523entry: 524 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 525 %val = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst 526 ret void 527} 528 529; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64: 530; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 531; VI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 532; SIVI: buffer_store_dword [[RET]] 533 534; GFX9: global_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 535define amdgpu_kernel void @atomic_umax_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 536entry: 537 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 538 %val = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst 539 store i32 %val, i32 addrspace(1)* %out2 540 ret void 541} 542 543; GCN-LABEL: {{^}}atomic_min_i32_offset: 544; SIVI: buffer_atomic_smin v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 545 546; GFX9: global_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 547define amdgpu_kernel void @atomic_min_i32_offset(i32 addrspace(1)* %out, i32 %in) { 548entry: 549 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 550 %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst 551 ret void 552} 553 554; GCN-LABEL: {{^}}atomic_min_i32_ret_offset: 555; SIVI: buffer_atomic_smin [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 556; SIVI: buffer_store_dword [[RET]] 557 558; GFX9: global_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 559define amdgpu_kernel void @atomic_min_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 560entry: 561 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 562 %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst 563 store i32 %val, i32 addrspace(1)* %out2 564 ret void 565} 566 567; GCN-LABEL: {{^}}atomic_min_i32_addr64_offset: 568; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 569; VI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 570; GFX9: global_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 571define amdgpu_kernel void @atomic_min_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 572entry: 573 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 574 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 575 %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst 576 ret void 577} 578 579; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64_offset: 580; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 581; VI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 582; SIVI: buffer_store_dword [[RET]] 583 584; GFX9: global_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 585define amdgpu_kernel void @atomic_min_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 586entry: 587 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 588 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 589 %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst 590 store i32 %val, i32 addrspace(1)* %out2 591 ret void 592} 593 594; GCN-LABEL: {{^}}atomic_min_i32: 595; SIVI: buffer_atomic_smin v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 596 597; GFX9: global_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 598define amdgpu_kernel void @atomic_min_i32(i32 addrspace(1)* %out, i32 %in) { 599entry: 600 %val = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst 601 ret void 602} 603 604; GCN-LABEL: {{^}}atomic_min_i32_ret: 605; SIVI: buffer_atomic_smin [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 606; SIVI: buffer_store_dword [[RET]] 607 608; GFX9: global_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 609define amdgpu_kernel void @atomic_min_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 610entry: 611 %val = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst 612 store i32 %val, i32 addrspace(1)* %out2 613 ret void 614} 615 616; GCN-LABEL: {{^}}atomic_min_i32_addr64: 617; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 618; VI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 619; GFX9: global_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 620define amdgpu_kernel void @atomic_min_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 621entry: 622 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 623 %val = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst 624 ret void 625} 626 627; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64: 628; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 629; VI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 630; SIVI: buffer_store_dword [[RET]] 631 632; GFX9: global_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 633define amdgpu_kernel void @atomic_min_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 634entry: 635 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 636 %val = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst 637 store i32 %val, i32 addrspace(1)* %out2 638 ret void 639} 640 641; GCN-LABEL: {{^}}atomic_umin_i32_offset: 642; SIVI: buffer_atomic_umin v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 643 644; GFX9: global_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 645define amdgpu_kernel void @atomic_umin_i32_offset(i32 addrspace(1)* %out, i32 %in) { 646entry: 647 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 648 %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst 649 ret void 650} 651 652; GCN-LABEL: {{^}}atomic_umin_i32_ret_offset: 653; SIVI: buffer_atomic_umin [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 654; SIVI: buffer_store_dword [[RET]] 655 656; GFX9: global_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 657define amdgpu_kernel void @atomic_umin_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 658entry: 659 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 660 %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst 661 store i32 %val, i32 addrspace(1)* %out2 662 ret void 663} 664 665; GCN-LABEL: {{^}}atomic_umin_i32_addr64_offset: 666; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 667; VI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 668; GFX9: global_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 669define amdgpu_kernel void @atomic_umin_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 670entry: 671 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 672 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 673 %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst 674 ret void 675} 676 677; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset: 678; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 679; VI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 680; SIVI: buffer_store_dword [[RET]] 681 682; GFX9: global_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 683define amdgpu_kernel void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 684entry: 685 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 686 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 687 %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst 688 store i32 %val, i32 addrspace(1)* %out2 689 ret void 690} 691 692; GCN-LABEL: {{^}}atomic_umin_i32: 693; SIVI: buffer_atomic_umin v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 694; GFX9: global_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 695define amdgpu_kernel void @atomic_umin_i32(i32 addrspace(1)* %out, i32 %in) { 696entry: 697 %val = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst 698 ret void 699} 700 701; GCN-LABEL: {{^}}atomic_umin_i32_ret: 702; SIVI: buffer_atomic_umin [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 703; SIVI: buffer_store_dword [[RET]] 704 705; GFX9: global_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 706define amdgpu_kernel void @atomic_umin_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 707entry: 708 %val = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst 709 store i32 %val, i32 addrspace(1)* %out2 710 ret void 711} 712 713; GCN-LABEL: {{^}}atomic_umin_i32_addr64: 714; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 715; VI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 716; GFX9: global_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 717define amdgpu_kernel void @atomic_umin_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 718entry: 719 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 720 %val = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst 721 ret void 722} 723 724; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64: 725; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 726; VI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 727; SIVI: buffer_store_dword [[RET]] 728 729; GFX9: global_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 730define amdgpu_kernel void @atomic_umin_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 731entry: 732 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 733 %val = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst 734 store i32 %val, i32 addrspace(1)* %out2 735 ret void 736} 737 738; GCN-LABEL: {{^}}atomic_or_i32_offset: 739; SIVI: buffer_atomic_or v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 740 741; GFX9: global_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 742define amdgpu_kernel void @atomic_or_i32_offset(i32 addrspace(1)* %out, i32 %in) { 743entry: 744 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 745 %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst 746 ret void 747} 748 749; GCN-LABEL: {{^}}atomic_or_i32_ret_offset: 750; SIVI: buffer_atomic_or [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 751; SIVI: buffer_store_dword [[RET]] 752 753; GFX9: global_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 754define amdgpu_kernel void @atomic_or_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 755entry: 756 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 757 %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst 758 store i32 %val, i32 addrspace(1)* %out2 759 ret void 760} 761 762; GCN-LABEL: {{^}}atomic_or_i32_addr64_offset: 763; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 764; VI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 765; GFX9: global_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 766define amdgpu_kernel void @atomic_or_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 767entry: 768 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 769 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 770 %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst 771 ret void 772} 773 774; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64_offset: 775; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 776; VI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 777; SIVI: buffer_store_dword [[RET]] 778 779; GFX9: global_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 780define amdgpu_kernel void @atomic_or_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 781entry: 782 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 783 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 784 %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst 785 store i32 %val, i32 addrspace(1)* %out2 786 ret void 787} 788 789; GCN-LABEL: {{^}}atomic_or_i32: 790; SIVI: buffer_atomic_or v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 791 792; GFX9: global_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 793define amdgpu_kernel void @atomic_or_i32(i32 addrspace(1)* %out, i32 %in) { 794entry: 795 %val = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst 796 ret void 797} 798 799; GCN-LABEL: {{^}}atomic_or_i32_ret: 800; SIVI: buffer_atomic_or [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 801; SIVI: buffer_store_dword [[RET]] 802 803; GFX9: global_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 804define amdgpu_kernel void @atomic_or_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 805entry: 806 %val = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst 807 store i32 %val, i32 addrspace(1)* %out2 808 ret void 809} 810 811; GCN-LABEL: {{^}}atomic_or_i32_addr64: 812; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 813; VI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 814; GFX9: global_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 815define amdgpu_kernel void @atomic_or_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 816entry: 817 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 818 %val = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst 819 ret void 820} 821 822; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64: 823; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 824; VI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 825; SIVI: buffer_store_dword [[RET]] 826 827; GFX9: global_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 828define amdgpu_kernel void @atomic_or_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 829entry: 830 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 831 %val = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst 832 store i32 %val, i32 addrspace(1)* %out2 833 ret void 834} 835 836; GCN-LABEL: {{^}}atomic_xchg_i32_offset: 837; SIVI: buffer_atomic_swap v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 838 839; GFX9: global_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 840define amdgpu_kernel void @atomic_xchg_i32_offset(i32 addrspace(1)* %out, i32 %in) { 841entry: 842 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 843 %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst 844 ret void 845} 846 847; GCN-LABEL: {{^}}atomic_xchg_f32_offset: 848; SIVI: buffer_atomic_swap v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 849 850; GFX9: global_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 851define amdgpu_kernel void @atomic_xchg_f32_offset(float addrspace(1)* %out, float %in) { 852entry: 853 %gep = getelementptr float, float addrspace(1)* %out, i64 4 854 %val = atomicrmw volatile xchg float addrspace(1)* %gep, float %in seq_cst 855 ret void 856} 857 858; GCN-LABEL: {{^}}atomic_xchg_i32_ret_offset: 859; SIVI: buffer_atomic_swap [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 860; SIVI: buffer_store_dword [[RET]] 861 862; GFX9: global_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 863define amdgpu_kernel void @atomic_xchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 864entry: 865 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 866 %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst 867 store i32 %val, i32 addrspace(1)* %out2 868 ret void 869} 870 871; GCN-LABEL: {{^}}atomic_xchg_i32_addr64_offset: 872; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 873; VI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 874; GFX9: global_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 875define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 876entry: 877 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 878 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 879 %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst 880 ret void 881} 882 883; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset: 884; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 885; VI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 886; SIVI: buffer_store_dword [[RET]] 887 888; GFX9: global_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 889define amdgpu_kernel void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 890entry: 891 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 892 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 893 %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst 894 store i32 %val, i32 addrspace(1)* %out2 895 ret void 896} 897 898; GCN-LABEL: {{^}}atomic_xchg_i32: 899; SIVI: buffer_atomic_swap v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 900; GFX9: global_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 901define amdgpu_kernel void @atomic_xchg_i32(i32 addrspace(1)* %out, i32 %in) { 902entry: 903 %val = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst 904 ret void 905} 906 907; GCN-LABEL: {{^}}atomic_xchg_i32_ret: 908; SIVI: buffer_atomic_swap [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 909; SIVI: buffer_store_dword [[RET]] 910 911; GFX9: global_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 912define amdgpu_kernel void @atomic_xchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 913entry: 914 %val = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst 915 store i32 %val, i32 addrspace(1)* %out2 916 ret void 917} 918 919; GCN-LABEL: {{^}}atomic_xchg_i32_addr64: 920; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 921; VI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 922; GFX9: global_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 923define amdgpu_kernel void @atomic_xchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 924entry: 925 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 926 %val = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst 927 ret void 928} 929 930; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64: 931; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 932; VI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 933; SIVI: buffer_store_dword [[RET]] 934 935; GFX9: global_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 936define amdgpu_kernel void @atomic_xchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 937entry: 938 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 939 %val = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst 940 store i32 %val, i32 addrspace(1)* %out2 941 ret void 942} 943 944; GCN-LABEL: {{^}}atomic_cmpxchg_i32_offset: 945; SIVI: buffer_atomic_cmpswap v[{{[0-9]+}}:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 946 947; GFX9: global_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:16{{$}} 948define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32 addrspace(1)* %out, i32 %in, i32 %old) { 949entry: 950 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 951 %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst 952 ret void 953} 954 955; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_offset: 956; SIVI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 957; SIVI: buffer_store_dword v[[RET]] 958 959; GFX9: global_atomic_cmpswap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}, off offset:16 glc{{$}} 960define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i32 %old) { 961entry: 962 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 963 %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst 964 %extract0 = extractvalue { i32, i1 } %val, 0 965 store i32 %extract0, i32 addrspace(1)* %out2 966 ret void 967} 968 969; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset: 970; SI: buffer_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 971 972; VI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} 973; GFX9: global_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], off offset:16{{$}} 974define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index, i32 %old) { 975entry: 976 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 977 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 978 %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst 979 ret void 980} 981 982; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64_offset: 983; SI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 984; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} 985; SIVI: buffer_store_dword v[[RET]] 986 987; GFX9: global_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:16 glc{{$}} 988define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index, i32 %old) { 989entry: 990 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 991 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 992 %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst 993 %extract0 = extractvalue { i32, i1 } %val, 0 994 store i32 %extract0, i32 addrspace(1)* %out2 995 ret void 996} 997 998; GCN-LABEL: {{^}}atomic_cmpxchg_i32: 999; SIVI: buffer_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 1000 1001; GFX9: global_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} 1002define amdgpu_kernel void @atomic_cmpxchg_i32(i32 addrspace(1)* %out, i32 %in, i32 %old) { 1003entry: 1004 %val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst 1005 ret void 1006} 1007 1008; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret: 1009; SIVI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 1010; SIVI: buffer_store_dword v[[RET]] 1011 1012; GFX9: global_atomic_cmpswap [[RET:v[0-9]+]], v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], off glc{{$}} 1013define amdgpu_kernel void @atomic_cmpxchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i32 %old) { 1014entry: 1015 %val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst 1016 %extract0 = extractvalue { i32, i1 } %val, 0 1017 store i32 %extract0, i32 addrspace(1)* %out2 1018 ret void 1019} 1020 1021; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64: 1022; SI: buffer_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 1023; VI: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} 1024; GFX9: global_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}} 1025define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index, i32 %old) { 1026entry: 1027 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 1028 %val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst 1029 ret void 1030} 1031 1032; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64: 1033; SI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 1034; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} 1035; SIVI: buffer_store_dword v[[RET]] 1036 1037; GFX9: global_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off glc{{$}} 1038define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index, i32 %old) { 1039entry: 1040 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 1041 %val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst 1042 %extract0 = extractvalue { i32, i1 } %val, 0 1043 store i32 %extract0, i32 addrspace(1)* %out2 1044 ret void 1045} 1046 1047; GCN-LABEL: {{^}}atomic_xor_i32_offset: 1048; SIVI: buffer_atomic_xor v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 1049 1050; GFX9: global_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 1051define amdgpu_kernel void @atomic_xor_i32_offset(i32 addrspace(1)* %out, i32 %in) { 1052entry: 1053 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 1054 %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst 1055 ret void 1056} 1057 1058; GCN-LABEL: {{^}}atomic_xor_i32_ret_offset: 1059; SIVI: buffer_atomic_xor [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 1060; SIVI: buffer_store_dword [[RET]] 1061 1062; GFX9: global_atomic_xor v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 1063define amdgpu_kernel void @atomic_xor_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 1064entry: 1065 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 1066 %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst 1067 store i32 %val, i32 addrspace(1)* %out2 1068 ret void 1069} 1070 1071; GCN-LABEL: {{^}}atomic_xor_i32_addr64_offset: 1072; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 1073; VI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 1074; GFX9: global_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}} 1075define amdgpu_kernel void @atomic_xor_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { 1076entry: 1077 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 1078 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 1079 %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst 1080 ret void 1081} 1082 1083; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset: 1084; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 1085; VI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 1086; SIVI: buffer_store_dword [[RET]] 1087 1088; GFX9: global_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off offset:16 glc{{$}} 1089define amdgpu_kernel void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 1090entry: 1091 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 1092 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 1093 %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst 1094 store i32 %val, i32 addrspace(1)* %out2 1095 ret void 1096} 1097 1098; GCN-LABEL: {{^}}atomic_xor_i32: 1099; SIVI: buffer_atomic_xor v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 1100; GFX9: global_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 1101define amdgpu_kernel void @atomic_xor_i32(i32 addrspace(1)* %out, i32 %in) { 1102entry: 1103 %val = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst 1104 ret void 1105} 1106 1107; GCN-LABEL: {{^}}atomic_xor_i32_ret: 1108; SIVI: buffer_atomic_xor [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 1109; SIVI: buffer_store_dword [[RET]] 1110 1111; GFX9: global_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 1112define amdgpu_kernel void @atomic_xor_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { 1113entry: 1114 %val = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst 1115 store i32 %val, i32 addrspace(1)* %out2 1116 ret void 1117} 1118 1119; GCN-LABEL: {{^}}atomic_xor_i32_addr64: 1120; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 1121; VI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} 1122; GFX9: global_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off{{$}} 1123define amdgpu_kernel void @atomic_xor_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { 1124entry: 1125 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 1126 %val = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst 1127 ret void 1128} 1129 1130; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64: 1131; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 1132; VI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} 1133; SIVI: buffer_store_dword [[RET]] 1134 1135; GFX9: global_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, off glc{{$}} 1136define amdgpu_kernel void @atomic_xor_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { 1137entry: 1138 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 1139 %val = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst 1140 store i32 %val, i32 addrspace(1)* %out2 1141 ret void 1142} 1143 1144; GCN-LABEL: {{^}}atomic_load_i32_offset: 1145; SI: buffer_load_dword [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 1146; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} 1147; SIVI: buffer_store_dword [[RET]] 1148 1149; GFX9: global_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], off offset:16 glc{{$}} 1150define amdgpu_kernel void @atomic_load_i32_offset(i32 addrspace(1)* %in, i32 addrspace(1)* %out) { 1151entry: 1152 %gep = getelementptr i32, i32 addrspace(1)* %in, i64 4 1153 %val = load atomic i32, i32 addrspace(1)* %gep seq_cst, align 4 1154 store i32 %val, i32 addrspace(1)* %out 1155 ret void 1156} 1157 1158; GCN-LABEL: {{^}}atomic_load_i32_negoffset: 1159; SI: buffer_load_dword [[RET:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 1160 1161; VI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0xfffffe00 1162; VI-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, -1 1163; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} 1164 1165; GFX9: global_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], off offset:-512 glc{{$}} 1166define amdgpu_kernel void @atomic_load_i32_negoffset(i32 addrspace(1)* %in, i32 addrspace(1)* %out) { 1167entry: 1168 %gep = getelementptr i32, i32 addrspace(1)* %in, i64 -128 1169 %val = load atomic i32, i32 addrspace(1)* %gep seq_cst, align 4 1170 store i32 %val, i32 addrspace(1)* %out 1171 ret void 1172} 1173 1174; GCN-LABEL: {{^}}atomic_load_f32_offset: 1175; SI: buffer_load_dword [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} 1176; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} 1177; SIVI: buffer_store_dword [[RET]] 1178 1179; GFX9: global_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], off offset:16 glc{{$}} 1180define amdgpu_kernel void @atomic_load_f32_offset(float addrspace(1)* %in, float addrspace(1)* %out) { 1181entry: 1182 %gep = getelementptr float, float addrspace(1)* %in, i64 4 1183 %val = load atomic float, float addrspace(1)* %gep seq_cst, align 4 1184 store float %val, float addrspace(1)* %out 1185 ret void 1186} 1187 1188; GCN-LABEL: {{^}}atomic_load_i32: 1189; SI: buffer_load_dword [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc 1190; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc 1191; SIVI: buffer_store_dword [[RET]] 1192 1193; GFX9: global_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], off glc 1194define amdgpu_kernel void @atomic_load_i32(i32 addrspace(1)* %in, i32 addrspace(1)* %out) { 1195entry: 1196 %val = load atomic i32, i32 addrspace(1)* %in seq_cst, align 4 1197 store i32 %val, i32 addrspace(1)* %out 1198 ret void 1199} 1200 1201; GCN-LABEL: {{^}}atomic_load_i32_addr64_offset: 1202; SI: buffer_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 1203; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} 1204; SIVI: buffer_store_dword [[RET]] 1205 1206; GFX9: global_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], off offset:16 glc{{$}} 1207define amdgpu_kernel void @atomic_load_i32_addr64_offset(i32 addrspace(1)* %in, i32 addrspace(1)* %out, i64 %index) { 1208entry: 1209 %ptr = getelementptr i32, i32 addrspace(1)* %in, i64 %index 1210 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 1211 %val = load atomic i32, i32 addrspace(1)* %gep seq_cst, align 4 1212 store i32 %val, i32 addrspace(1)* %out 1213 ret void 1214} 1215 1216; GCN-LABEL: {{^}}atomic_load_i32_addr64: 1217; SI: buffer_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} 1218; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} 1219; SIVI: buffer_store_dword [[RET]] 1220 1221; GFX9: global_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], off glc{{$}} 1222define amdgpu_kernel void @atomic_load_i32_addr64(i32 addrspace(1)* %in, i32 addrspace(1)* %out, i64 %index) { 1223entry: 1224 %ptr = getelementptr i32, i32 addrspace(1)* %in, i64 %index 1225 %val = load atomic i32, i32 addrspace(1)* %ptr seq_cst, align 4 1226 store i32 %val, i32 addrspace(1)* %out 1227 ret void 1228} 1229 1230; GCN-LABEL: {{^}}atomic_load_f32_addr64_offset: 1231; SI: buffer_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} 1232; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} 1233; SIVI: buffer_store_dword [[RET]] 1234 1235; GFX9: global_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], off offset:16 glc{{$}} 1236define amdgpu_kernel void @atomic_load_f32_addr64_offset(float addrspace(1)* %in, float addrspace(1)* %out, i64 %index) { 1237entry: 1238 %ptr = getelementptr float, float addrspace(1)* %in, i64 %index 1239 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4 1240 %val = load atomic float, float addrspace(1)* %gep seq_cst, align 4 1241 store float %val, float addrspace(1)* %out 1242 ret void 1243} 1244 1245; GCN-LABEL: {{^}}atomic_store_i32_offset: 1246; SI: buffer_store_dword {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 1247; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}} 1248; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}, off offset:16{{$}} 1249define amdgpu_kernel void @atomic_store_i32_offset(i32 %in, i32 addrspace(1)* %out) { 1250entry: 1251 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 1252 store atomic i32 %in, i32 addrspace(1)* %gep seq_cst, align 4 1253 ret void 1254} 1255 1256; GCN-LABEL: {{^}}atomic_store_i32: 1257; SI: buffer_store_dword {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 1258; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}} 1259; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}, off{{$}} 1260define amdgpu_kernel void @atomic_store_i32(i32 %in, i32 addrspace(1)* %out) { 1261entry: 1262 store atomic i32 %in, i32 addrspace(1)* %out seq_cst, align 4 1263 ret void 1264} 1265 1266; GCN-LABEL: {{^}}atomic_store_f32: 1267; SI: buffer_store_dword {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} 1268; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}} 1269; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}, off{{$}} 1270define amdgpu_kernel void @atomic_store_f32(float %in, float addrspace(1)* %out) { 1271entry: 1272 store atomic float %in, float addrspace(1)* %out seq_cst, align 4 1273 ret void 1274} 1275 1276; GCN-LABEL: {{^}}atomic_store_i32_addr64_offset: 1277; SI: buffer_store_dword {{v[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 1278; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}} 1279; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}, off offset:16{{$}} 1280define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, i32 addrspace(1)* %out, i64 %index) { 1281entry: 1282 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 1283 %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 1284 store atomic i32 %in, i32 addrspace(1)* %gep seq_cst, align 4 1285 ret void 1286} 1287 1288; GCN-LABEL: {{^}}atomic_store_f32_addr64_offset: 1289; SI: buffer_store_dword {{v[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} 1290; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}} 1291; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}, off offset:16{{$}} 1292define amdgpu_kernel void @atomic_store_f32_addr64_offset(float %in, float addrspace(1)* %out, i64 %index) { 1293entry: 1294 %ptr = getelementptr float, float addrspace(1)* %out, i64 %index 1295 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4 1296 store atomic float %in, float addrspace(1)* %gep seq_cst, align 4 1297 ret void 1298} 1299 1300; GCN-LABEL: {{^}}atomic_store_i32_addr64: 1301; SI: buffer_store_dword {{v[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 1302; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}} 1303; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}, off{{$}} 1304define amdgpu_kernel void @atomic_store_i32_addr64(i32 %in, i32 addrspace(1)* %out, i64 %index) { 1305entry: 1306 %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index 1307 store atomic i32 %in, i32 addrspace(1)* %ptr seq_cst, align 4 1308 ret void 1309} 1310 1311; GCN-LABEL: {{^}}atomic_store_f32_addr64: 1312; SI: buffer_store_dword {{v[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} 1313; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}} 1314; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}, off{{$}} 1315define amdgpu_kernel void @atomic_store_f32_addr64(float %in, float addrspace(1)* %out, i64 %index) { 1316entry: 1317 %ptr = getelementptr float, float addrspace(1)* %out, i64 %index 1318 store atomic float %in, float addrspace(1)* %ptr seq_cst, align 4 1319 ret void 1320} 1321