1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s 4 5; Test using saddr addressing mode of global_*store_* flat instructions. 6 7define amdgpu_ps void @global_store_saddr_i8_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr, i8 %data) { 8; GCN-LABEL: global_store_saddr_i8_zext_vgpr: 9; GCN: ; %bb.0: 10; GCN-NEXT: global_load_dword v0, v[0:1], off 11; GCN-NEXT: s_waitcnt vmcnt(0) 12; GCN-NEXT: global_store_byte v0, v2, s[2:3] 13; GCN-NEXT: s_endpgm 14 %voffset = load i32, i32 addrspace(1)* %voffset.ptr 15 %zext.offset = zext i32 %voffset to i64 16 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 17 store i8 %data, i8 addrspace(1)* %gep0 18 ret void 19} 20 21; Maximum positive offset on gfx10 22define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_2047(i8 addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr, i8 %data) { 23; GCN-LABEL: global_store_saddr_i8_zext_vgpr_offset_2047: 24; GCN: ; %bb.0: 25; GCN-NEXT: global_load_dword v0, v[0:1], off 26; GCN-NEXT: s_waitcnt vmcnt(0) 27; GCN-NEXT: global_store_byte v0, v2, s[2:3] offset:2047 28; GCN-NEXT: s_endpgm 29 %voffset = load i32, i32 addrspace(1)* %voffset.ptr 30 %zext.offset = zext i32 %voffset to i64 31 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 32 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 2047 33 store i8 %data, i8 addrspace(1)* %gep1 34 ret void 35} 36 37; Maximum negative offset on gfx10 38define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_neg2048(i8 addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr, i8 %data) { 39; GCN-LABEL: global_store_saddr_i8_zext_vgpr_offset_neg2048: 40; GCN: ; %bb.0: 41; GCN-NEXT: global_load_dword v0, v[0:1], off 42; GCN-NEXT: s_waitcnt vmcnt(0) 43; GCN-NEXT: global_store_byte v0, v2, s[2:3] offset:-2048 44; GCN-NEXT: s_endpgm 45 %voffset = load i32, i32 addrspace(1)* %voffset.ptr 46 %zext.offset = zext i32 %voffset to i64 47 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 48 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -2048 49 store i8 %data, i8 addrspace(1)* %gep1 50 ret void 51} 52 53; -------------------------------------------------------------------------------- 54; Uniformity edge cases 55; -------------------------------------------------------------------------------- 56 57@ptr.in.lds = internal addrspace(3) global i8 addrspace(1)* undef 58 59; Base pointer is uniform, but also in VGPRs 60define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %data) { 61; GFX9-LABEL: global_store_saddr_uniform_ptr_in_vgprs: 62; GFX9: ; %bb.0: 63; GFX9-NEXT: v_mov_b32_e32 v2, 0 64; GFX9-NEXT: ds_read_b64 v[2:3], v2 65; GFX9-NEXT: s_waitcnt lgkmcnt(0) 66; GFX9-NEXT: v_readfirstlane_b32 s0, v2 67; GFX9-NEXT: v_readfirstlane_b32 s1, v3 68; GFX9-NEXT: s_nop 4 69; GFX9-NEXT: global_store_byte v0, v1, s[0:1] 70; GFX9-NEXT: s_endpgm 71; 72; GFX10-LABEL: global_store_saddr_uniform_ptr_in_vgprs: 73; GFX10: ; %bb.0: 74; GFX10-NEXT: v_mov_b32_e32 v2, 0 75; GFX10-NEXT: ds_read_b64 v[2:3], v2 76; GFX10-NEXT: s_waitcnt lgkmcnt(0) 77; GFX10-NEXT: v_readfirstlane_b32 s0, v2 78; GFX10-NEXT: v_readfirstlane_b32 s1, v3 79; GFX10-NEXT: global_store_byte v0, v1, s[0:1] 80; GFX10-NEXT: s_endpgm 81 %sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds 82 %zext.offset = zext i32 %voffset to i64 83 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 84 store i8 %data, i8 addrspace(1)* %gep0 85 ret void 86} 87 88; Base pointer is uniform, but also in VGPRs, with imm offset 89define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voffset, i8 %data) { 90; GFX9-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset: 91; GFX9: ; %bb.0: 92; GFX9-NEXT: v_mov_b32_e32 v2, 0 93; GFX9-NEXT: ds_read_b64 v[2:3], v2 94; GFX9-NEXT: s_waitcnt lgkmcnt(0) 95; GFX9-NEXT: v_readfirstlane_b32 s0, v2 96; GFX9-NEXT: v_readfirstlane_b32 s1, v3 97; GFX9-NEXT: s_nop 4 98; GFX9-NEXT: global_store_byte v0, v1, s[0:1] offset:-120 99; GFX9-NEXT: s_endpgm 100; 101; GFX10-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset: 102; GFX10: ; %bb.0: 103; GFX10-NEXT: v_mov_b32_e32 v2, 0 104; GFX10-NEXT: ds_read_b64 v[2:3], v2 105; GFX10-NEXT: s_waitcnt lgkmcnt(0) 106; GFX10-NEXT: v_readfirstlane_b32 s0, v2 107; GFX10-NEXT: v_readfirstlane_b32 s1, v3 108; GFX10-NEXT: global_store_byte v0, v1, s[0:1] offset:-120 109; GFX10-NEXT: s_endpgm 110 %sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds 111 %zext.offset = zext i32 %voffset to i64 112 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 113 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -120 114 store i8 %data, i8 addrspace(1)* %gep1 115 ret void 116} 117 118; -------------------------------------------------------------------------------- 119; Stress various type stores 120; -------------------------------------------------------------------------------- 121 122define amdgpu_ps void @global_store_saddr_i16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i16 %data) { 123; GCN-LABEL: global_store_saddr_i16_zext_vgpr: 124; GCN: ; %bb.0: 125; GCN-NEXT: global_store_short v0, v1, s[2:3] 126; GCN-NEXT: s_endpgm 127 %zext.offset = zext i32 %voffset to i64 128 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 129 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 130 store i16 %data, i16 addrspace(1)* %gep0.cast 131 ret void 132} 133 134define amdgpu_ps void @global_store_saddr_i16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i16 %data) { 135; GCN-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128: 136; GCN: ; %bb.0: 137; GCN-NEXT: global_store_short v0, v1, s[2:3] offset:-128 138; GCN-NEXT: s_endpgm 139 %zext.offset = zext i32 %voffset to i64 140 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 141 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 142 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 143 store i16 %data, i16 addrspace(1)* %gep1.cast 144 ret void 145} 146 147define amdgpu_ps void @global_store_saddr_f16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, half %data) { 148; GCN-LABEL: global_store_saddr_f16_zext_vgpr: 149; GCN: ; %bb.0: 150; GCN-NEXT: global_store_short v0, v1, s[2:3] 151; GCN-NEXT: s_endpgm 152 %zext.offset = zext i32 %voffset to i64 153 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 154 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to half addrspace(1)* 155 store half %data, half addrspace(1)* %gep0.cast 156 ret void 157} 158 159define amdgpu_ps void @global_store_saddr_f16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, half %data) { 160; GCN-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128: 161; GCN: ; %bb.0: 162; GCN-NEXT: global_store_short v0, v1, s[2:3] offset:-128 163; GCN-NEXT: s_endpgm 164 %zext.offset = zext i32 %voffset to i64 165 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 166 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 167 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to half addrspace(1)* 168 store half %data, half addrspace(1)* %gep1.cast 169 ret void 170} 171 172define amdgpu_ps void @global_store_saddr_i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 173; GCN-LABEL: global_store_saddr_i32_zext_vgpr: 174; GCN: ; %bb.0: 175; GCN-NEXT: global_store_dword v0, v1, s[2:3] 176; GCN-NEXT: s_endpgm 177 %zext.offset = zext i32 %voffset to i64 178 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 179 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)* 180 store i32 %data, i32 addrspace(1)* %gep0.cast 181 ret void 182} 183 184define amdgpu_ps void @global_store_saddr_i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 185; GCN-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128: 186; GCN: ; %bb.0: 187; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 188; GCN-NEXT: s_endpgm 189 %zext.offset = zext i32 %voffset to i64 190 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 191 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 192 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)* 193 store i32 %data, i32 addrspace(1)* %gep1.cast 194 ret void 195} 196 197define amdgpu_ps void @global_store_saddr_f32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, float %data) { 198; GCN-LABEL: global_store_saddr_f32_zext_vgpr: 199; GCN: ; %bb.0: 200; GCN-NEXT: global_store_dword v0, v1, s[2:3] 201; GCN-NEXT: s_endpgm 202 %zext.offset = zext i32 %voffset to i64 203 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 204 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to float addrspace(1)* 205 store float %data, float addrspace(1)* %gep0.cast 206 ret void 207} 208 209define amdgpu_ps void @global_store_saddr_f32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, float %data) { 210; GCN-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128: 211; GCN: ; %bb.0: 212; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 213; GCN-NEXT: s_endpgm 214 %zext.offset = zext i32 %voffset to i64 215 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 216 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 217 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to float addrspace(1)* 218 store float %data, float addrspace(1)* %gep1.cast 219 ret void 220} 221 222define amdgpu_ps void @global_store_saddr_p3_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i8 addrspace(3)* %data) { 223; GCN-LABEL: global_store_saddr_p3_zext_vgpr: 224; GCN: ; %bb.0: 225; GCN-NEXT: global_store_dword v0, v1, s[2:3] 226; GCN-NEXT: s_endpgm 227 %zext.offset = zext i32 %voffset to i64 228 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 229 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(3)* addrspace(1)* 230 store i8 addrspace(3)* %data, i8 addrspace(3)* addrspace(1)* %gep0.cast 231 ret void 232} 233 234define amdgpu_ps void @global_store_saddr_p3_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i8 addrspace(3)* %data) { 235; GCN-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128: 236; GCN: ; %bb.0: 237; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 238; GCN-NEXT: s_endpgm 239 %zext.offset = zext i32 %voffset to i64 240 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 241 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 242 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(3)* addrspace(1)* 243 store i8 addrspace(3)* %data, i8 addrspace(3)* addrspace(1)* %gep1.cast 244 ret void 245} 246 247define amdgpu_ps void @global_store_saddr_i64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) { 248; GCN-LABEL: global_store_saddr_i64_zext_vgpr: 249; GCN: ; %bb.0: 250; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 251; GCN-NEXT: s_endpgm 252 %zext.offset = zext i32 %voffset to i64 253 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 254 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)* 255 store i64 %data, i64 addrspace(1)* %gep0.cast 256 ret void 257} 258 259define amdgpu_ps void @global_store_saddr_i64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) { 260; GCN-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128: 261; GCN: ; %bb.0: 262; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 263; GCN-NEXT: s_endpgm 264 %zext.offset = zext i32 %voffset to i64 265 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 266 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 267 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)* 268 store i64 %data, i64 addrspace(1)* %gep1.cast 269 ret void 270} 271 272define amdgpu_ps void @global_store_saddr_f64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, double %data) { 273; GCN-LABEL: global_store_saddr_f64_zext_vgpr: 274; GCN: ; %bb.0: 275; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 276; GCN-NEXT: s_endpgm 277 %zext.offset = zext i32 %voffset to i64 278 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 279 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to double addrspace(1)* 280 store double %data, double addrspace(1)* %gep0.cast 281 ret void 282} 283 284define amdgpu_ps void @global_store_saddr_f64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, double %data) { 285; GCN-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128: 286; GCN: ; %bb.0: 287; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 288; GCN-NEXT: s_endpgm 289 %zext.offset = zext i32 %voffset to i64 290 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 291 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 292 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to double addrspace(1)* 293 store double %data, double addrspace(1)* %gep1.cast 294 ret void 295} 296 297define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i32> %data) { 298; GCN-LABEL: global_store_saddr_v2i32_zext_vgpr: 299; GCN: ; %bb.0: 300; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 301; GCN-NEXT: s_endpgm 302 %zext.offset = zext i32 %voffset to i64 303 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 304 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i32> addrspace(1)* 305 store <2 x i32> %data, <2 x i32> addrspace(1)* %gep0.cast 306 ret void 307} 308 309define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i32> %data) { 310; GCN-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128: 311; GCN: ; %bb.0: 312; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 313; GCN-NEXT: s_endpgm 314 %zext.offset = zext i32 %voffset to i64 315 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 316 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 317 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i32> addrspace(1)* 318 store <2 x i32> %data, <2 x i32> addrspace(1)* %gep1.cast 319 ret void 320} 321 322define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x float> %data) { 323; GCN-LABEL: global_store_saddr_v2f32_zext_vgpr: 324; GCN: ; %bb.0: 325; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 326; GCN-NEXT: s_endpgm 327 %zext.offset = zext i32 %voffset to i64 328 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 329 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x float> addrspace(1)* 330 store <2 x float> %data, <2 x float> addrspace(1)* %gep0.cast 331 ret void 332} 333 334define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x float> %data) { 335; GCN-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128: 336; GCN: ; %bb.0: 337; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 338; GCN-NEXT: s_endpgm 339 %zext.offset = zext i32 %voffset to i64 340 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 341 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 342 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x float> addrspace(1)* 343 store <2 x float> %data, <2 x float> addrspace(1)* %gep1.cast 344 ret void 345} 346 347define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i16> %data) { 348; GCN-LABEL: global_store_saddr_v4i16_zext_vgpr: 349; GCN: ; %bb.0: 350; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 351; GCN-NEXT: s_endpgm 352 %zext.offset = zext i32 %voffset to i64 353 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 354 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i16> addrspace(1)* 355 store <4 x i16> %data, <4 x i16> addrspace(1)* %gep0.cast 356 ret void 357} 358 359define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i16> %data) { 360; GCN-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128: 361; GCN: ; %bb.0: 362; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 363; GCN-NEXT: s_endpgm 364 %zext.offset = zext i32 %voffset to i64 365 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 366 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 367 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i16> addrspace(1)* 368 store <4 x i16> %data, <4 x i16> addrspace(1)* %gep1.cast 369 ret void 370} 371 372define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x half> %data) { 373; GCN-LABEL: global_store_saddr_v4f16_zext_vgpr: 374; GCN: ; %bb.0: 375; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 376; GCN-NEXT: s_endpgm 377 %zext.offset = zext i32 %voffset to i64 378 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 379 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x half> addrspace(1)* 380 store <4 x half> %data, <4 x half> addrspace(1)* %gep0.cast 381 ret void 382} 383 384define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x half> %data) { 385; GCN-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128: 386; GCN: ; %bb.0: 387; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 388; GCN-NEXT: s_endpgm 389 %zext.offset = zext i32 %voffset to i64 390 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 391 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 392 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x half> addrspace(1)* 393 store <4 x half> %data, <4 x half> addrspace(1)* %gep1.cast 394 ret void 395} 396 397define amdgpu_ps void @global_store_saddr_p1_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i8 addrspace(1)* %data) { 398; GCN-LABEL: global_store_saddr_p1_zext_vgpr: 399; GCN: ; %bb.0: 400; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 401; GCN-NEXT: s_endpgm 402 %zext.offset = zext i32 %voffset to i64 403 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 404 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(1)* addrspace(1)* 405 store i8 addrspace(1)* %data, i8 addrspace(1)* addrspace(1)* %gep0.cast 406 ret void 407} 408 409define amdgpu_ps void @global_store_saddr_p1_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i8 addrspace(1)* %data) { 410; GCN-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128: 411; GCN: ; %bb.0: 412; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 413; GCN-NEXT: s_endpgm 414 %zext.offset = zext i32 %voffset to i64 415 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 416 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 417 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(1)* addrspace(1)* 418 store i8 addrspace(1)* %data, i8 addrspace(1)* addrspace(1)* %gep1.cast 419 ret void 420} 421 422define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <3 x i32> %data) { 423; GCN-LABEL: global_store_saddr_v3i32_zext_vgpr: 424; GCN: ; %bb.0: 425; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] 426; GCN-NEXT: s_endpgm 427 %zext.offset = zext i32 %voffset to i64 428 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 429 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <3 x i32> addrspace(1)* 430 store <3 x i32> %data, <3 x i32> addrspace(1)* %gep0.cast 431 ret void 432} 433 434define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <3 x i32> %data) { 435; GCN-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128: 436; GCN: ; %bb.0: 437; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128 438; GCN-NEXT: s_endpgm 439 %zext.offset = zext i32 %voffset to i64 440 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 441 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 442 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <3 x i32> addrspace(1)* 443 store <3 x i32> %data, <3 x i32> addrspace(1)* %gep1.cast 444 ret void 445} 446 447define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <3 x float> %data) { 448; GCN-LABEL: global_store_saddr_v3f32_zext_vgpr: 449; GCN: ; %bb.0: 450; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] 451; GCN-NEXT: s_endpgm 452 %zext.offset = zext i32 %voffset to i64 453 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 454 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <3 x float> addrspace(1)* 455 store <3 x float> %data, <3 x float> addrspace(1)* %gep0.cast 456 ret void 457} 458 459define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <3 x float> %data) { 460; GCN-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128: 461; GCN: ; %bb.0: 462; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128 463; GCN-NEXT: s_endpgm 464 %zext.offset = zext i32 %voffset to i64 465 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 466 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 467 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <3 x float> addrspace(1)* 468 store <3 x float> %data, <3 x float> addrspace(1)* %gep1.cast 469 ret void 470} 471 472define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <6 x i16> %data) { 473; GCN-LABEL: global_store_saddr_v6i16_zext_vgpr: 474; GCN: ; %bb.0: 475; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] 476; GCN-NEXT: s_endpgm 477 %zext.offset = zext i32 %voffset to i64 478 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 479 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <6 x i16> addrspace(1)* 480 store <6 x i16> %data, <6 x i16> addrspace(1)* %gep0.cast 481 ret void 482} 483 484define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <6 x i16> %data) { 485; GCN-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128: 486; GCN: ; %bb.0: 487; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128 488; GCN-NEXT: s_endpgm 489 %zext.offset = zext i32 %voffset to i64 490 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 491 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 492 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <6 x i16> addrspace(1)* 493 store <6 x i16> %data, <6 x i16> addrspace(1)* %gep1.cast 494 ret void 495} 496 497define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <6 x half> %data) { 498; GCN-LABEL: global_store_saddr_v6f16_zext_vgpr: 499; GCN: ; %bb.0: 500; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] 501; GCN-NEXT: s_endpgm 502 %zext.offset = zext i32 %voffset to i64 503 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 504 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <6 x half> addrspace(1)* 505 store <6 x half> %data, <6 x half> addrspace(1)* %gep0.cast 506 ret void 507} 508 509define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <6 x half> %data) { 510; GCN-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128: 511; GCN: ; %bb.0: 512; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128 513; GCN-NEXT: s_endpgm 514 %zext.offset = zext i32 %voffset to i64 515 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 516 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 517 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <6 x half> addrspace(1)* 518 store <6 x half> %data, <6 x half> addrspace(1)* %gep1.cast 519 ret void 520} 521 522define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i32> %data) { 523; GCN-LABEL: global_store_saddr_v4i32_zext_vgpr: 524; GCN: ; %bb.0: 525; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 526; GCN-NEXT: s_endpgm 527 %zext.offset = zext i32 %voffset to i64 528 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 529 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i32> addrspace(1)* 530 store <4 x i32> %data, <4 x i32> addrspace(1)* %gep0.cast 531 ret void 532} 533 534define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i32> %data) { 535; GCN-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128: 536; GCN: ; %bb.0: 537; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 538; GCN-NEXT: s_endpgm 539 %zext.offset = zext i32 %voffset to i64 540 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 541 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 542 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i32> addrspace(1)* 543 store <4 x i32> %data, <4 x i32> addrspace(1)* %gep1.cast 544 ret void 545} 546 547define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x float> %data) { 548; GCN-LABEL: global_store_saddr_v4f32_zext_vgpr: 549; GCN: ; %bb.0: 550; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 551; GCN-NEXT: s_endpgm 552 %zext.offset = zext i32 %voffset to i64 553 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 554 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x float> addrspace(1)* 555 store <4 x float> %data, <4 x float> addrspace(1)* %gep0.cast 556 ret void 557} 558 559define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x float> %data) { 560; GCN-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128: 561; GCN: ; %bb.0: 562; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 563; GCN-NEXT: s_endpgm 564 %zext.offset = zext i32 %voffset to i64 565 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 566 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 567 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x float> addrspace(1)* 568 store <4 x float> %data, <4 x float> addrspace(1)* %gep1.cast 569 ret void 570} 571 572define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i64> %data) { 573; GCN-LABEL: global_store_saddr_v2i64_zext_vgpr: 574; GCN: ; %bb.0: 575; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 576; GCN-NEXT: s_endpgm 577 %zext.offset = zext i32 %voffset to i64 578 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 579 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i64> addrspace(1)* 580 store <2 x i64> %data, <2 x i64> addrspace(1)* %gep0.cast 581 ret void 582} 583 584define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i64> %data) { 585; GCN-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128: 586; GCN: ; %bb.0: 587; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 588; GCN-NEXT: s_endpgm 589 %zext.offset = zext i32 %voffset to i64 590 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 591 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 592 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i64> addrspace(1)* 593 store <2 x i64> %data, <2 x i64> addrspace(1)* %gep1.cast 594 ret void 595} 596 597define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x double> %data) { 598; GCN-LABEL: global_store_saddr_v2f64_zext_vgpr: 599; GCN: ; %bb.0: 600; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 601; GCN-NEXT: s_endpgm 602 %zext.offset = zext i32 %voffset to i64 603 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 604 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x double> addrspace(1)* 605 store <2 x double> %data, <2 x double> addrspace(1)* %gep0.cast 606 ret void 607} 608 609define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x double> %data) { 610; GCN-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128: 611; GCN: ; %bb.0: 612; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 613; GCN-NEXT: s_endpgm 614 %zext.offset = zext i32 %voffset to i64 615 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 616 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 617 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x double> addrspace(1)* 618 store <2 x double> %data, <2 x double> addrspace(1)* %gep1.cast 619 ret void 620} 621 622define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <8 x i16> %data) { 623; GCN-LABEL: global_store_saddr_v8i16_zext_vgpr: 624; GCN: ; %bb.0: 625; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 626; GCN-NEXT: s_endpgm 627 %zext.offset = zext i32 %voffset to i64 628 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 629 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <8 x i16> addrspace(1)* 630 store <8 x i16> %data, <8 x i16> addrspace(1)* %gep0.cast 631 ret void 632} 633 634define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <8 x i16> %data) { 635; GCN-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128: 636; GCN: ; %bb.0: 637; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 638; GCN-NEXT: s_endpgm 639 %zext.offset = zext i32 %voffset to i64 640 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 641 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 642 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <8 x i16> addrspace(1)* 643 store <8 x i16> %data, <8 x i16> addrspace(1)* %gep1.cast 644 ret void 645} 646 647define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <8 x half> %data) { 648; GCN-LABEL: global_store_saddr_v8f16_zext_vgpr: 649; GCN: ; %bb.0: 650; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 651; GCN-NEXT: s_endpgm 652 %zext.offset = zext i32 %voffset to i64 653 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 654 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <8 x half> addrspace(1)* 655 store <8 x half> %data, <8 x half> addrspace(1)* %gep0.cast 656 ret void 657} 658 659define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <8 x half> %data) { 660; GCN-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128: 661; GCN: ; %bb.0: 662; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 663; GCN-NEXT: s_endpgm 664 %zext.offset = zext i32 %voffset to i64 665 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 666 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 667 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <8 x half> addrspace(1)* 668 store <8 x half> %data, <8 x half> addrspace(1)* %gep1.cast 669 ret void 670} 671 672define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i8 addrspace(1)*> %data) { 673; GCN-LABEL: global_store_saddr_v2p1_zext_vgpr: 674; GCN: ; %bb.0: 675; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 676; GCN-NEXT: s_endpgm 677 %zext.offset = zext i32 %voffset to i64 678 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 679 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i8 addrspace(1)*> addrspace(1)* 680 store <2 x i8 addrspace(1)*> %data, <2 x i8 addrspace(1)*> addrspace(1)* %gep0.cast 681 ret void 682} 683 684define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i8 addrspace(1)*> %data) { 685; GCN-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128: 686; GCN: ; %bb.0: 687; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 688; GCN-NEXT: s_endpgm 689 %zext.offset = zext i32 %voffset to i64 690 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 691 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 692 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i8 addrspace(1)*> addrspace(1)* 693 store <2 x i8 addrspace(1)*> %data, <2 x i8 addrspace(1)*> addrspace(1)* %gep1.cast 694 ret void 695} 696 697define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i8 addrspace(3)*> %data) { 698; GCN-LABEL: global_store_saddr_v4p3_zext_vgpr: 699; GCN: ; %bb.0: 700; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 701; GCN-NEXT: s_endpgm 702 %zext.offset = zext i32 %voffset to i64 703 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 704 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i8 addrspace(3)*> addrspace(1)* 705 store <4 x i8 addrspace(3)*> %data, <4 x i8 addrspace(3)*> addrspace(1)* %gep0.cast 706 ret void 707} 708 709define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i8 addrspace(3)*> %data) { 710; GCN-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128: 711; GCN: ; %bb.0: 712; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 713; GCN-NEXT: s_endpgm 714 %zext.offset = zext i32 %voffset to i64 715 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 716 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 717 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i8 addrspace(3)*> addrspace(1)* 718 store <4 x i8 addrspace(3)*> %data, <4 x i8 addrspace(3)*> addrspace(1)* %gep1.cast 719 ret void 720} 721 722; -------------------------------------------------------------------------------- 723; Atomic store 724; -------------------------------------------------------------------------------- 725 726define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 727; GFX9-LABEL: atomic_global_store_saddr_i32_zext_vgpr: 728; GFX9: ; %bb.0: 729; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 730; GFX9-NEXT: global_store_dword v0, v1, s[2:3] 731; GFX9-NEXT: s_endpgm 732; 733; GFX10-LABEL: atomic_global_store_saddr_i32_zext_vgpr: 734; GFX10: ; %bb.0: 735; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 736; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 737; GFX10-NEXT: global_store_dword v0, v1, s[2:3] 738; GFX10-NEXT: s_endpgm 739 %zext.offset = zext i32 %voffset to i64 740 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 741 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)* 742 store atomic i32 %data, i32 addrspace(1)* %gep0.cast seq_cst, align 4 743 ret void 744} 745 746define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 747; GFX9-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128: 748; GFX9: ; %bb.0: 749; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 750; GFX9-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 751; GFX9-NEXT: s_endpgm 752; 753; GFX10-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128: 754; GFX10: ; %bb.0: 755; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 756; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 757; GFX10-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 758; GFX10-NEXT: s_endpgm 759 %zext.offset = zext i32 %voffset to i64 760 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 761 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 762 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)* 763 store atomic i32 %data, i32 addrspace(1)* %gep1.cast seq_cst, align 4 764 ret void 765} 766 767define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) { 768; GFX9-LABEL: atomic_global_store_saddr_i64_zext_vgpr: 769; GFX9: ; %bb.0: 770; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 771; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 772; GFX9-NEXT: s_endpgm 773; 774; GFX10-LABEL: atomic_global_store_saddr_i64_zext_vgpr: 775; GFX10: ; %bb.0: 776; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 777; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 778; GFX10-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 779; GFX10-NEXT: s_endpgm 780 %zext.offset = zext i32 %voffset to i64 781 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 782 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)* 783 store atomic i64 %data, i64 addrspace(1)* %gep0.cast seq_cst, align 8 784 ret void 785} 786 787define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) { 788; GFX9-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128: 789; GFX9: ; %bb.0: 790; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 791; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 792; GFX9-NEXT: s_endpgm 793; 794; GFX10-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128: 795; GFX10: ; %bb.0: 796; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 797; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 798; GFX10-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 799; GFX10-NEXT: s_endpgm 800 %zext.offset = zext i32 %voffset to i64 801 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 802 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 803 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)* 804 store atomic i64 %data, i64 addrspace(1)* %gep1.cast seq_cst, align 8 805 ret void 806} 807 808; -------------------------------------------------------------------------------- 809; D16 HI store (hi 16) 810; -------------------------------------------------------------------------------- 811 812define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %data) { 813; GCN-LABEL: global_store_saddr_i16_d16hi_zext_vgpr: 814; GCN: ; %bb.0: 815; GCN-NEXT: global_store_short_d16_hi v0, v1, s[2:3] 816; GCN-NEXT: s_endpgm 817 %zext.offset = zext i32 %voffset to i64 818 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 819 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 820 %data.hi = extractelement <2 x i16> %data, i32 1 821 store i16 %data.hi, i16 addrspace(1)* %gep0.cast 822 ret void 823} 824 825define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %data) { 826; GCN-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128: 827; GCN: ; %bb.0: 828; GCN-NEXT: global_store_short_d16_hi v0, v1, s[2:3] offset:-128 829; GCN-NEXT: s_endpgm 830 %zext.offset = zext i32 %voffset to i64 831 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 832 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 833 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 834 %data.hi = extractelement <2 x i16> %data, i32 1 835 store i16 %data.hi, i16 addrspace(1)* %gep1.cast 836 ret void 837} 838 839define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %data) { 840; GCN-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr: 841; GCN: ; %bb.0: 842; GCN-NEXT: global_store_byte_d16_hi v0, v1, s[2:3] 843; GCN-NEXT: s_endpgm 844 %zext.offset = zext i32 %voffset to i64 845 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 846 %data.hi = extractelement <2 x i16> %data, i32 1 847 %data.hi.trunc = trunc i16 %data.hi to i8 848 store i8 %data.hi.trunc, i8 addrspace(1)* %gep0 849 ret void 850} 851 852define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %data) { 853; GCN-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128: 854; GCN: ; %bb.0: 855; GCN-NEXT: global_store_byte_d16_hi v0, v1, s[2:3] offset:-128 856; GCN-NEXT: s_endpgm 857 %zext.offset = zext i32 %voffset to i64 858 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 859 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 860 %data.hi = extractelement <2 x i16> %data, i32 1 861 %data.hi.trunc = trunc i16 %data.hi to i8 862 store i8 %data.hi.trunc, i8 addrspace(1)* %gep1 863 ret void 864} 865