1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s 4 5; Test using saddr addressing mode of global_*store_* flat instructions. 6 7define amdgpu_ps void @global_store_saddr_i8_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr, i8 %data) { 8; GCN-LABEL: global_store_saddr_i8_zext_vgpr: 9; GCN: ; %bb.0: 10; GCN-NEXT: global_load_dword v0, v[0:1], off 11; GCN-NEXT: s_waitcnt vmcnt(0) 12; GCN-NEXT: global_store_byte v0, v2, s[2:3] 13; GCN-NEXT: s_endpgm 14 %voffset = load i32, i32 addrspace(1)* %voffset.ptr 15 %zext.offset = zext i32 %voffset to i64 16 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 17 store i8 %data, i8 addrspace(1)* %gep0 18 ret void 19} 20 21; Maximum positive offset on gfx10 22define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_2047(i8 addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr, i8 %data) { 23; GCN-LABEL: global_store_saddr_i8_zext_vgpr_offset_2047: 24; GCN: ; %bb.0: 25; GCN-NEXT: global_load_dword v0, v[0:1], off 26; GCN-NEXT: s_waitcnt vmcnt(0) 27; GCN-NEXT: global_store_byte v0, v2, s[2:3] offset:2047 28; GCN-NEXT: s_endpgm 29 %voffset = load i32, i32 addrspace(1)* %voffset.ptr 30 %zext.offset = zext i32 %voffset to i64 31 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 32 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 2047 33 store i8 %data, i8 addrspace(1)* %gep1 34 ret void 35} 36 37; Maximum negative offset on gfx10 38define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_neg2048(i8 addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr, i8 %data) { 39; GCN-LABEL: global_store_saddr_i8_zext_vgpr_offset_neg2048: 40; GCN: ; %bb.0: 41; GCN-NEXT: global_load_dword v0, v[0:1], off 42; GCN-NEXT: s_waitcnt vmcnt(0) 43; GCN-NEXT: global_store_byte v0, v2, s[2:3] offset:-2048 44; GCN-NEXT: s_endpgm 45 %voffset = load i32, i32 addrspace(1)* %voffset.ptr 46 %zext.offset = zext i32 %voffset to i64 47 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 48 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -2048 49 store i8 %data, i8 addrspace(1)* %gep1 50 ret void 51} 52 53; -------------------------------------------------------------------------------- 54; Uniformity edge cases 55; -------------------------------------------------------------------------------- 56 57@ptr.in.lds = internal addrspace(3) global i8 addrspace(1)* undef 58 59; Base pointer is uniform, but also in VGPRs 60define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %data) { 61; GCN-LABEL: global_store_saddr_uniform_ptr_in_vgprs: 62; GCN: ; %bb.0: 63; GCN-NEXT: v_mov_b32_e32 v2, 0 64; GCN-NEXT: ds_read_b64 v[2:3], v2 65; GCN-NEXT: s_waitcnt lgkmcnt(0) 66; GCN-NEXT: v_readfirstlane_b32 s0, v2 67; GCN-NEXT: v_readfirstlane_b32 s1, v3 68; GCN-NEXT: s_nop 4 69; GCN-NEXT: global_store_byte v0, v1, s[0:1] 70; GCN-NEXT: s_endpgm 71 %sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds 72 %zext.offset = zext i32 %voffset to i64 73 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 74 store i8 %data, i8 addrspace(1)* %gep0 75 ret void 76} 77 78; Base pointer is uniform, but also in VGPRs, with imm offset 79define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voffset, i8 %data) { 80; GCN-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset: 81; GCN: ; %bb.0: 82; GCN-NEXT: v_mov_b32_e32 v2, 0 83; GCN-NEXT: ds_read_b64 v[2:3], v2 84; GCN-NEXT: s_waitcnt lgkmcnt(0) 85; GCN-NEXT: v_readfirstlane_b32 s0, v2 86; GCN-NEXT: v_readfirstlane_b32 s1, v3 87; GCN-NEXT: s_nop 4 88; GCN-NEXT: global_store_byte v0, v1, s[0:1] offset:-120 89; GCN-NEXT: s_endpgm 90 %sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds 91 %zext.offset = zext i32 %voffset to i64 92 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 93 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -120 94 store i8 %data, i8 addrspace(1)* %gep1 95 ret void 96} 97 98; -------------------------------------------------------------------------------- 99; Stress various type stores 100; -------------------------------------------------------------------------------- 101 102define amdgpu_ps void @global_store_saddr_i16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i16 %data) { 103; GCN-LABEL: global_store_saddr_i16_zext_vgpr: 104; GCN: ; %bb.0: 105; GCN-NEXT: global_store_short v0, v1, s[2:3] 106; GCN-NEXT: s_endpgm 107 %zext.offset = zext i32 %voffset to i64 108 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 109 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 110 store i16 %data, i16 addrspace(1)* %gep0.cast 111 ret void 112} 113 114define amdgpu_ps void @global_store_saddr_i16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i16 %data) { 115; GCN-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128: 116; GCN: ; %bb.0: 117; GCN-NEXT: global_store_short v0, v1, s[2:3] offset:-128 118; GCN-NEXT: s_endpgm 119 %zext.offset = zext i32 %voffset to i64 120 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 121 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 122 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 123 store i16 %data, i16 addrspace(1)* %gep1.cast 124 ret void 125} 126 127define amdgpu_ps void @global_store_saddr_f16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, half %data) { 128; GCN-LABEL: global_store_saddr_f16_zext_vgpr: 129; GCN: ; %bb.0: 130; GCN-NEXT: global_store_short v0, v1, s[2:3] 131; GCN-NEXT: s_endpgm 132 %zext.offset = zext i32 %voffset to i64 133 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 134 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to half addrspace(1)* 135 store half %data, half addrspace(1)* %gep0.cast 136 ret void 137} 138 139define amdgpu_ps void @global_store_saddr_f16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, half %data) { 140; GCN-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128: 141; GCN: ; %bb.0: 142; GCN-NEXT: global_store_short v0, v1, s[2:3] offset:-128 143; GCN-NEXT: s_endpgm 144 %zext.offset = zext i32 %voffset to i64 145 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 146 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 147 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to half addrspace(1)* 148 store half %data, half addrspace(1)* %gep1.cast 149 ret void 150} 151 152define amdgpu_ps void @global_store_saddr_i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 153; GCN-LABEL: global_store_saddr_i32_zext_vgpr: 154; GCN: ; %bb.0: 155; GCN-NEXT: global_store_dword v0, v1, s[2:3] 156; GCN-NEXT: s_endpgm 157 %zext.offset = zext i32 %voffset to i64 158 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 159 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)* 160 store i32 %data, i32 addrspace(1)* %gep0.cast 161 ret void 162} 163 164define amdgpu_ps void @global_store_saddr_i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 165; GCN-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128: 166; GCN: ; %bb.0: 167; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 168; GCN-NEXT: s_endpgm 169 %zext.offset = zext i32 %voffset to i64 170 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 171 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 172 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)* 173 store i32 %data, i32 addrspace(1)* %gep1.cast 174 ret void 175} 176 177define amdgpu_ps void @global_store_saddr_f32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, float %data) { 178; GCN-LABEL: global_store_saddr_f32_zext_vgpr: 179; GCN: ; %bb.0: 180; GCN-NEXT: global_store_dword v0, v1, s[2:3] 181; GCN-NEXT: s_endpgm 182 %zext.offset = zext i32 %voffset to i64 183 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 184 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to float addrspace(1)* 185 store float %data, float addrspace(1)* %gep0.cast 186 ret void 187} 188 189define amdgpu_ps void @global_store_saddr_f32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, float %data) { 190; GCN-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128: 191; GCN: ; %bb.0: 192; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 193; GCN-NEXT: s_endpgm 194 %zext.offset = zext i32 %voffset to i64 195 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 196 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 197 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to float addrspace(1)* 198 store float %data, float addrspace(1)* %gep1.cast 199 ret void 200} 201 202define amdgpu_ps void @global_store_saddr_p3_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i8 addrspace(3)* %data) { 203; GCN-LABEL: global_store_saddr_p3_zext_vgpr: 204; GCN: ; %bb.0: 205; GCN-NEXT: global_store_dword v0, v1, s[2:3] 206; GCN-NEXT: s_endpgm 207 %zext.offset = zext i32 %voffset to i64 208 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 209 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(3)* addrspace(1)* 210 store i8 addrspace(3)* %data, i8 addrspace(3)* addrspace(1)* %gep0.cast 211 ret void 212} 213 214define amdgpu_ps void @global_store_saddr_p3_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i8 addrspace(3)* %data) { 215; GCN-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128: 216; GCN: ; %bb.0: 217; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 218; GCN-NEXT: s_endpgm 219 %zext.offset = zext i32 %voffset to i64 220 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 221 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 222 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(3)* addrspace(1)* 223 store i8 addrspace(3)* %data, i8 addrspace(3)* addrspace(1)* %gep1.cast 224 ret void 225} 226 227define amdgpu_ps void @global_store_saddr_i64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) { 228; GCN-LABEL: global_store_saddr_i64_zext_vgpr: 229; GCN: ; %bb.0: 230; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 231; GCN-NEXT: s_endpgm 232 %zext.offset = zext i32 %voffset to i64 233 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 234 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)* 235 store i64 %data, i64 addrspace(1)* %gep0.cast 236 ret void 237} 238 239define amdgpu_ps void @global_store_saddr_i64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) { 240; GCN-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128: 241; GCN: ; %bb.0: 242; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 243; GCN-NEXT: s_endpgm 244 %zext.offset = zext i32 %voffset to i64 245 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 246 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 247 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)* 248 store i64 %data, i64 addrspace(1)* %gep1.cast 249 ret void 250} 251 252define amdgpu_ps void @global_store_saddr_f64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, double %data) { 253; GCN-LABEL: global_store_saddr_f64_zext_vgpr: 254; GCN: ; %bb.0: 255; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 256; GCN-NEXT: s_endpgm 257 %zext.offset = zext i32 %voffset to i64 258 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 259 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to double addrspace(1)* 260 store double %data, double addrspace(1)* %gep0.cast 261 ret void 262} 263 264define amdgpu_ps void @global_store_saddr_f64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, double %data) { 265; GCN-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128: 266; GCN: ; %bb.0: 267; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 268; GCN-NEXT: s_endpgm 269 %zext.offset = zext i32 %voffset to i64 270 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 271 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 272 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to double addrspace(1)* 273 store double %data, double addrspace(1)* %gep1.cast 274 ret void 275} 276 277define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i32> %data) { 278; GCN-LABEL: global_store_saddr_v2i32_zext_vgpr: 279; GCN: ; %bb.0: 280; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 281; GCN-NEXT: s_endpgm 282 %zext.offset = zext i32 %voffset to i64 283 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 284 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i32> addrspace(1)* 285 store <2 x i32> %data, <2 x i32> addrspace(1)* %gep0.cast 286 ret void 287} 288 289define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i32> %data) { 290; GCN-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128: 291; GCN: ; %bb.0: 292; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 293; GCN-NEXT: s_endpgm 294 %zext.offset = zext i32 %voffset to i64 295 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 296 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 297 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i32> addrspace(1)* 298 store <2 x i32> %data, <2 x i32> addrspace(1)* %gep1.cast 299 ret void 300} 301 302define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x float> %data) { 303; GCN-LABEL: global_store_saddr_v2f32_zext_vgpr: 304; GCN: ; %bb.0: 305; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 306; GCN-NEXT: s_endpgm 307 %zext.offset = zext i32 %voffset to i64 308 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 309 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x float> addrspace(1)* 310 store <2 x float> %data, <2 x float> addrspace(1)* %gep0.cast 311 ret void 312} 313 314define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x float> %data) { 315; GCN-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128: 316; GCN: ; %bb.0: 317; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 318; GCN-NEXT: s_endpgm 319 %zext.offset = zext i32 %voffset to i64 320 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 321 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 322 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x float> addrspace(1)* 323 store <2 x float> %data, <2 x float> addrspace(1)* %gep1.cast 324 ret void 325} 326 327define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i16> %data) { 328; GCN-LABEL: global_store_saddr_v4i16_zext_vgpr: 329; GCN: ; %bb.0: 330; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 331; GCN-NEXT: s_endpgm 332 %zext.offset = zext i32 %voffset to i64 333 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 334 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i16> addrspace(1)* 335 store <4 x i16> %data, <4 x i16> addrspace(1)* %gep0.cast 336 ret void 337} 338 339define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i16> %data) { 340; GCN-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128: 341; GCN: ; %bb.0: 342; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 343; GCN-NEXT: s_endpgm 344 %zext.offset = zext i32 %voffset to i64 345 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 346 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 347 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i16> addrspace(1)* 348 store <4 x i16> %data, <4 x i16> addrspace(1)* %gep1.cast 349 ret void 350} 351 352define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x half> %data) { 353; GCN-LABEL: global_store_saddr_v4f16_zext_vgpr: 354; GCN: ; %bb.0: 355; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 356; GCN-NEXT: s_endpgm 357 %zext.offset = zext i32 %voffset to i64 358 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 359 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x half> addrspace(1)* 360 store <4 x half> %data, <4 x half> addrspace(1)* %gep0.cast 361 ret void 362} 363 364define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x half> %data) { 365; GCN-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128: 366; GCN: ; %bb.0: 367; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 368; GCN-NEXT: s_endpgm 369 %zext.offset = zext i32 %voffset to i64 370 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 371 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 372 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x half> addrspace(1)* 373 store <4 x half> %data, <4 x half> addrspace(1)* %gep1.cast 374 ret void 375} 376 377define amdgpu_ps void @global_store_saddr_p1_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i8 addrspace(1)* %data) { 378; GCN-LABEL: global_store_saddr_p1_zext_vgpr: 379; GCN: ; %bb.0: 380; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 381; GCN-NEXT: s_endpgm 382 %zext.offset = zext i32 %voffset to i64 383 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 384 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(1)* addrspace(1)* 385 store i8 addrspace(1)* %data, i8 addrspace(1)* addrspace(1)* %gep0.cast 386 ret void 387} 388 389define amdgpu_ps void @global_store_saddr_p1_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i8 addrspace(1)* %data) { 390; GCN-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128: 391; GCN: ; %bb.0: 392; GCN-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 393; GCN-NEXT: s_endpgm 394 %zext.offset = zext i32 %voffset to i64 395 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 396 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 397 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(1)* addrspace(1)* 398 store i8 addrspace(1)* %data, i8 addrspace(1)* addrspace(1)* %gep1.cast 399 ret void 400} 401 402define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <3 x i32> %data) { 403; GCN-LABEL: global_store_saddr_v3i32_zext_vgpr: 404; GCN: ; %bb.0: 405; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] 406; GCN-NEXT: s_endpgm 407 %zext.offset = zext i32 %voffset to i64 408 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 409 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <3 x i32> addrspace(1)* 410 store <3 x i32> %data, <3 x i32> addrspace(1)* %gep0.cast 411 ret void 412} 413 414define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <3 x i32> %data) { 415; GCN-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128: 416; GCN: ; %bb.0: 417; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128 418; GCN-NEXT: s_endpgm 419 %zext.offset = zext i32 %voffset to i64 420 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 421 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 422 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <3 x i32> addrspace(1)* 423 store <3 x i32> %data, <3 x i32> addrspace(1)* %gep1.cast 424 ret void 425} 426 427define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <3 x float> %data) { 428; GCN-LABEL: global_store_saddr_v3f32_zext_vgpr: 429; GCN: ; %bb.0: 430; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] 431; GCN-NEXT: s_endpgm 432 %zext.offset = zext i32 %voffset to i64 433 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 434 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <3 x float> addrspace(1)* 435 store <3 x float> %data, <3 x float> addrspace(1)* %gep0.cast 436 ret void 437} 438 439define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <3 x float> %data) { 440; GCN-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128: 441; GCN: ; %bb.0: 442; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128 443; GCN-NEXT: s_endpgm 444 %zext.offset = zext i32 %voffset to i64 445 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 446 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 447 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <3 x float> addrspace(1)* 448 store <3 x float> %data, <3 x float> addrspace(1)* %gep1.cast 449 ret void 450} 451 452define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <6 x i16> %data) { 453; GCN-LABEL: global_store_saddr_v6i16_zext_vgpr: 454; GCN: ; %bb.0: 455; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] 456; GCN-NEXT: s_endpgm 457 %zext.offset = zext i32 %voffset to i64 458 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 459 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <6 x i16> addrspace(1)* 460 store <6 x i16> %data, <6 x i16> addrspace(1)* %gep0.cast 461 ret void 462} 463 464define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <6 x i16> %data) { 465; GCN-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128: 466; GCN: ; %bb.0: 467; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128 468; GCN-NEXT: s_endpgm 469 %zext.offset = zext i32 %voffset to i64 470 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 471 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 472 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <6 x i16> addrspace(1)* 473 store <6 x i16> %data, <6 x i16> addrspace(1)* %gep1.cast 474 ret void 475} 476 477define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <6 x half> %data) { 478; GCN-LABEL: global_store_saddr_v6f16_zext_vgpr: 479; GCN: ; %bb.0: 480; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] 481; GCN-NEXT: s_endpgm 482 %zext.offset = zext i32 %voffset to i64 483 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 484 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <6 x half> addrspace(1)* 485 store <6 x half> %data, <6 x half> addrspace(1)* %gep0.cast 486 ret void 487} 488 489define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <6 x half> %data) { 490; GCN-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128: 491; GCN: ; %bb.0: 492; GCN-NEXT: global_store_dwordx3 v0, v[1:3], s[2:3] offset:-128 493; GCN-NEXT: s_endpgm 494 %zext.offset = zext i32 %voffset to i64 495 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 496 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 497 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <6 x half> addrspace(1)* 498 store <6 x half> %data, <6 x half> addrspace(1)* %gep1.cast 499 ret void 500} 501 502define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i32> %data) { 503; GCN-LABEL: global_store_saddr_v4i32_zext_vgpr: 504; GCN: ; %bb.0: 505; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 506; GCN-NEXT: s_endpgm 507 %zext.offset = zext i32 %voffset to i64 508 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 509 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i32> addrspace(1)* 510 store <4 x i32> %data, <4 x i32> addrspace(1)* %gep0.cast 511 ret void 512} 513 514define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i32> %data) { 515; GCN-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128: 516; GCN: ; %bb.0: 517; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 518; GCN-NEXT: s_endpgm 519 %zext.offset = zext i32 %voffset to i64 520 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 521 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 522 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i32> addrspace(1)* 523 store <4 x i32> %data, <4 x i32> addrspace(1)* %gep1.cast 524 ret void 525} 526 527define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x float> %data) { 528; GCN-LABEL: global_store_saddr_v4f32_zext_vgpr: 529; GCN: ; %bb.0: 530; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 531; GCN-NEXT: s_endpgm 532 %zext.offset = zext i32 %voffset to i64 533 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 534 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x float> addrspace(1)* 535 store <4 x float> %data, <4 x float> addrspace(1)* %gep0.cast 536 ret void 537} 538 539define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x float> %data) { 540; GCN-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128: 541; GCN: ; %bb.0: 542; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 543; GCN-NEXT: s_endpgm 544 %zext.offset = zext i32 %voffset to i64 545 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 546 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 547 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x float> addrspace(1)* 548 store <4 x float> %data, <4 x float> addrspace(1)* %gep1.cast 549 ret void 550} 551 552define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i64> %data) { 553; GCN-LABEL: global_store_saddr_v2i64_zext_vgpr: 554; GCN: ; %bb.0: 555; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 556; GCN-NEXT: s_endpgm 557 %zext.offset = zext i32 %voffset to i64 558 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 559 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i64> addrspace(1)* 560 store <2 x i64> %data, <2 x i64> addrspace(1)* %gep0.cast 561 ret void 562} 563 564define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i64> %data) { 565; GCN-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128: 566; GCN: ; %bb.0: 567; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 568; GCN-NEXT: s_endpgm 569 %zext.offset = zext i32 %voffset to i64 570 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 571 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 572 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i64> addrspace(1)* 573 store <2 x i64> %data, <2 x i64> addrspace(1)* %gep1.cast 574 ret void 575} 576 577define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x double> %data) { 578; GCN-LABEL: global_store_saddr_v2f64_zext_vgpr: 579; GCN: ; %bb.0: 580; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 581; GCN-NEXT: s_endpgm 582 %zext.offset = zext i32 %voffset to i64 583 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 584 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x double> addrspace(1)* 585 store <2 x double> %data, <2 x double> addrspace(1)* %gep0.cast 586 ret void 587} 588 589define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x double> %data) { 590; GCN-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128: 591; GCN: ; %bb.0: 592; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 593; GCN-NEXT: s_endpgm 594 %zext.offset = zext i32 %voffset to i64 595 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 596 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 597 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x double> addrspace(1)* 598 store <2 x double> %data, <2 x double> addrspace(1)* %gep1.cast 599 ret void 600} 601 602define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <8 x i16> %data) { 603; GCN-LABEL: global_store_saddr_v8i16_zext_vgpr: 604; GCN: ; %bb.0: 605; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 606; GCN-NEXT: s_endpgm 607 %zext.offset = zext i32 %voffset to i64 608 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 609 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <8 x i16> addrspace(1)* 610 store <8 x i16> %data, <8 x i16> addrspace(1)* %gep0.cast 611 ret void 612} 613 614define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <8 x i16> %data) { 615; GCN-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128: 616; GCN: ; %bb.0: 617; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 618; GCN-NEXT: s_endpgm 619 %zext.offset = zext i32 %voffset to i64 620 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 621 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 622 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <8 x i16> addrspace(1)* 623 store <8 x i16> %data, <8 x i16> addrspace(1)* %gep1.cast 624 ret void 625} 626 627define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <8 x half> %data) { 628; GCN-LABEL: global_store_saddr_v8f16_zext_vgpr: 629; GCN: ; %bb.0: 630; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 631; GCN-NEXT: s_endpgm 632 %zext.offset = zext i32 %voffset to i64 633 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 634 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <8 x half> addrspace(1)* 635 store <8 x half> %data, <8 x half> addrspace(1)* %gep0.cast 636 ret void 637} 638 639define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <8 x half> %data) { 640; GCN-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128: 641; GCN: ; %bb.0: 642; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 643; GCN-NEXT: s_endpgm 644 %zext.offset = zext i32 %voffset to i64 645 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 646 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 647 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <8 x half> addrspace(1)* 648 store <8 x half> %data, <8 x half> addrspace(1)* %gep1.cast 649 ret void 650} 651 652define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i8 addrspace(1)*> %data) { 653; GCN-LABEL: global_store_saddr_v2p1_zext_vgpr: 654; GCN: ; %bb.0: 655; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 656; GCN-NEXT: s_endpgm 657 %zext.offset = zext i32 %voffset to i64 658 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 659 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i8 addrspace(1)*> addrspace(1)* 660 store <2 x i8 addrspace(1)*> %data, <2 x i8 addrspace(1)*> addrspace(1)* %gep0.cast 661 ret void 662} 663 664define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i8 addrspace(1)*> %data) { 665; GCN-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128: 666; GCN: ; %bb.0: 667; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 668; GCN-NEXT: s_endpgm 669 %zext.offset = zext i32 %voffset to i64 670 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 671 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 672 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i8 addrspace(1)*> addrspace(1)* 673 store <2 x i8 addrspace(1)*> %data, <2 x i8 addrspace(1)*> addrspace(1)* %gep1.cast 674 ret void 675} 676 677define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i8 addrspace(3)*> %data) { 678; GCN-LABEL: global_store_saddr_v4p3_zext_vgpr: 679; GCN: ; %bb.0: 680; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] 681; GCN-NEXT: s_endpgm 682 %zext.offset = zext i32 %voffset to i64 683 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 684 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i8 addrspace(3)*> addrspace(1)* 685 store <4 x i8 addrspace(3)*> %data, <4 x i8 addrspace(3)*> addrspace(1)* %gep0.cast 686 ret void 687} 688 689define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <4 x i8 addrspace(3)*> %data) { 690; GCN-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128: 691; GCN: ; %bb.0: 692; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3] offset:-128 693; GCN-NEXT: s_endpgm 694 %zext.offset = zext i32 %voffset to i64 695 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 696 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 697 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i8 addrspace(3)*> addrspace(1)* 698 store <4 x i8 addrspace(3)*> %data, <4 x i8 addrspace(3)*> addrspace(1)* %gep1.cast 699 ret void 700} 701 702; -------------------------------------------------------------------------------- 703; Atomic store 704; -------------------------------------------------------------------------------- 705 706define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 707; GFX9-LABEL: atomic_global_store_saddr_i32_zext_vgpr: 708; GFX9: ; %bb.0: 709; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 710; GFX9-NEXT: global_store_dword v0, v1, s[2:3] 711; GFX9-NEXT: s_endpgm 712; 713; GFX10-LABEL: atomic_global_store_saddr_i32_zext_vgpr: 714; GFX10: ; %bb.0: 715; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 716; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 717; GFX10-NEXT: global_store_dword v0, v1, s[2:3] 718; GFX10-NEXT: s_endpgm 719 %zext.offset = zext i32 %voffset to i64 720 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 721 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)* 722 store atomic i32 %data, i32 addrspace(1)* %gep0.cast seq_cst, align 4 723 ret void 724} 725 726define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 727; GFX9-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128: 728; GFX9: ; %bb.0: 729; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 730; GFX9-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 731; GFX9-NEXT: s_endpgm 732; 733; GFX10-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128: 734; GFX10: ; %bb.0: 735; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 736; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 737; GFX10-NEXT: global_store_dword v0, v1, s[2:3] offset:-128 738; GFX10-NEXT: s_endpgm 739 %zext.offset = zext i32 %voffset to i64 740 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 741 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 742 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)* 743 store atomic i32 %data, i32 addrspace(1)* %gep1.cast seq_cst, align 4 744 ret void 745} 746 747define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) { 748; GFX9-LABEL: atomic_global_store_saddr_i64_zext_vgpr: 749; GFX9: ; %bb.0: 750; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 751; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 752; GFX9-NEXT: s_endpgm 753; 754; GFX10-LABEL: atomic_global_store_saddr_i64_zext_vgpr: 755; GFX10: ; %bb.0: 756; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 757; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 758; GFX10-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] 759; GFX10-NEXT: s_endpgm 760 %zext.offset = zext i32 %voffset to i64 761 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 762 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)* 763 store atomic i64 %data, i64 addrspace(1)* %gep0.cast seq_cst, align 8 764 ret void 765} 766 767define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i64 %data) { 768; GFX9-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128: 769; GFX9: ; %bb.0: 770; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 771; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 772; GFX9-NEXT: s_endpgm 773; 774; GFX10-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128: 775; GFX10: ; %bb.0: 776; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 777; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 778; GFX10-NEXT: global_store_dwordx2 v0, v[1:2], s[2:3] offset:-128 779; GFX10-NEXT: s_endpgm 780 %zext.offset = zext i32 %voffset to i64 781 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 782 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 783 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)* 784 store atomic i64 %data, i64 addrspace(1)* %gep1.cast seq_cst, align 8 785 ret void 786} 787 788; -------------------------------------------------------------------------------- 789; D16 HI store (hi 16) 790; -------------------------------------------------------------------------------- 791 792define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %data) { 793; GCN-LABEL: global_store_saddr_i16_d16hi_zext_vgpr: 794; GCN: ; %bb.0: 795; GCN-NEXT: global_store_short_d16_hi v0, v1, s[2:3] 796; GCN-NEXT: s_endpgm 797 %zext.offset = zext i32 %voffset to i64 798 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 799 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 800 %data.hi = extractelement <2 x i16> %data, i32 1 801 store i16 %data.hi, i16 addrspace(1)* %gep0.cast 802 ret void 803} 804 805define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %data) { 806; GCN-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128: 807; GCN: ; %bb.0: 808; GCN-NEXT: global_store_short_d16_hi v0, v1, s[2:3] offset:-128 809; GCN-NEXT: s_endpgm 810 %zext.offset = zext i32 %voffset to i64 811 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 812 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 813 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 814 %data.hi = extractelement <2 x i16> %data, i32 1 815 store i16 %data.hi, i16 addrspace(1)* %gep1.cast 816 ret void 817} 818 819define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %data) { 820; GCN-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr: 821; GCN: ; %bb.0: 822; GCN-NEXT: global_store_byte_d16_hi v0, v1, s[2:3] 823; GCN-NEXT: s_endpgm 824 %zext.offset = zext i32 %voffset to i64 825 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 826 %data.hi = extractelement <2 x i16> %data, i32 1 827 %data.hi.trunc = trunc i16 %data.hi to i8 828 store i8 %data.hi.trunc, i8 addrspace(1)* %gep0 829 ret void 830} 831 832define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %data) { 833; GCN-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128: 834; GCN: ; %bb.0: 835; GCN-NEXT: global_store_byte_d16_hi v0, v1, s[2:3] offset:-128 836; GCN-NEXT: s_endpgm 837 %zext.offset = zext i32 %voffset to i64 838 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 839 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 840 %data.hi = extractelement <2 x i16> %data, i32 1 841 %data.hi.trunc = trunc i16 %data.hi to i8 842 store i8 %data.hi.trunc, i8 addrspace(1)* %gep1 843 ret void 844} 845