1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 3; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10 %s 4 5; Test using saddr addressing mode of global_*load_* flat instructions. 6 7; -------------------------------------------------------------------------------- 8; No vgpr offset, constants 9; -------------------------------------------------------------------------------- 10 11; SGPR base only 12define amdgpu_ps float @global_load_saddr_i8_offset_0(i8 addrspace(1)* inreg %sbase) { 13; GCN-LABEL: global_load_saddr_i8_offset_0: 14; GCN: ; %bb.0: 15; GCN-NEXT: v_mov_b32_e32 v0, 0 16; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] 17; GCN-NEXT: s_waitcnt vmcnt(0) 18; GCN-NEXT: ; return to shader part epilog 19 %load = load i8, i8 addrspace(1)* %sbase 20 %zext = zext i8 %load to i32 21 %to.vgpr = bitcast i32 %zext to float 22 ret float %to.vgpr 23} 24 25; SGPR base with maximum gfx9 immediate offset 26define amdgpu_ps float @global_load_saddr_i8_offset_4095(i8 addrspace(1)* inreg %sbase) { 27; GFX9-LABEL: global_load_saddr_i8_offset_4095: 28; GFX9: ; %bb.0: 29; GFX9-NEXT: v_mov_b32_e32 v0, 0 30; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:4095 31; GFX9-NEXT: s_waitcnt vmcnt(0) 32; GFX9-NEXT: ; return to shader part epilog 33; 34; GFX10-LABEL: global_load_saddr_i8_offset_4095: 35; GFX10: ; %bb.0: 36; GFX10-NEXT: v_mov_b32_e32 v0, 0x800 37; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2047 38; GFX10-NEXT: s_waitcnt vmcnt(0) 39; GFX10-NEXT: ; return to shader part epilog 40 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4095 41 %load = load i8, i8 addrspace(1)* %gep0 42 %zext = zext i8 %load to i32 43 %to.vgpr = bitcast i32 %zext to float 44 ret float %to.vgpr 45} 46 47; SGPR base with maximum gfx9 immediate offset + 1 48define amdgpu_ps float @global_load_saddr_i8_offset_4096(i8 addrspace(1)* inreg %sbase) { 49; GCN-LABEL: global_load_saddr_i8_offset_4096: 50; GCN: ; %bb.0: 51; GCN-NEXT: v_mov_b32_e32 v0, 0x1000 52; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] 53; GCN-NEXT: s_waitcnt vmcnt(0) 54; GCN-NEXT: ; return to shader part epilog 55 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4096 56 %load = load i8, i8 addrspace(1)* %gep0 57 %zext = zext i8 %load to i32 58 %to.vgpr = bitcast i32 %zext to float 59 ret float %to.vgpr 60} 61 62; SGPR base with maximum gfx9 immediate offset + 2 63define amdgpu_ps float @global_load_saddr_i8_offset_4097(i8 addrspace(1)* inreg %sbase) { 64; GCN-LABEL: global_load_saddr_i8_offset_4097: 65; GCN: ; %bb.0: 66; GCN-NEXT: v_mov_b32_e32 v0, 0x1000 67; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:1 68; GCN-NEXT: s_waitcnt vmcnt(0) 69; GCN-NEXT: ; return to shader part epilog 70 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4097 71 %load = load i8, i8 addrspace(1)* %gep0 72 %zext = zext i8 %load to i32 73 %to.vgpr = bitcast i32 %zext to float 74 ret float %to.vgpr 75} 76 77; SGPR base with maximum negative gfx9 immediate offset 78define amdgpu_ps float @global_load_saddr_i8_offset_neg4096(i8 addrspace(1)* inreg %sbase) { 79; GFX9-LABEL: global_load_saddr_i8_offset_neg4096: 80; GFX9: ; %bb.0: 81; GFX9-NEXT: v_mov_b32_e32 v0, 0 82; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-4096 83; GFX9-NEXT: s_waitcnt vmcnt(0) 84; GFX9-NEXT: ; return to shader part epilog 85; 86; GFX10-LABEL: global_load_saddr_i8_offset_neg4096: 87; GFX10: ; %bb.0: 88; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0xfffff000, s2 89; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] 90; GFX10-NEXT: global_load_ubyte v0, v[0:1], off 91; GFX10-NEXT: s_waitcnt vmcnt(0) 92; GFX10-NEXT: ; return to shader part epilog 93 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4096 94 %load = load i8, i8 addrspace(1)* %gep0 95 %zext = zext i8 %load to i32 96 %to.vgpr = bitcast i32 %zext to float 97 ret float %to.vgpr 98} 99 100; SGPR base with maximum negative gfx9 immediate offset -1 101define amdgpu_ps float @global_load_saddr_i8_offset_neg4097(i8 addrspace(1)* inreg %sbase) { 102; GFX9-LABEL: global_load_saddr_i8_offset_neg4097: 103; GFX9: ; %bb.0: 104; GFX9-NEXT: v_mov_b32_e32 v0, s2 105; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 106; GFX9-NEXT: v_mov_b32_e32 v1, s3 107; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc 108; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 109; GFX9-NEXT: s_waitcnt vmcnt(0) 110; GFX9-NEXT: ; return to shader part epilog 111; 112; GFX10-LABEL: global_load_saddr_i8_offset_neg4097: 113; GFX10: ; %bb.0: 114; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0xfffff000, s2 115; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] 116; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 117; GFX10-NEXT: s_waitcnt vmcnt(0) 118; GFX10-NEXT: ; return to shader part epilog 119 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4097 120 %load = load i8, i8 addrspace(1)* %gep0 121 %zext = zext i8 %load to i32 122 %to.vgpr = bitcast i32 %zext to float 123 ret float %to.vgpr 124} 125 126; SGPR base with maximum negative gfx9 immediate offset -2 127define amdgpu_ps float @global_load_saddr_i8_offset_neg4098(i8 addrspace(1)* inreg %sbase) { 128; GFX9-LABEL: global_load_saddr_i8_offset_neg4098: 129; GFX9: ; %bb.0: 130; GFX9-NEXT: v_mov_b32_e32 v0, s2 131; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 132; GFX9-NEXT: v_mov_b32_e32 v1, s3 133; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc 134; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-2 135; GFX9-NEXT: s_waitcnt vmcnt(0) 136; GFX9-NEXT: ; return to shader part epilog 137; 138; GFX10-LABEL: global_load_saddr_i8_offset_neg4098: 139; GFX10: ; %bb.0: 140; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0xfffff000, s2 141; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] 142; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-2 143; GFX10-NEXT: s_waitcnt vmcnt(0) 144; GFX10-NEXT: ; return to shader part epilog 145 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4098 146 %load = load i8, i8 addrspace(1)* %gep0 147 %zext = zext i8 %load to i32 148 %to.vgpr = bitcast i32 %zext to float 149 ret float %to.vgpr 150} 151 152; SGPR base with maximum gfx10 immediate offset 153define amdgpu_ps float @global_load_saddr_i8_offset_2048(i8 addrspace(1)* inreg %sbase) { 154; GFX9-LABEL: global_load_saddr_i8_offset_2048: 155; GFX9: ; %bb.0: 156; GFX9-NEXT: v_mov_b32_e32 v0, 0 157; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2048 158; GFX9-NEXT: s_waitcnt vmcnt(0) 159; GFX9-NEXT: ; return to shader part epilog 160; 161; GFX10-LABEL: global_load_saddr_i8_offset_2048: 162; GFX10: ; %bb.0: 163; GFX10-NEXT: v_mov_b32_e32 v0, 0x800 164; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] 165; GFX10-NEXT: s_waitcnt vmcnt(0) 166; GFX10-NEXT: ; return to shader part epilog 167 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 2048 168 %load = load i8, i8 addrspace(1)* %gep0 169 %zext = zext i8 %load to i32 170 %to.vgpr = bitcast i32 %zext to float 171 ret float %to.vgpr 172} 173 174; SGPR base with maximum gfx10 immediate offset + 1 175define amdgpu_ps float @global_load_saddr_i8_offset_2049(i8 addrspace(1)* inreg %sbase) { 176; GFX9-LABEL: global_load_saddr_i8_offset_2049: 177; GFX9: ; %bb.0: 178; GFX9-NEXT: v_mov_b32_e32 v0, 0 179; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2049 180; GFX9-NEXT: s_waitcnt vmcnt(0) 181; GFX9-NEXT: ; return to shader part epilog 182; 183; GFX10-LABEL: global_load_saddr_i8_offset_2049: 184; GFX10: ; %bb.0: 185; GFX10-NEXT: v_mov_b32_e32 v0, 0x800 186; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:1 187; GFX10-NEXT: s_waitcnt vmcnt(0) 188; GFX10-NEXT: ; return to shader part epilog 189 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 2049 190 %load = load i8, i8 addrspace(1)* %gep0 191 %zext = zext i8 %load to i32 192 %to.vgpr = bitcast i32 %zext to float 193 ret float %to.vgpr 194} 195 196; SGPR base with maximum gfx10 immediate offset + 2 197define amdgpu_ps float @global_load_saddr_i8_offset_2050(i8 addrspace(1)* inreg %sbase) { 198; GFX9-LABEL: global_load_saddr_i8_offset_2050: 199; GFX9: ; %bb.0: 200; GFX9-NEXT: v_mov_b32_e32 v0, 0 201; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2050 202; GFX9-NEXT: s_waitcnt vmcnt(0) 203; GFX9-NEXT: ; return to shader part epilog 204; 205; GFX10-LABEL: global_load_saddr_i8_offset_2050: 206; GFX10: ; %bb.0: 207; GFX10-NEXT: v_mov_b32_e32 v0, 0x800 208; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2 209; GFX10-NEXT: s_waitcnt vmcnt(0) 210; GFX10-NEXT: ; return to shader part epilog 211 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 2050 212 %load = load i8, i8 addrspace(1)* %gep0 213 %zext = zext i8 %load to i32 214 %to.vgpr = bitcast i32 %zext to float 215 ret float %to.vgpr 216} 217 218; SGPR base with maximum negative gfx10 immediate offset 219define amdgpu_ps float @global_load_saddr_i8_offset_neg2048(i8 addrspace(1)* inreg %sbase) { 220; GCN-LABEL: global_load_saddr_i8_offset_neg2048: 221; GCN: ; %bb.0: 222; GCN-NEXT: v_mov_b32_e32 v0, 0 223; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-2048 224; GCN-NEXT: s_waitcnt vmcnt(0) 225; GCN-NEXT: ; return to shader part epilog 226 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -2048 227 %load = load i8, i8 addrspace(1)* %gep0 228 %zext = zext i8 %load to i32 229 %to.vgpr = bitcast i32 %zext to float 230 ret float %to.vgpr 231} 232 233; SGPR base with maximum negative gfx10 immediate offset - 1 234define amdgpu_ps float @global_load_saddr_i8_offset_neg2049(i8 addrspace(1)* inreg %sbase) { 235; GFX9-LABEL: global_load_saddr_i8_offset_neg2049: 236; GFX9: ; %bb.0: 237; GFX9-NEXT: v_mov_b32_e32 v0, 0 238; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-2049 239; GFX9-NEXT: s_waitcnt vmcnt(0) 240; GFX9-NEXT: ; return to shader part epilog 241; 242; GFX10-LABEL: global_load_saddr_i8_offset_neg2049: 243; GFX10: ; %bb.0: 244; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0xfffff800, s2 245; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] 246; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 247; GFX10-NEXT: s_waitcnt vmcnt(0) 248; GFX10-NEXT: ; return to shader part epilog 249 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -2049 250 %load = load i8, i8 addrspace(1)* %gep0 251 %zext = zext i8 %load to i32 252 %to.vgpr = bitcast i32 %zext to float 253 ret float %to.vgpr 254} 255 256; SGPR base with maximum negative gfx10 immediate offset - 1 257define amdgpu_ps float @global_load_saddr_i8_offset_neg2050(i8 addrspace(1)* inreg %sbase) { 258; GFX9-LABEL: global_load_saddr_i8_offset_neg2050: 259; GFX9: ; %bb.0: 260; GFX9-NEXT: v_mov_b32_e32 v0, 0 261; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-2050 262; GFX9-NEXT: s_waitcnt vmcnt(0) 263; GFX9-NEXT: ; return to shader part epilog 264; 265; GFX10-LABEL: global_load_saddr_i8_offset_neg2050: 266; GFX10: ; %bb.0: 267; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0xfffff800, s2 268; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] 269; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-2 270; GFX10-NEXT: s_waitcnt vmcnt(0) 271; GFX10-NEXT: ; return to shader part epilog 272 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -2050 273 %load = load i8, i8 addrspace(1)* %gep0 274 %zext = zext i8 %load to i32 275 %to.vgpr = bitcast i32 %zext to float 276 ret float %to.vgpr 277} 278 279define amdgpu_ps float @global_load_saddr_i8_offset_4294967295(i8 addrspace(1)* inreg %sbase) { 280; GFX9-LABEL: global_load_saddr_i8_offset_4294967295: 281; GFX9: ; %bb.0: 282; GFX9-NEXT: v_mov_b32_e32 v0, 0xfffff000 283; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:4095 284; GFX9-NEXT: s_waitcnt vmcnt(0) 285; GFX9-NEXT: ; return to shader part epilog 286; 287; GFX10-LABEL: global_load_saddr_i8_offset_4294967295: 288; GFX10: ; %bb.0: 289; GFX10-NEXT: v_mov_b32_e32 v0, 0xfffff800 290; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2047 291; GFX10-NEXT: s_waitcnt vmcnt(0) 292; GFX10-NEXT: ; return to shader part epilog 293 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294967295 294 %load = load i8, i8 addrspace(1)* %gep0 295 %zext = zext i8 %load to i32 296 %to.vgpr = bitcast i32 %zext to float 297 ret float %to.vgpr 298} 299 300define amdgpu_ps float @global_load_saddr_i8_offset_4294967296(i8 addrspace(1)* inreg %sbase) { 301; GFX9-LABEL: global_load_saddr_i8_offset_4294967296: 302; GFX9: ; %bb.0: 303; GFX9-NEXT: v_mov_b32_e32 v1, s3 304; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 305; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc 306; GFX9-NEXT: global_load_ubyte v0, v[0:1], off 307; GFX9-NEXT: s_waitcnt vmcnt(0) 308; GFX9-NEXT: ; return to shader part epilog 309; 310; GFX10-LABEL: global_load_saddr_i8_offset_4294967296: 311; GFX10: ; %bb.0: 312; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 313; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1] 314; GFX10-NEXT: global_load_ubyte v0, v[0:1], off 315; GFX10-NEXT: s_waitcnt vmcnt(0) 316; GFX10-NEXT: ; return to shader part epilog 317 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294967296 318 %load = load i8, i8 addrspace(1)* %gep0 319 %zext = zext i8 %load to i32 320 %to.vgpr = bitcast i32 %zext to float 321 ret float %to.vgpr 322} 323 324define amdgpu_ps float @global_load_saddr_i8_offset_4294967297(i8 addrspace(1)* inreg %sbase) { 325; GFX9-LABEL: global_load_saddr_i8_offset_4294967297: 326; GFX9: ; %bb.0: 327; GFX9-NEXT: v_mov_b32_e32 v1, s3 328; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 329; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc 330; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:1 331; GFX9-NEXT: s_waitcnt vmcnt(0) 332; GFX9-NEXT: ; return to shader part epilog 333; 334; GFX10-LABEL: global_load_saddr_i8_offset_4294967297: 335; GFX10: ; %bb.0: 336; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 337; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1] 338; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:1 339; GFX10-NEXT: s_waitcnt vmcnt(0) 340; GFX10-NEXT: ; return to shader part epilog 341 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294967297 342 %load = load i8, i8 addrspace(1)* %gep0 343 %zext = zext i8 %load to i32 344 %to.vgpr = bitcast i32 %zext to float 345 ret float %to.vgpr 346} 347 348define amdgpu_ps float @global_load_saddr_i8_offset_4294971391(i8 addrspace(1)* inreg %sbase) { 349; GFX9-LABEL: global_load_saddr_i8_offset_4294971391: 350; GFX9: ; %bb.0: 351; GFX9-NEXT: v_mov_b32_e32 v1, s3 352; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 353; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc 354; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 355; GFX9-NEXT: s_waitcnt vmcnt(0) 356; GFX9-NEXT: ; return to shader part epilog 357; 358; GFX10-LABEL: global_load_saddr_i8_offset_4294971391: 359; GFX10: ; %bb.0: 360; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0x800, s2 361; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1] 362; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 363; GFX10-NEXT: s_waitcnt vmcnt(0) 364; GFX10-NEXT: ; return to shader part epilog 365 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294971391 366 %load = load i8, i8 addrspace(1)* %gep0 367 %zext = zext i8 %load to i32 368 %to.vgpr = bitcast i32 %zext to float 369 ret float %to.vgpr 370} 371 372define amdgpu_ps float @global_load_saddr_i8_offset_4294971392(i8 addrspace(1)* inreg %sbase) { 373; GFX9-LABEL: global_load_saddr_i8_offset_4294971392: 374; GFX9: ; %bb.0: 375; GFX9-NEXT: v_mov_b32_e32 v0, s2 376; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 377; GFX9-NEXT: v_mov_b32_e32 v1, s3 378; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc 379; GFX9-NEXT: global_load_ubyte v0, v[0:1], off 380; GFX9-NEXT: s_waitcnt vmcnt(0) 381; GFX9-NEXT: ; return to shader part epilog 382; 383; GFX10-LABEL: global_load_saddr_i8_offset_4294971392: 384; GFX10: ; %bb.0: 385; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0x1000, s2 386; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1] 387; GFX10-NEXT: global_load_ubyte v0, v[0:1], off 388; GFX10-NEXT: s_waitcnt vmcnt(0) 389; GFX10-NEXT: ; return to shader part epilog 390 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294971392 391 %load = load i8, i8 addrspace(1)* %gep0 392 %zext = zext i8 %load to i32 393 %to.vgpr = bitcast i32 %zext to float 394 ret float %to.vgpr 395} 396 397define amdgpu_ps float @global_load_saddr_i8_offset_neg4294967295(i8 addrspace(1)* inreg %sbase) { 398; GFX9-LABEL: global_load_saddr_i8_offset_neg4294967295: 399; GFX9: ; %bb.0: 400; GFX9-NEXT: v_mov_b32_e32 v0, s2 401; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 402; GFX9-NEXT: v_mov_b32_e32 v1, s3 403; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc 404; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-4095 405; GFX9-NEXT: s_waitcnt vmcnt(0) 406; GFX9-NEXT: ; return to shader part epilog 407; 408; GFX10-LABEL: global_load_saddr_i8_offset_neg4294967295: 409; GFX10: ; %bb.0: 410; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0x800, s2 411; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] 412; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-2047 413; GFX10-NEXT: s_waitcnt vmcnt(0) 414; GFX10-NEXT: ; return to shader part epilog 415 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4294967295 416 %load = load i8, i8 addrspace(1)* %gep0 417 %zext = zext i8 %load to i32 418 %to.vgpr = bitcast i32 %zext to float 419 ret float %to.vgpr 420} 421 422define amdgpu_ps float @global_load_saddr_i8_offset_neg4294967296(i8 addrspace(1)* inreg %sbase) { 423; GFX9-LABEL: global_load_saddr_i8_offset_neg4294967296: 424; GFX9: ; %bb.0: 425; GFX9-NEXT: v_mov_b32_e32 v1, s3 426; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 427; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc 428; GFX9-NEXT: global_load_ubyte v0, v[0:1], off 429; GFX9-NEXT: s_waitcnt vmcnt(0) 430; GFX9-NEXT: ; return to shader part epilog 431; 432; GFX10-LABEL: global_load_saddr_i8_offset_neg4294967296: 433; GFX10: ; %bb.0: 434; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 435; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] 436; GFX10-NEXT: global_load_ubyte v0, v[0:1], off 437; GFX10-NEXT: s_waitcnt vmcnt(0) 438; GFX10-NEXT: ; return to shader part epilog 439 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4294967296 440 %load = load i8, i8 addrspace(1)* %gep0 441 %zext = zext i8 %load to i32 442 %to.vgpr = bitcast i32 %zext to float 443 ret float %to.vgpr 444} 445 446define amdgpu_ps float @global_load_saddr_i8_offset_neg4294967297(i8 addrspace(1)* inreg %sbase) { 447; GFX9-LABEL: global_load_saddr_i8_offset_neg4294967297: 448; GFX9: ; %bb.0: 449; GFX9-NEXT: v_mov_b32_e32 v1, s3 450; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 451; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc 452; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 453; GFX9-NEXT: s_waitcnt vmcnt(0) 454; GFX9-NEXT: ; return to shader part epilog 455; 456; GFX10-LABEL: global_load_saddr_i8_offset_neg4294967297: 457; GFX10: ; %bb.0: 458; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 459; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] 460; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 461; GFX10-NEXT: s_waitcnt vmcnt(0) 462; GFX10-NEXT: ; return to shader part epilog 463 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4294967297 464 %load = load i8, i8 addrspace(1)* %gep0 465 %zext = zext i8 %load to i32 466 %to.vgpr = bitcast i32 %zext to float 467 ret float %to.vgpr 468} 469 470; -------------------------------------------------------------------------------- 471; Basic addressing patterns 472; -------------------------------------------------------------------------------- 473 474; Basic pattern, no immediate offset. 475define amdgpu_ps float @global_load_saddr_i8_zext_vgpr(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 476; GCN-LABEL: global_load_saddr_i8_zext_vgpr: 477; GCN: ; %bb.0: 478; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] 479; GCN-NEXT: s_waitcnt vmcnt(0) 480; GCN-NEXT: ; return to shader part epilog 481 %zext.offset = zext i32 %voffset to i64 482 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 483 %load = load i8, i8 addrspace(1)* %gep0 484 %zext = zext i8 %load to i32 485 %to.vgpr = bitcast i32 %zext to float 486 ret float %to.vgpr 487} 488 489; Maximum positive offset on gfx9 490define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4095(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 491; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095: 492; GFX9: ; %bb.0: 493; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:4095 494; GFX9-NEXT: s_waitcnt vmcnt(0) 495; GFX9-NEXT: ; return to shader part epilog 496; 497; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095: 498; GFX10: ; %bb.0: 499; GFX10-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 500; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1] 501; GFX10-NEXT: v_add_co_u32 v0, vcc, 0x800, v0 502; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc 503; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 504; GFX10-NEXT: s_waitcnt vmcnt(0) 505; GFX10-NEXT: ; return to shader part epilog 506 %zext.offset = zext i32 %voffset to i64 507 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 508 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 4095 509 %load = load i8, i8 addrspace(1)* %gep1 510 %zext = zext i8 %load to i32 511 %to.vgpr = bitcast i32 %zext to float 512 ret float %to.vgpr 513} 514 515; Maximum positive offset on gfx9 + 1 516define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4096(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 517; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096: 518; GFX9: ; %bb.0: 519; GFX9-NEXT: v_mov_b32_e32 v1, s3 520; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v0 521; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 522; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 523; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 524; GFX9-NEXT: global_load_ubyte v0, v[0:1], off 525; GFX9-NEXT: s_waitcnt vmcnt(0) 526; GFX9-NEXT: ; return to shader part epilog 527; 528; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096: 529; GFX10: ; %bb.0: 530; GFX10-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 531; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1] 532; GFX10-NEXT: v_add_co_u32 v0, vcc, 0x1000, v0 533; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc 534; GFX10-NEXT: global_load_ubyte v0, v[0:1], off 535; GFX10-NEXT: s_waitcnt vmcnt(0) 536; GFX10-NEXT: ; return to shader part epilog 537 %zext.offset = zext i32 %voffset to i64 538 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 539 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 4096 540 %load = load i8, i8 addrspace(1)* %gep1 541 %zext = zext i8 %load to i32 542 %to.vgpr = bitcast i32 %zext to float 543 ret float %to.vgpr 544} 545 546; Maximum negative offset on gfx9 547define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg4096(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 548; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4096: 549; GFX9: ; %bb.0: 550; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-4096 551; GFX9-NEXT: s_waitcnt vmcnt(0) 552; GFX9-NEXT: ; return to shader part epilog 553; 554; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4096: 555; GFX10: ; %bb.0: 556; GFX10-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 557; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1] 558; GFX10-NEXT: v_add_co_u32 v0, vcc, 0xfffff000, v0 559; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, -1, v1, vcc 560; GFX10-NEXT: global_load_ubyte v0, v[0:1], off 561; GFX10-NEXT: s_waitcnt vmcnt(0) 562; GFX10-NEXT: ; return to shader part epilog 563 %zext.offset = zext i32 %voffset to i64 564 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 565 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -4096 566 %load = load i8, i8 addrspace(1)* %gep1 567 %zext = zext i8 %load to i32 568 %to.vgpr = bitcast i32 %zext to float 569 ret float %to.vgpr 570} 571 572; Maximum negative offset on gfx9 - 1 573define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg4097(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 574; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097: 575; GFX9: ; %bb.0: 576; GFX9-NEXT: v_mov_b32_e32 v1, s3 577; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v0 578; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 579; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 580; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc 581; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 582; GFX9-NEXT: s_waitcnt vmcnt(0) 583; GFX9-NEXT: ; return to shader part epilog 584; 585; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097: 586; GFX10: ; %bb.0: 587; GFX10-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 588; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1] 589; GFX10-NEXT: v_add_co_u32 v0, vcc, 0xfffff000, v0 590; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, -1, v1, vcc 591; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 592; GFX10-NEXT: s_waitcnt vmcnt(0) 593; GFX10-NEXT: ; return to shader part epilog 594 %zext.offset = zext i32 %voffset to i64 595 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 596 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -4097 597 %load = load i8, i8 addrspace(1)* %gep1 598 %zext = zext i8 %load to i32 599 %to.vgpr = bitcast i32 %zext to float 600 ret float %to.vgpr 601} 602 603; Maximum positive offset on gfx10 604define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_2047(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 605; GCN-LABEL: global_load_saddr_i8_zext_vgpr_offset_2047: 606; GCN: ; %bb.0: 607; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2047 608; GCN-NEXT: s_waitcnt vmcnt(0) 609; GCN-NEXT: ; return to shader part epilog 610 %zext.offset = zext i32 %voffset to i64 611 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 612 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 2047 613 %load = load i8, i8 addrspace(1)* %gep1 614 %zext = zext i8 %load to i32 615 %to.vgpr = bitcast i32 %zext to float 616 ret float %to.vgpr 617} 618 619; Maximum positive offset on gfx10 + 1 620define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_2048(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 621; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_2048: 622; GFX9: ; %bb.0: 623; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:2048 624; GFX9-NEXT: s_waitcnt vmcnt(0) 625; GFX9-NEXT: ; return to shader part epilog 626; 627; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_2048: 628; GFX10: ; %bb.0: 629; GFX10-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 630; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1] 631; GFX10-NEXT: v_add_co_u32 v0, vcc, 0x800, v0 632; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc 633; GFX10-NEXT: global_load_ubyte v0, v[0:1], off 634; GFX10-NEXT: s_waitcnt vmcnt(0) 635; GFX10-NEXT: ; return to shader part epilog 636 %zext.offset = zext i32 %voffset to i64 637 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 638 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 2048 639 %load = load i8, i8 addrspace(1)* %gep1 640 %zext = zext i8 %load to i32 641 %to.vgpr = bitcast i32 %zext to float 642 ret float %to.vgpr 643} 644 645; Maximum negative offset on gfx10 646define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg2048(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 647; GCN-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2048: 648; GCN: ; %bb.0: 649; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-2048 650; GCN-NEXT: s_waitcnt vmcnt(0) 651; GCN-NEXT: ; return to shader part epilog 652 %zext.offset = zext i32 %voffset to i64 653 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 654 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -2048 655 %load = load i8, i8 addrspace(1)* %gep1 656 %zext = zext i8 %load to i32 657 %to.vgpr = bitcast i32 %zext to float 658 ret float %to.vgpr 659} 660 661; Maximum negative offset on gfx10 - 1 662define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg2049(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 663; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2049: 664; GFX9: ; %bb.0: 665; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-2049 666; GFX9-NEXT: s_waitcnt vmcnt(0) 667; GFX9-NEXT: ; return to shader part epilog 668; 669; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2049: 670; GFX10: ; %bb.0: 671; GFX10-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 672; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1] 673; GFX10-NEXT: v_add_co_u32 v0, vcc, 0xfffff800, v0 674; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, -1, v1, vcc 675; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 676; GFX10-NEXT: s_waitcnt vmcnt(0) 677; GFX10-NEXT: ; return to shader part epilog 678 %zext.offset = zext i32 %voffset to i64 679 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 680 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -2049 681 %load = load i8, i8 addrspace(1)* %gep1 682 %zext = zext i8 %load to i32 683 %to.vgpr = bitcast i32 %zext to float 684 ret float %to.vgpr 685} 686 687; Maximum positive offset on gfx9, and immediate needs to be moved lower. 688define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4095_gep_order(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 689; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095_gep_order: 690; GFX9: ; %bb.0: 691; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] offset:4095 692; GFX9-NEXT: s_waitcnt vmcnt(0) 693; GFX9-NEXT: ; return to shader part epilog 694; 695; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095_gep_order: 696; GFX10: ; %bb.0: 697; GFX10-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 698; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1] 699; GFX10-NEXT: v_add_co_u32 v0, vcc, 0x800, v0 700; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc 701; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 702; GFX10-NEXT: s_waitcnt vmcnt(0) 703; GFX10-NEXT: ; return to shader part epilog 704 %zext.offset = zext i32 %voffset to i64 705 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4095 706 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 %zext.offset 707 %load = load i8, i8 addrspace(1)* %gep1 708 %zext = zext i8 %load to i32 709 %to.vgpr = bitcast i32 %zext to float 710 ret float %to.vgpr 711} 712 713; pointer addressing done in integers 714define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_ptrtoint(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 715; GCN-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint: 716; GCN: ; %bb.0: 717; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] 718; GCN-NEXT: s_waitcnt vmcnt(0) 719; GCN-NEXT: ; return to shader part epilog 720 %zext.offset = zext i32 %voffset to i64 721 %sbase.as.int = ptrtoint i8 addrspace(1)* %sbase to i64 722 %add = add i64 %sbase.as.int, %zext.offset 723 %dirty.gep = inttoptr i64 %add to i8 addrspace(1)* 724 %load = load i8, i8 addrspace(1)* %dirty.gep 725 %zext = zext i8 %load to i32 726 %to.vgpr = bitcast i32 %zext to float 727 ret float %to.vgpr 728} 729 730; zext forced to LHS of addressing expression 731define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 732; GCN-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add: 733; GCN: ; %bb.0: 734; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] 735; GCN-NEXT: s_waitcnt vmcnt(0) 736; GCN-NEXT: ; return to shader part epilog 737 %zext.offset = zext i32 %voffset to i64 738 %sbase.as.int = ptrtoint i8 addrspace(1)* %sbase to i64 739 %add = add i64 %zext.offset, %sbase.as.int 740 %dirty.gep = inttoptr i64 %add to i8 addrspace(1)* 741 %load = load i8, i8 addrspace(1)* %dirty.gep 742 %zext = zext i8 %load to i32 743 %to.vgpr = bitcast i32 %zext to float 744 ret float %to.vgpr 745} 746 747; zext forced to LHS of addressing expression, with immediate offset 748define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 749; GCN-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0: 750; GCN: ; %bb.0: 751; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:128 752; GCN-NEXT: s_waitcnt vmcnt(0) 753; GCN-NEXT: ; return to shader part epilog 754 %zext.offset = zext i32 %voffset to i64 755 %sbase.as.int = ptrtoint i8 addrspace(1)* %sbase to i64 756 %add = add i64 %zext.offset, %sbase.as.int 757 %add.immoffset = add i64 %add, 128 758 %dirty.gep = inttoptr i64 %add.immoffset to i8 addrspace(1)* 759 %load = load i8, i8 addrspace(1)* %dirty.gep 760 %zext = zext i8 %load to i32 761 %to.vgpr = bitcast i32 %zext to float 762 ret float %to.vgpr 763} 764 765; zext forced to LHS of addressing expression, with immediate offset in non-canonical position 766define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 767; GCN-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1: 768; GCN: ; %bb.0: 769; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:128 770; GCN-NEXT: s_waitcnt vmcnt(0) 771; GCN-NEXT: ; return to shader part epilog 772 %zext.offset = zext i32 %voffset to i64 773 %sbase.as.int = ptrtoint i8 addrspace(1)* %sbase to i64 774 %add.immoffset = add i64 %sbase.as.int, 128 775 %add = add i64 %zext.offset, %add.immoffset 776 %dirty.gep = inttoptr i64 %add to i8 addrspace(1)* 777 %load = load i8, i8 addrspace(1)* %dirty.gep 778 %zext = zext i8 %load to i32 779 %to.vgpr = bitcast i32 %zext to float 780 ret float %to.vgpr 781} 782 783; -------------------------------------------------------------------------------- 784; Uniformity edge cases 785; -------------------------------------------------------------------------------- 786 787@ptr.in.lds = internal addrspace(3) global i8 addrspace(1)* undef 788 789; Base pointer is uniform, but also in VGPRs 790define amdgpu_ps float @global_load_saddr_uniform_ptr_in_vgprs(i32 %voffset) { 791; GFX9-LABEL: global_load_saddr_uniform_ptr_in_vgprs: 792; GFX9: ; %bb.0: 793; GFX9-NEXT: v_mov_b32_e32 v1, 0 794; GFX9-NEXT: ds_read_b64 v[1:2], v1 795; GFX9-NEXT: s_waitcnt lgkmcnt(0) 796; GFX9-NEXT: v_readfirstlane_b32 s0, v1 797; GFX9-NEXT: v_readfirstlane_b32 s1, v2 798; GFX9-NEXT: s_nop 4 799; GFX9-NEXT: global_load_ubyte v0, v0, s[0:1] 800; GFX9-NEXT: s_waitcnt vmcnt(0) 801; GFX9-NEXT: ; return to shader part epilog 802; 803; GFX10-LABEL: global_load_saddr_uniform_ptr_in_vgprs: 804; GFX10: ; %bb.0: 805; GFX10-NEXT: v_mov_b32_e32 v1, 0 806; GFX10-NEXT: ds_read_b64 v[1:2], v1 807; GFX10-NEXT: s_waitcnt lgkmcnt(0) 808; GFX10-NEXT: v_readfirstlane_b32 s0, v1 809; GFX10-NEXT: v_readfirstlane_b32 s1, v2 810; GFX10-NEXT: global_load_ubyte v0, v0, s[0:1] 811; GFX10-NEXT: s_waitcnt vmcnt(0) 812; GFX10-NEXT: ; return to shader part epilog 813 %sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds 814 %zext.offset = zext i32 %voffset to i64 815 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 816 %load = load i8, i8 addrspace(1)* %gep0 817 %zext = zext i8 %load to i32 818 %to.vgpr = bitcast i32 %zext to float 819 ret float %to.vgpr 820} 821 822; Base pointer is uniform, but also in VGPRs, with imm offset 823define amdgpu_ps float @global_load_saddr_uniform_ptr_in_vgprs_immoffset(i32 %voffset) { 824; GFX9-LABEL: global_load_saddr_uniform_ptr_in_vgprs_immoffset: 825; GFX9: ; %bb.0: 826; GFX9-NEXT: v_mov_b32_e32 v1, 0 827; GFX9-NEXT: ds_read_b64 v[1:2], v1 828; GFX9-NEXT: s_waitcnt lgkmcnt(0) 829; GFX9-NEXT: v_readfirstlane_b32 s0, v1 830; GFX9-NEXT: v_readfirstlane_b32 s1, v2 831; GFX9-NEXT: s_nop 4 832; GFX9-NEXT: global_load_ubyte v0, v0, s[0:1] offset:42 833; GFX9-NEXT: s_waitcnt vmcnt(0) 834; GFX9-NEXT: ; return to shader part epilog 835; 836; GFX10-LABEL: global_load_saddr_uniform_ptr_in_vgprs_immoffset: 837; GFX10: ; %bb.0: 838; GFX10-NEXT: v_mov_b32_e32 v1, 0 839; GFX10-NEXT: ds_read_b64 v[1:2], v1 840; GFX10-NEXT: s_waitcnt lgkmcnt(0) 841; GFX10-NEXT: v_readfirstlane_b32 s0, v1 842; GFX10-NEXT: v_readfirstlane_b32 s1, v2 843; GFX10-NEXT: global_load_ubyte v0, v0, s[0:1] offset:42 844; GFX10-NEXT: s_waitcnt vmcnt(0) 845; GFX10-NEXT: ; return to shader part epilog 846 %sbase = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(3)* @ptr.in.lds 847 %zext.offset = zext i32 %voffset to i64 848 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 849 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 42 850 %load = load i8, i8 addrspace(1)* %gep1 851 %zext = zext i8 %load to i32 852 %to.vgpr = bitcast i32 %zext to float 853 ret float %to.vgpr 854} 855 856; Both 64-bit base and 32-bit offset are scalar 857define amdgpu_ps float @global_load_saddr_i8_zext_uniform_offset(i8 addrspace(1)* inreg %sbase, i32 inreg %soffset) { 858; GCN-LABEL: global_load_saddr_i8_zext_uniform_offset: 859; GCN: ; %bb.0: 860; GCN-NEXT: v_mov_b32_e32 v0, s4 861; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] 862; GCN-NEXT: s_waitcnt vmcnt(0) 863; GCN-NEXT: ; return to shader part epilog 864 %zext.offset = zext i32 %soffset to i64 865 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 866 %load = load i8, i8 addrspace(1)* %gep0 867 %zext = zext i8 %load to i32 868 %to.vgpr = bitcast i32 %zext to float 869 ret float %to.vgpr 870} 871 872; Both 64-bit base and 32-bit offset are scalar, with immediate offset. 873define amdgpu_ps float @global_load_saddr_i8_zext_uniform_offset_immoffset(i8 addrspace(1)* inreg %sbase, i32 inreg %soffset) { 874; GCN-LABEL: global_load_saddr_i8_zext_uniform_offset_immoffset: 875; GCN: ; %bb.0: 876; GCN-NEXT: v_mov_b32_e32 v0, s4 877; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-24 878; GCN-NEXT: s_waitcnt vmcnt(0) 879; GCN-NEXT: ; return to shader part epilog 880 %zext.offset = zext i32 %soffset to i64 881 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 882 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -24 883 %load = load i8, i8 addrspace(1)* %gep1 884 %zext = zext i8 %load to i32 885 %to.vgpr = bitcast i32 %zext to float 886 ret float %to.vgpr 887} 888 889; Both components uniform, zext forced to LHS of addressing expression 890define amdgpu_ps float @global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add(i8 addrspace(1)* inreg %sbase, i32 inreg %soffset) { 891; GCN-LABEL: global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add: 892; GCN: ; %bb.0: 893; GCN-NEXT: v_mov_b32_e32 v0, s4 894; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] 895; GCN-NEXT: s_waitcnt vmcnt(0) 896; GCN-NEXT: ; return to shader part epilog 897 %zext.offset = zext i32 %soffset to i64 898 %sbase.as.int = ptrtoint i8 addrspace(1)* %sbase to i64 899 %add = add i64 %zext.offset, %sbase.as.int 900 %dirty.gep = inttoptr i64 %add to i8 addrspace(1)* 901 %load = load i8, i8 addrspace(1)* %dirty.gep 902 %zext = zext i8 %load to i32 903 %to.vgpr = bitcast i32 %zext to float 904 ret float %to.vgpr 905} 906 907; Both components uniform, zext forced to LHS of addressing expression, with immediate offset 908define amdgpu_ps float @global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0(i8 addrspace(1)* inreg %sbase, i32 inreg %soffset) { 909; GCN-LABEL: global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0: 910; GCN: ; %bb.0: 911; GCN-NEXT: v_mov_b32_e32 v0, s4 912; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:128 913; GCN-NEXT: s_waitcnt vmcnt(0) 914; GCN-NEXT: ; return to shader part epilog 915 %zext.offset = zext i32 %soffset to i64 916 %sbase.as.int = ptrtoint i8 addrspace(1)* %sbase to i64 917 %add = add i64 %zext.offset, %sbase.as.int 918 %add.immoffset = add i64 %add, 128 919 %dirty.gep = inttoptr i64 %add.immoffset to i8 addrspace(1)* 920 %load = load i8, i8 addrspace(1)* %dirty.gep 921 %zext = zext i8 %load to i32 922 %to.vgpr = bitcast i32 %zext to float 923 ret float %to.vgpr 924} 925 926; divergent 64-bit base, 32-bit scalar offset. 927define amdgpu_ps float @global_load_i8_vgpr64_sgpr32(i8 addrspace(1)* %vbase, i32 inreg %soffset) { 928; GFX9-LABEL: global_load_i8_vgpr64_sgpr32: 929; GFX9: ; %bb.0: 930; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v0 931; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 932; GFX9-NEXT: global_load_ubyte v0, v[0:1], off 933; GFX9-NEXT: s_waitcnt vmcnt(0) 934; GFX9-NEXT: ; return to shader part epilog 935; 936; GFX10-LABEL: global_load_i8_vgpr64_sgpr32: 937; GFX10: ; %bb.0: 938; GFX10-NEXT: v_add_co_u32 v0, vcc, v0, s2 939; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc 940; GFX10-NEXT: global_load_ubyte v0, v[0:1], off 941; GFX10-NEXT: s_waitcnt vmcnt(0) 942; GFX10-NEXT: ; return to shader part epilog 943 %zext.offset = zext i32 %soffset to i64 944 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %vbase, i64 %zext.offset 945 %load = load i8, i8 addrspace(1)* %gep0 946 %zext = zext i8 %load to i32 947 %to.vgpr = bitcast i32 %zext to float 948 ret float %to.vgpr 949} 950 951; divergent 64-bit base, 32-bit scalar offset, with imm offset 952define amdgpu_ps float @global_load_i8_vgpr64_sgpr32_offset_4095(i8 addrspace(1)* %vbase, i32 inreg %soffset) { 953; GFX9-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095: 954; GFX9: ; %bb.0: 955; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v0 956; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 957; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 958; GFX9-NEXT: s_waitcnt vmcnt(0) 959; GFX9-NEXT: ; return to shader part epilog 960; 961; GFX10-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095: 962; GFX10: ; %bb.0: 963; GFX10-NEXT: v_add_co_u32 v0, vcc, v0, s2 964; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc 965; GFX10-NEXT: v_add_co_u32 v0, vcc, 0x800, v0 966; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc 967; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 968; GFX10-NEXT: s_waitcnt vmcnt(0) 969; GFX10-NEXT: ; return to shader part epilog 970 %zext.offset = zext i32 %soffset to i64 971 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %vbase, i64 %zext.offset 972 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 4095 973 %load = load i8, i8 addrspace(1)* %gep1 974 %zext = zext i8 %load to i32 975 %to.vgpr = bitcast i32 %zext to float 976 ret float %to.vgpr 977} 978 979; -------------------------------------------------------------------------------- 980; Natural addressing shifts with restricted range 981; -------------------------------------------------------------------------------- 982 983; Cannot push the shift into 32-bits, and cannot match. 984define amdgpu_ps float @global_load_saddr_f32_natural_addressing(float addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr) { 985; GFX9-LABEL: global_load_saddr_f32_natural_addressing: 986; GFX9: ; %bb.0: 987; GFX9-NEXT: global_load_dword v0, v[0:1], off 988; GFX9-NEXT: v_mov_b32_e32 v1, 0 989; GFX9-NEXT: v_mov_b32_e32 v2, s3 990; GFX9-NEXT: s_waitcnt vmcnt(0) 991; GFX9-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] 992; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v0 993; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc 994; GFX9-NEXT: global_load_dword v0, v[0:1], off 995; GFX9-NEXT: s_waitcnt vmcnt(0) 996; GFX9-NEXT: ; return to shader part epilog 997; 998; GFX10-LABEL: global_load_saddr_f32_natural_addressing: 999; GFX10: ; %bb.0: 1000; GFX10-NEXT: global_load_dword v0, v[0:1], off 1001; GFX10-NEXT: v_mov_b32_e32 v1, 0 1002; GFX10-NEXT: s_waitcnt vmcnt(0) 1003; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] 1004; GFX10-NEXT: v_add_co_u32 v0, vcc, s2, v0 1005; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, s3, v1, vcc 1006; GFX10-NEXT: global_load_dword v0, v[0:1], off 1007; GFX10-NEXT: s_waitcnt vmcnt(0) 1008; GFX10-NEXT: ; return to shader part epilog 1009 %voffset = load i32, i32 addrspace(1)* %voffset.ptr 1010 %zext.offset = zext i32 %voffset to i64 1011 %gep = getelementptr inbounds float, float addrspace(1)* %sbase, i64 %zext.offset 1012 %load = load float, float addrspace(1)* %gep 1013 ret float %load 1014} 1015 1016; Cannot push the shift into 32-bits, with an immediate offset. 1017define amdgpu_ps float @global_load_saddr_f32_natural_addressing_immoffset(i8 addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr) { 1018; GCN-LABEL: global_load_saddr_f32_natural_addressing_immoffset: 1019; GCN: ; %bb.0: 1020; GCN-NEXT: global_load_dword v0, v[0:1], off 1021; GCN-NEXT: s_waitcnt vmcnt(0) 1022; GCN-NEXT: global_load_dword v0, v0, s[2:3] offset:128 1023; GCN-NEXT: s_waitcnt vmcnt(0) 1024; GCN-NEXT: ; return to shader part epilog 1025 %voffset = load i32, i32 addrspace(1)* %voffset.ptr 1026 %zext.offset = zext i32 %voffset to i64 1027 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1028 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 128 1029 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to float addrspace(1)* 1030 %load = load float, float addrspace(1)* %gep1.cast 1031 ret float %load 1032} 1033 1034; Range is sufficiently restricted to push the shift into 32-bits. 1035define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range(float addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr) { 1036; GCN-LABEL: global_load_f32_saddr_zext_vgpr_range: 1037; GCN: ; %bb.0: 1038; GCN-NEXT: global_load_dword v0, v[0:1], off 1039; GCN-NEXT: s_waitcnt vmcnt(0) 1040; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1041; GCN-NEXT: global_load_dword v0, v0, s[2:3] 1042; GCN-NEXT: s_waitcnt vmcnt(0) 1043; GCN-NEXT: ; return to shader part epilog 1044 %voffset = load i32, i32 addrspace(1)* %voffset.ptr, !range !0 1045 %zext.offset = zext i32 %voffset to i64 1046 %gep = getelementptr inbounds float, float addrspace(1)* %sbase, i64 %zext.offset 1047 %load = load float, float addrspace(1)* %gep 1048 ret float %load 1049} 1050 1051; Range is sufficiently restricted to push the shift into 32-bits, with an imm offset 1052define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range_imm_offset(float addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr) { 1053; GCN-LABEL: global_load_f32_saddr_zext_vgpr_range_imm_offset: 1054; GCN: ; %bb.0: 1055; GCN-NEXT: global_load_dword v0, v[0:1], off 1056; GCN-NEXT: s_waitcnt vmcnt(0) 1057; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1058; GCN-NEXT: global_load_dword v0, v0, s[2:3] offset:400 1059; GCN-NEXT: s_waitcnt vmcnt(0) 1060; GCN-NEXT: ; return to shader part epilog 1061 %voffset = load i32, i32 addrspace(1)* %voffset.ptr, !range !0 1062 %zext.offset = zext i32 %voffset to i64 1063 %gep0 = getelementptr inbounds float, float addrspace(1)* %sbase, i64 %zext.offset 1064 %gep1 = getelementptr inbounds float, float addrspace(1)* %gep0, i64 100 1065 %load = load float, float addrspace(1)* %gep1 1066 ret float %load 1067} 1068 1069; Range is 1 beyond the limit where we can move the shift into 32-bits. 1070define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range_too_large(float addrspace(1)* inreg %sbase, i32 addrspace(1)* %voffset.ptr) { 1071; GFX9-LABEL: global_load_f32_saddr_zext_vgpr_range_too_large: 1072; GFX9: ; %bb.0: 1073; GFX9-NEXT: global_load_dword v0, v[0:1], off 1074; GFX9-NEXT: v_mov_b32_e32 v1, 0 1075; GFX9-NEXT: v_mov_b32_e32 v2, s3 1076; GFX9-NEXT: s_waitcnt vmcnt(0) 1077; GFX9-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] 1078; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v0 1079; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc 1080; GFX9-NEXT: global_load_dword v0, v[0:1], off 1081; GFX9-NEXT: s_waitcnt vmcnt(0) 1082; GFX9-NEXT: ; return to shader part epilog 1083; 1084; GFX10-LABEL: global_load_f32_saddr_zext_vgpr_range_too_large: 1085; GFX10: ; %bb.0: 1086; GFX10-NEXT: global_load_dword v0, v[0:1], off 1087; GFX10-NEXT: v_mov_b32_e32 v1, 0 1088; GFX10-NEXT: s_waitcnt vmcnt(0) 1089; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] 1090; GFX10-NEXT: v_add_co_u32 v0, vcc, s2, v0 1091; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc, s3, v1, vcc 1092; GFX10-NEXT: global_load_dword v0, v[0:1], off 1093; GFX10-NEXT: s_waitcnt vmcnt(0) 1094; GFX10-NEXT: ; return to shader part epilog 1095 %voffset = load i32, i32 addrspace(1)* %voffset.ptr, !range !1 1096 %zext.offset = zext i32 %voffset to i64 1097 %gep = getelementptr inbounds float, float addrspace(1)* %sbase, i64 %zext.offset 1098 %load = load float, float addrspace(1)* %gep 1099 ret float %load 1100} 1101 1102; -------------------------------------------------------------------------------- 1103; Stress various type loads 1104; -------------------------------------------------------------------------------- 1105 1106define amdgpu_ps half @global_load_saddr_i16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1107; GCN-LABEL: global_load_saddr_i16: 1108; GCN: ; %bb.0: 1109; GCN-NEXT: global_load_ushort v0, v0, s[2:3] 1110; GCN-NEXT: s_waitcnt vmcnt(0) 1111; GCN-NEXT: ; return to shader part epilog 1112 %zext.offset = zext i32 %voffset to i64 1113 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1114 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 1115 %load = load i16, i16 addrspace(1)* %gep0.cast 1116 %cast.load = bitcast i16 %load to half 1117 ret half %cast.load 1118} 1119 1120define amdgpu_ps half @global_load_saddr_i16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1121; GCN-LABEL: global_load_saddr_i16_immneg128: 1122; GCN: ; %bb.0: 1123; GCN-NEXT: global_load_ushort v0, v0, s[2:3] offset:-128 1124; GCN-NEXT: s_waitcnt vmcnt(0) 1125; GCN-NEXT: ; return to shader part epilog 1126 %zext.offset = zext i32 %voffset to i64 1127 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1128 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1129 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 1130 %load = load i16, i16 addrspace(1)* %gep1.cast 1131 %cast.load = bitcast i16 %load to half 1132 ret half %cast.load 1133} 1134 1135define amdgpu_ps half @global_load_saddr_f16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1136; GCN-LABEL: global_load_saddr_f16: 1137; GCN: ; %bb.0: 1138; GCN-NEXT: global_load_ushort v0, v0, s[2:3] 1139; GCN-NEXT: s_waitcnt vmcnt(0) 1140; GCN-NEXT: ; return to shader part epilog 1141 %zext.offset = zext i32 %voffset to i64 1142 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1143 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to half addrspace(1)* 1144 %load = load half, half addrspace(1)* %gep0.cast 1145 ret half %load 1146} 1147 1148define amdgpu_ps half @global_load_saddr_f16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1149; GCN-LABEL: global_load_saddr_f16_immneg128: 1150; GCN: ; %bb.0: 1151; GCN-NEXT: global_load_ushort v0, v0, s[2:3] offset:-128 1152; GCN-NEXT: s_waitcnt vmcnt(0) 1153; GCN-NEXT: ; return to shader part epilog 1154 %zext.offset = zext i32 %voffset to i64 1155 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1156 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1157 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to half addrspace(1)* 1158 %load = load half, half addrspace(1)* %gep1.cast 1159 ret half %load 1160} 1161 1162define amdgpu_ps float @global_load_saddr_i32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1163; GCN-LABEL: global_load_saddr_i32: 1164; GCN: ; %bb.0: 1165; GCN-NEXT: global_load_dword v0, v0, s[2:3] 1166; GCN-NEXT: s_waitcnt vmcnt(0) 1167; GCN-NEXT: ; return to shader part epilog 1168 %zext.offset = zext i32 %voffset to i64 1169 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1170 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)* 1171 %load = load i32, i32 addrspace(1)* %gep0.cast 1172 %cast.load = bitcast i32 %load to float 1173 ret float %cast.load 1174} 1175 1176define amdgpu_ps float @global_load_saddr_i32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1177; GCN-LABEL: global_load_saddr_i32_immneg128: 1178; GCN: ; %bb.0: 1179; GCN-NEXT: global_load_dword v0, v0, s[2:3] offset:-128 1180; GCN-NEXT: s_waitcnt vmcnt(0) 1181; GCN-NEXT: ; return to shader part epilog 1182 %zext.offset = zext i32 %voffset to i64 1183 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1184 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1185 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)* 1186 %load = load i32, i32 addrspace(1)* %gep1.cast 1187 %cast.load = bitcast i32 %load to float 1188 ret float %cast.load 1189} 1190 1191define amdgpu_ps float @global_load_saddr_f32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1192; GCN-LABEL: global_load_saddr_f32: 1193; GCN: ; %bb.0: 1194; GCN-NEXT: global_load_dword v0, v0, s[2:3] 1195; GCN-NEXT: s_waitcnt vmcnt(0) 1196; GCN-NEXT: ; return to shader part epilog 1197 %zext.offset = zext i32 %voffset to i64 1198 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1199 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to float addrspace(1)* 1200 %load = load float, float addrspace(1)* %gep0.cast 1201 ret float %load 1202} 1203 1204define amdgpu_ps float @global_load_saddr_f32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1205; GCN-LABEL: global_load_saddr_f32_immneg128: 1206; GCN: ; %bb.0: 1207; GCN-NEXT: global_load_dword v0, v0, s[2:3] offset:-128 1208; GCN-NEXT: s_waitcnt vmcnt(0) 1209; GCN-NEXT: ; return to shader part epilog 1210 %zext.offset = zext i32 %voffset to i64 1211 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1212 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1213 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to float addrspace(1)* 1214 %load = load float, float addrspace(1)* %gep1.cast 1215 ret float %load 1216} 1217 1218define amdgpu_ps <2 x half> @global_load_saddr_v2i16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1219; GCN-LABEL: global_load_saddr_v2i16: 1220; GCN: ; %bb.0: 1221; GCN-NEXT: global_load_dword v0, v0, s[2:3] 1222; GCN-NEXT: s_waitcnt vmcnt(0) 1223; GCN-NEXT: ; return to shader part epilog 1224 %zext.offset = zext i32 %voffset to i64 1225 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1226 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i16> addrspace(1)* 1227 %load = load <2 x i16>, <2 x i16> addrspace(1)* %gep0.cast 1228 %cast.load = bitcast <2 x i16> %load to <2 x half> 1229 ret <2 x half> %cast.load 1230} 1231 1232define amdgpu_ps <2 x half> @global_load_saddr_v2i16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1233; GCN-LABEL: global_load_saddr_v2i16_immneg128: 1234; GCN: ; %bb.0: 1235; GCN-NEXT: global_load_dword v0, v0, s[2:3] offset:-128 1236; GCN-NEXT: s_waitcnt vmcnt(0) 1237; GCN-NEXT: ; return to shader part epilog 1238 %zext.offset = zext i32 %voffset to i64 1239 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1240 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1241 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i16> addrspace(1)* 1242 %load = load <2 x i16>, <2 x i16> addrspace(1)* %gep1.cast 1243 %cast.load = bitcast <2 x i16> %load to <2 x half> 1244 ret <2 x half> %cast.load 1245} 1246 1247define amdgpu_ps <2 x half> @global_load_saddr_v2f16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1248; GCN-LABEL: global_load_saddr_v2f16: 1249; GCN: ; %bb.0: 1250; GCN-NEXT: global_load_dword v0, v0, s[2:3] 1251; GCN-NEXT: s_waitcnt vmcnt(0) 1252; GCN-NEXT: ; return to shader part epilog 1253 %zext.offset = zext i32 %voffset to i64 1254 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1255 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x half> addrspace(1)* 1256 %load = load <2 x half>, <2 x half> addrspace(1)* %gep0.cast 1257 ret <2 x half> %load 1258} 1259 1260define amdgpu_ps <2 x half> @global_load_saddr_v2f16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1261; GCN-LABEL: global_load_saddr_v2f16_immneg128: 1262; GCN: ; %bb.0: 1263; GCN-NEXT: global_load_dword v0, v0, s[2:3] offset:-128 1264; GCN-NEXT: s_waitcnt vmcnt(0) 1265; GCN-NEXT: ; return to shader part epilog 1266 %zext.offset = zext i32 %voffset to i64 1267 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1268 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1269 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x half> addrspace(1)* 1270 %load = load <2 x half>, <2 x half> addrspace(1)* %gep1.cast 1271 ret <2 x half> %load 1272} 1273 1274define amdgpu_ps <2 x half> @global_load_saddr_p3(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1275; GCN-LABEL: global_load_saddr_p3: 1276; GCN: ; %bb.0: 1277; GCN-NEXT: global_load_dword v0, v0, s[2:3] 1278; GCN-NEXT: s_waitcnt vmcnt(0) 1279; GCN-NEXT: ; return to shader part epilog 1280 %zext.offset = zext i32 %voffset to i64 1281 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1282 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(3)* addrspace(1)* 1283 %load = load i8 addrspace(3)*, i8 addrspace(3)* addrspace(1)* %gep0.cast 1284 %cast.load0 = ptrtoint i8 addrspace(3)* %load to i32 1285 %cast.load1 = bitcast i32 %cast.load0 to <2 x half> 1286 ret <2 x half> %cast.load1 1287} 1288 1289define amdgpu_ps <2 x half> @global_load_saddr_p3_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1290; GCN-LABEL: global_load_saddr_p3_immneg128: 1291; GCN: ; %bb.0: 1292; GCN-NEXT: global_load_dword v0, v0, s[2:3] offset:-128 1293; GCN-NEXT: s_waitcnt vmcnt(0) 1294; GCN-NEXT: ; return to shader part epilog 1295 %zext.offset = zext i32 %voffset to i64 1296 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1297 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1298 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(3)* addrspace(1)* 1299 %load = load i8 addrspace(3)*, i8 addrspace(3)* addrspace(1)* %gep1.cast 1300 %cast.load0 = ptrtoint i8 addrspace(3)* %load to i32 1301 %cast.load1 = bitcast i32 %cast.load0 to <2 x half> 1302 ret <2 x half> %cast.load1 1303} 1304 1305define amdgpu_ps <2 x float> @global_load_saddr_f64(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1306; GCN-LABEL: global_load_saddr_f64: 1307; GCN: ; %bb.0: 1308; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] 1309; GCN-NEXT: s_waitcnt vmcnt(0) 1310; GCN-NEXT: ; return to shader part epilog 1311 %zext.offset = zext i32 %voffset to i64 1312 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1313 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to double addrspace(1)* 1314 %load = load double, double addrspace(1)* %gep0.cast 1315 %cast.load = bitcast double %load to <2 x float> 1316 ret <2 x float> %cast.load 1317} 1318 1319define amdgpu_ps <2 x float> @global_load_saddr_f64_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1320; GCN-LABEL: global_load_saddr_f64_immneg128: 1321; GCN: ; %bb.0: 1322; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 1323; GCN-NEXT: s_waitcnt vmcnt(0) 1324; GCN-NEXT: ; return to shader part epilog 1325 %zext.offset = zext i32 %voffset to i64 1326 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1327 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1328 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to double addrspace(1)* 1329 %load = load double, double addrspace(1)* %gep1.cast 1330 %cast.load = bitcast double %load to <2 x float> 1331 ret <2 x float> %cast.load 1332} 1333 1334define amdgpu_ps <2 x float> @global_load_saddr_i64(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1335; GCN-LABEL: global_load_saddr_i64: 1336; GCN: ; %bb.0: 1337; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] 1338; GCN-NEXT: s_waitcnt vmcnt(0) 1339; GCN-NEXT: ; return to shader part epilog 1340 %zext.offset = zext i32 %voffset to i64 1341 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1342 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)* 1343 %load = load i64, i64 addrspace(1)* %gep0.cast 1344 %cast.load = bitcast i64 %load to <2 x float> 1345 ret <2 x float> %cast.load 1346} 1347 1348define amdgpu_ps <2 x float> @global_load_saddr_i64_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1349; GCN-LABEL: global_load_saddr_i64_immneg128: 1350; GCN: ; %bb.0: 1351; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 1352; GCN-NEXT: s_waitcnt vmcnt(0) 1353; GCN-NEXT: ; return to shader part epilog 1354 %zext.offset = zext i32 %voffset to i64 1355 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1356 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1357 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)* 1358 %load = load i64, i64 addrspace(1)* %gep1.cast 1359 %cast.load = bitcast i64 %load to <2 x float> 1360 ret <2 x float> %cast.load 1361} 1362 1363define amdgpu_ps <2 x float> @global_load_saddr_v2f32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1364; GCN-LABEL: global_load_saddr_v2f32: 1365; GCN: ; %bb.0: 1366; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] 1367; GCN-NEXT: s_waitcnt vmcnt(0) 1368; GCN-NEXT: ; return to shader part epilog 1369 %zext.offset = zext i32 %voffset to i64 1370 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1371 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x float> addrspace(1)* 1372 %load = load <2 x float>, <2 x float> addrspace(1)* %gep0.cast 1373 ret <2 x float> %load 1374} 1375 1376define amdgpu_ps <2 x float> @global_load_saddr_v2f32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1377; GCN-LABEL: global_load_saddr_v2f32_immneg128: 1378; GCN: ; %bb.0: 1379; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 1380; GCN-NEXT: s_waitcnt vmcnt(0) 1381; GCN-NEXT: ; return to shader part epilog 1382 %zext.offset = zext i32 %voffset to i64 1383 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1384 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1385 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x float> addrspace(1)* 1386 %load = load <2 x float>, <2 x float> addrspace(1)* %gep1.cast 1387 ret <2 x float> %load 1388} 1389 1390define amdgpu_ps <2 x float> @global_load_saddr_v2i32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1391; GCN-LABEL: global_load_saddr_v2i32: 1392; GCN: ; %bb.0: 1393; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] 1394; GCN-NEXT: s_waitcnt vmcnt(0) 1395; GCN-NEXT: ; return to shader part epilog 1396 %zext.offset = zext i32 %voffset to i64 1397 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1398 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i32> addrspace(1)* 1399 %load = load <2 x i32>, <2 x i32> addrspace(1)* %gep0.cast 1400 %cast.load = bitcast <2 x i32> %load to <2 x float> 1401 ret <2 x float> %cast.load 1402} 1403 1404define amdgpu_ps <2 x float> @global_load_saddr_v2i32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1405; GCN-LABEL: global_load_saddr_v2i32_immneg128: 1406; GCN: ; %bb.0: 1407; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 1408; GCN-NEXT: s_waitcnt vmcnt(0) 1409; GCN-NEXT: ; return to shader part epilog 1410 %zext.offset = zext i32 %voffset to i64 1411 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1412 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1413 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i32> addrspace(1)* 1414 %load = load <2 x i32>, <2 x i32> addrspace(1)* %gep1.cast 1415 %cast.load = bitcast <2 x i32> %load to <2 x float> 1416 ret <2 x float> %cast.load 1417} 1418 1419define amdgpu_ps <2 x float> @global_load_saddr_v4i16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1420; GCN-LABEL: global_load_saddr_v4i16: 1421; GCN: ; %bb.0: 1422; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] 1423; GCN-NEXT: s_waitcnt vmcnt(0) 1424; GCN-NEXT: ; return to shader part epilog 1425 %zext.offset = zext i32 %voffset to i64 1426 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1427 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i16> addrspace(1)* 1428 %load = load <4 x i16>, <4 x i16> addrspace(1)* %gep0.cast 1429 %cast.load = bitcast <4 x i16> %load to <2 x float> 1430 ret <2 x float> %cast.load 1431} 1432 1433define amdgpu_ps <2 x float> @global_load_saddr_v4i16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1434; GCN-LABEL: global_load_saddr_v4i16_immneg128: 1435; GCN: ; %bb.0: 1436; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 1437; GCN-NEXT: s_waitcnt vmcnt(0) 1438; GCN-NEXT: ; return to shader part epilog 1439 %zext.offset = zext i32 %voffset to i64 1440 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1441 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1442 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i16> addrspace(1)* 1443 %load = load <4 x i16>, <4 x i16> addrspace(1)* %gep1.cast 1444 %cast.load = bitcast <4 x i16> %load to <2 x float> 1445 ret <2 x float> %cast.load 1446} 1447 1448define amdgpu_ps <2 x float> @global_load_saddr_v4f16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1449; GCN-LABEL: global_load_saddr_v4f16: 1450; GCN: ; %bb.0: 1451; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] 1452; GCN-NEXT: s_waitcnt vmcnt(0) 1453; GCN-NEXT: ; return to shader part epilog 1454 %zext.offset = zext i32 %voffset to i64 1455 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1456 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x half> addrspace(1)* 1457 %load = load <4 x half>, <4 x half> addrspace(1)* %gep0.cast 1458 %cast.load = bitcast <4 x half> %load to <2 x float> 1459 ret <2 x float> %cast.load 1460} 1461 1462define amdgpu_ps <2 x float> @global_load_saddr_v4f16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1463; GCN-LABEL: global_load_saddr_v4f16_immneg128: 1464; GCN: ; %bb.0: 1465; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 1466; GCN-NEXT: s_waitcnt vmcnt(0) 1467; GCN-NEXT: ; return to shader part epilog 1468 %zext.offset = zext i32 %voffset to i64 1469 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1470 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1471 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x half> addrspace(1)* 1472 %load = load <4 x half>, <4 x half> addrspace(1)* %gep1.cast 1473 %cast.load = bitcast <4 x half> %load to <2 x float> 1474 ret <2 x float> %cast.load 1475} 1476 1477define amdgpu_ps <2 x float> @global_load_saddr_p1(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1478; GCN-LABEL: global_load_saddr_p1: 1479; GCN: ; %bb.0: 1480; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] 1481; GCN-NEXT: s_waitcnt vmcnt(0) 1482; GCN-NEXT: ; return to shader part epilog 1483 %zext.offset = zext i32 %voffset to i64 1484 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1485 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(1)* addrspace(1)* 1486 %load = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %gep0.cast 1487 %cast.load0 = ptrtoint i8 addrspace(1)* %load to i64 1488 %cast.load1 = bitcast i64 %cast.load0 to <2 x float> 1489 ret <2 x float> %cast.load1 1490} 1491 1492define amdgpu_ps <2 x float> @global_load_saddr_p1_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1493; GCN-LABEL: global_load_saddr_p1_immneg128: 1494; GCN: ; %bb.0: 1495; GCN-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 1496; GCN-NEXT: s_waitcnt vmcnt(0) 1497; GCN-NEXT: ; return to shader part epilog 1498 %zext.offset = zext i32 %voffset to i64 1499 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1500 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1501 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(1)* addrspace(1)* 1502 %load = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %gep1.cast 1503 %cast.load0 = ptrtoint i8 addrspace(1)* %load to i64 1504 %cast.load1 = bitcast i64 %cast.load0 to <2 x float> 1505 ret <2 x float> %cast.load1 1506} 1507 1508define amdgpu_ps <3 x float> @global_load_saddr_v3f32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1509; GCN-LABEL: global_load_saddr_v3f32: 1510; GCN: ; %bb.0: 1511; GCN-NEXT: global_load_dwordx3 v[0:2], v0, s[2:3] 1512; GCN-NEXT: s_waitcnt vmcnt(0) 1513; GCN-NEXT: ; return to shader part epilog 1514 %zext.offset = zext i32 %voffset to i64 1515 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1516 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <3 x float> addrspace(1)* 1517 %load = load <3 x float>, <3 x float> addrspace(1)* %gep0.cast 1518 ret <3 x float> %load 1519} 1520 1521define amdgpu_ps <3 x float> @global_load_saddr_v3f32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1522; GCN-LABEL: global_load_saddr_v3f32_immneg128: 1523; GCN: ; %bb.0: 1524; GCN-NEXT: global_load_dwordx3 v[0:2], v0, s[2:3] offset:-128 1525; GCN-NEXT: s_waitcnt vmcnt(0) 1526; GCN-NEXT: ; return to shader part epilog 1527 %zext.offset = zext i32 %voffset to i64 1528 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1529 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1530 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <3 x float> addrspace(1)* 1531 %load = load <3 x float>, <3 x float> addrspace(1)* %gep1.cast 1532 ret <3 x float> %load 1533} 1534 1535define amdgpu_ps <3 x float> @global_load_saddr_v3i32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1536; GCN-LABEL: global_load_saddr_v3i32: 1537; GCN: ; %bb.0: 1538; GCN-NEXT: global_load_dwordx3 v[0:2], v0, s[2:3] 1539; GCN-NEXT: s_waitcnt vmcnt(0) 1540; GCN-NEXT: ; return to shader part epilog 1541 %zext.offset = zext i32 %voffset to i64 1542 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1543 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <3 x i32> addrspace(1)* 1544 %load = load <3 x i32>, <3 x i32> addrspace(1)* %gep0.cast 1545 %cast.load = bitcast <3 x i32> %load to <3 x float> 1546 ret <3 x float> %cast.load 1547} 1548 1549define amdgpu_ps <3 x float> @global_load_saddr_v3i32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1550; GCN-LABEL: global_load_saddr_v3i32_immneg128: 1551; GCN: ; %bb.0: 1552; GCN-NEXT: global_load_dwordx3 v[0:2], v0, s[2:3] offset:-128 1553; GCN-NEXT: s_waitcnt vmcnt(0) 1554; GCN-NEXT: ; return to shader part epilog 1555 %zext.offset = zext i32 %voffset to i64 1556 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1557 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1558 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <3 x i32> addrspace(1)* 1559 %load = load <3 x i32>, <3 x i32> addrspace(1)* %gep1.cast 1560 %cast.load = bitcast <3 x i32> %load to <3 x float> 1561 ret <3 x float> %cast.load 1562} 1563 1564define amdgpu_ps <6 x half> @global_load_saddr_v6f16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1565; GCN-LABEL: global_load_saddr_v6f16: 1566; GCN: ; %bb.0: 1567; GCN-NEXT: global_load_dwordx3 v[0:2], v0, s[2:3] 1568; GCN-NEXT: s_waitcnt vmcnt(0) 1569; GCN-NEXT: ; return to shader part epilog 1570 %zext.offset = zext i32 %voffset to i64 1571 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1572 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <6 x half> addrspace(1)* 1573 %load = load <6 x half>, <6 x half> addrspace(1)* %gep0.cast 1574 ret <6 x half> %load 1575} 1576 1577define amdgpu_ps <6 x half> @global_load_saddr_v6f16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1578; GCN-LABEL: global_load_saddr_v6f16_immneg128: 1579; GCN: ; %bb.0: 1580; GCN-NEXT: global_load_dwordx3 v[0:2], v0, s[2:3] offset:-128 1581; GCN-NEXT: s_waitcnt vmcnt(0) 1582; GCN-NEXT: ; return to shader part epilog 1583 %zext.offset = zext i32 %voffset to i64 1584 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1585 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1586 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <6 x half> addrspace(1)* 1587 %load = load <6 x half>, <6 x half> addrspace(1)* %gep1.cast 1588 ret <6 x half> %load 1589} 1590 1591define amdgpu_ps <4 x float> @global_load_saddr_v4f32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1592; GCN-LABEL: global_load_saddr_v4f32: 1593; GCN: ; %bb.0: 1594; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] 1595; GCN-NEXT: s_waitcnt vmcnt(0) 1596; GCN-NEXT: ; return to shader part epilog 1597 %zext.offset = zext i32 %voffset to i64 1598 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1599 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x float> addrspace(1)* 1600 %load = load <4 x float>, <4 x float> addrspace(1)* %gep0.cast 1601 ret <4 x float> %load 1602} 1603 1604define amdgpu_ps <4 x float> @global_load_saddr_v4f32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1605; GCN-LABEL: global_load_saddr_v4f32_immneg128: 1606; GCN: ; %bb.0: 1607; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] offset:-128 1608; GCN-NEXT: s_waitcnt vmcnt(0) 1609; GCN-NEXT: ; return to shader part epilog 1610 %zext.offset = zext i32 %voffset to i64 1611 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1612 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1613 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x float> addrspace(1)* 1614 %load = load <4 x float>, <4 x float> addrspace(1)* %gep1.cast 1615 ret <4 x float> %load 1616} 1617 1618define amdgpu_ps <4 x float> @global_load_saddr_v4i32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1619; GCN-LABEL: global_load_saddr_v4i32: 1620; GCN: ; %bb.0: 1621; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] 1622; GCN-NEXT: s_waitcnt vmcnt(0) 1623; GCN-NEXT: ; return to shader part epilog 1624 %zext.offset = zext i32 %voffset to i64 1625 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1626 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i32> addrspace(1)* 1627 %load = load <4 x i32>, <4 x i32> addrspace(1)* %gep0.cast 1628 %cast.load = bitcast <4 x i32> %load to <4 x float> 1629 ret <4 x float> %cast.load 1630} 1631 1632define amdgpu_ps <4 x float> @global_load_saddr_v4i32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1633; GCN-LABEL: global_load_saddr_v4i32_immneg128: 1634; GCN: ; %bb.0: 1635; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] offset:-128 1636; GCN-NEXT: s_waitcnt vmcnt(0) 1637; GCN-NEXT: ; return to shader part epilog 1638 %zext.offset = zext i32 %voffset to i64 1639 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1640 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1641 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i32> addrspace(1)* 1642 %load = load <4 x i32>, <4 x i32> addrspace(1)* %gep1.cast 1643 %cast.load = bitcast <4 x i32> %load to <4 x float> 1644 ret <4 x float> %cast.load 1645} 1646 1647define amdgpu_ps <4 x float> @global_load_saddr_v2i64(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1648; GCN-LABEL: global_load_saddr_v2i64: 1649; GCN: ; %bb.0: 1650; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] 1651; GCN-NEXT: s_waitcnt vmcnt(0) 1652; GCN-NEXT: ; return to shader part epilog 1653 %zext.offset = zext i32 %voffset to i64 1654 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1655 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i64> addrspace(1)* 1656 %load = load <2 x i64>, <2 x i64> addrspace(1)* %gep0.cast 1657 %cast.load = bitcast <2 x i64> %load to <4 x float> 1658 ret <4 x float> %cast.load 1659} 1660 1661define amdgpu_ps <4 x float> @global_load_saddr_v2i64_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1662; GCN-LABEL: global_load_saddr_v2i64_immneg128: 1663; GCN: ; %bb.0: 1664; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] offset:-128 1665; GCN-NEXT: s_waitcnt vmcnt(0) 1666; GCN-NEXT: ; return to shader part epilog 1667 %zext.offset = zext i32 %voffset to i64 1668 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1669 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1670 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i64> addrspace(1)* 1671 %load = load <2 x i64>, <2 x i64> addrspace(1)* %gep1.cast 1672 %cast.load = bitcast <2 x i64> %load to <4 x float> 1673 ret <4 x float> %cast.load 1674} 1675 1676define amdgpu_ps <4 x float> @global_load_saddr_i128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1677; GCN-LABEL: global_load_saddr_i128: 1678; GCN: ; %bb.0: 1679; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] 1680; GCN-NEXT: s_waitcnt vmcnt(0) 1681; GCN-NEXT: ; return to shader part epilog 1682 %zext.offset = zext i32 %voffset to i64 1683 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1684 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i128 addrspace(1)* 1685 %load = load i128, i128 addrspace(1)* %gep0.cast 1686 %cast.load = bitcast i128 %load to <4 x float> 1687 ret <4 x float> %cast.load 1688} 1689 1690define amdgpu_ps <4 x float> @global_load_saddr_i128_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1691; GCN-LABEL: global_load_saddr_i128_immneg128: 1692; GCN: ; %bb.0: 1693; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] offset:-128 1694; GCN-NEXT: s_waitcnt vmcnt(0) 1695; GCN-NEXT: ; return to shader part epilog 1696 %zext.offset = zext i32 %voffset to i64 1697 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1698 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1699 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i128 addrspace(1)* 1700 %load = load i128, i128 addrspace(1)* %gep1.cast 1701 %cast.load = bitcast i128 %load to <4 x float> 1702 ret <4 x float> %cast.load 1703} 1704 1705define amdgpu_ps <4 x float> @global_load_saddr_v2p1(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1706; GCN-LABEL: global_load_saddr_v2p1: 1707; GCN: ; %bb.0: 1708; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] 1709; GCN-NEXT: s_waitcnt vmcnt(0) 1710; GCN-NEXT: ; return to shader part epilog 1711 %zext.offset = zext i32 %voffset to i64 1712 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1713 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <2 x i8 addrspace(1)*> addrspace(1)* 1714 %load = load <2 x i8 addrspace(1)*>, <2 x i8 addrspace(1)*> addrspace(1)* %gep0.cast 1715 %cast.load0 = ptrtoint <2 x i8 addrspace(1)*> %load to <2 x i64> 1716 %cast.load1 = bitcast <2 x i64> %cast.load0 to <4 x float> 1717 ret <4 x float> %cast.load1 1718} 1719 1720define amdgpu_ps <4 x float> @global_load_saddr_v2p1_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1721; GCN-LABEL: global_load_saddr_v2p1_immneg128: 1722; GCN: ; %bb.0: 1723; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] offset:-128 1724; GCN-NEXT: s_waitcnt vmcnt(0) 1725; GCN-NEXT: ; return to shader part epilog 1726 %zext.offset = zext i32 %voffset to i64 1727 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1728 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1729 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <2 x i8 addrspace(1)*> addrspace(1)* 1730 %load = load <2 x i8 addrspace(1)*>, <2 x i8 addrspace(1)*> addrspace(1)* %gep1.cast 1731 %cast.load0 = ptrtoint <2 x i8 addrspace(1)*> %load to <2 x i64> 1732 %cast.load1 = bitcast <2 x i64> %cast.load0 to <4 x float> 1733 ret <4 x float> %cast.load1 1734} 1735 1736define amdgpu_ps <4 x float> @global_load_saddr_v4p3(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1737; GCN-LABEL: global_load_saddr_v4p3: 1738; GCN: ; %bb.0: 1739; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] 1740; GCN-NEXT: s_waitcnt vmcnt(0) 1741; GCN-NEXT: ; return to shader part epilog 1742 %zext.offset = zext i32 %voffset to i64 1743 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1744 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to <4 x i8 addrspace(3)*> addrspace(1)* 1745 %load = load <4 x i8 addrspace(3)*>, <4 x i8 addrspace(3)*> addrspace(1)* %gep0.cast 1746 %cast.load0 = ptrtoint <4 x i8 addrspace(3)*> %load to <4 x i32> 1747 %cast.load1 = bitcast <4 x i32> %cast.load0 to <4 x float> 1748 ret <4 x float> %cast.load1 1749} 1750 1751define amdgpu_ps <4 x float> @global_load_saddr_v4p3_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1752; GCN-LABEL: global_load_saddr_v4p3_immneg128: 1753; GCN: ; %bb.0: 1754; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] offset:-128 1755; GCN-NEXT: s_waitcnt vmcnt(0) 1756; GCN-NEXT: ; return to shader part epilog 1757 %zext.offset = zext i32 %voffset to i64 1758 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1759 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1760 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to <4 x i8 addrspace(3)*> addrspace(1)* 1761 %load = load <4 x i8 addrspace(3)*>, <4 x i8 addrspace(3)*> addrspace(1)* %gep1.cast 1762 %cast.load0 = ptrtoint <4 x i8 addrspace(3)*> %load to <4 x i32> 1763 %cast.load1 = bitcast <4 x i32> %cast.load0 to <4 x float> 1764 ret <4 x float> %cast.load1 1765} 1766 1767; -------------------------------------------------------------------------------- 1768; Extending loads 1769; -------------------------------------------------------------------------------- 1770 1771define amdgpu_ps float @global_sextload_saddr_i8(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1772; GCN-LABEL: global_sextload_saddr_i8: 1773; GCN: ; %bb.0: 1774; GCN-NEXT: global_load_sbyte v0, v0, s[2:3] 1775; GCN-NEXT: s_waitcnt vmcnt(0) 1776; GCN-NEXT: ; return to shader part epilog 1777 %zext.offset = zext i32 %voffset to i64 1778 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1779 %load = load i8, i8 addrspace(1)* %gep0 1780 %sextload = sext i8 %load to i32 1781 %cast.load = bitcast i32 %sextload to float 1782 ret float %cast.load 1783} 1784 1785define amdgpu_ps float @global_sextload_saddr_i8_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1786; GCN-LABEL: global_sextload_saddr_i8_immneg128: 1787; GCN: ; %bb.0: 1788; GCN-NEXT: global_load_sbyte v0, v0, s[2:3] offset:-128 1789; GCN-NEXT: s_waitcnt vmcnt(0) 1790; GCN-NEXT: ; return to shader part epilog 1791 %zext.offset = zext i32 %voffset to i64 1792 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1793 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1794 %load = load i8, i8 addrspace(1)* %gep1 1795 %sextload = sext i8 %load to i32 1796 %cast.load = bitcast i32 %sextload to float 1797 ret float %cast.load 1798} 1799 1800define amdgpu_ps float @global_sextload_saddr_i16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1801; GCN-LABEL: global_sextload_saddr_i16: 1802; GCN: ; %bb.0: 1803; GCN-NEXT: global_load_sshort v0, v0, s[2:3] 1804; GCN-NEXT: s_waitcnt vmcnt(0) 1805; GCN-NEXT: ; return to shader part epilog 1806 %zext.offset = zext i32 %voffset to i64 1807 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1808 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 1809 %load = load i16, i16 addrspace(1)* %gep0.cast 1810 %sextload = sext i16 %load to i32 1811 %cast.load = bitcast i32 %sextload to float 1812 ret float %cast.load 1813} 1814 1815define amdgpu_ps float @global_sextload_saddr_i16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1816; GCN-LABEL: global_sextload_saddr_i16_immneg128: 1817; GCN: ; %bb.0: 1818; GCN-NEXT: global_load_sshort v0, v0, s[2:3] offset:-128 1819; GCN-NEXT: s_waitcnt vmcnt(0) 1820; GCN-NEXT: ; return to shader part epilog 1821 %zext.offset = zext i32 %voffset to i64 1822 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1823 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1824 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 1825 %load = load i16, i16 addrspace(1)* %gep1.cast 1826 %sextload = sext i16 %load to i32 1827 %cast.load = bitcast i32 %sextload to float 1828 ret float %cast.load 1829} 1830 1831define amdgpu_ps float @global_zextload_saddr_i8(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1832; GCN-LABEL: global_zextload_saddr_i8: 1833; GCN: ; %bb.0: 1834; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] 1835; GCN-NEXT: s_waitcnt vmcnt(0) 1836; GCN-NEXT: ; return to shader part epilog 1837 %zext.offset = zext i32 %voffset to i64 1838 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1839 %load = load i8, i8 addrspace(1)* %gep0 1840 %zextload = zext i8 %load to i32 1841 %cast.load = bitcast i32 %zextload to float 1842 ret float %cast.load 1843} 1844 1845define amdgpu_ps float @global_zextload_saddr_i8_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1846; GCN-LABEL: global_zextload_saddr_i8_immneg128: 1847; GCN: ; %bb.0: 1848; GCN-NEXT: global_load_ubyte v0, v0, s[2:3] offset:-128 1849; GCN-NEXT: s_waitcnt vmcnt(0) 1850; GCN-NEXT: ; return to shader part epilog 1851 %zext.offset = zext i32 %voffset to i64 1852 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1853 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1854 %load = load i8, i8 addrspace(1)* %gep1 1855 %zextload = zext i8 %load to i32 1856 %cast.load = bitcast i32 %zextload to float 1857 ret float %cast.load 1858} 1859 1860define amdgpu_ps float @global_zextload_saddr_i16(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1861; GCN-LABEL: global_zextload_saddr_i16: 1862; GCN: ; %bb.0: 1863; GCN-NEXT: global_load_ushort v0, v0, s[2:3] 1864; GCN-NEXT: s_waitcnt vmcnt(0) 1865; GCN-NEXT: ; return to shader part epilog 1866 %zext.offset = zext i32 %voffset to i64 1867 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1868 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 1869 %load = load i16, i16 addrspace(1)* %gep0.cast 1870 %zextload = zext i16 %load to i32 1871 %cast.load = bitcast i32 %zextload to float 1872 ret float %cast.load 1873} 1874 1875define amdgpu_ps float @global_zextload_saddr_i16_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1876; GCN-LABEL: global_zextload_saddr_i16_immneg128: 1877; GCN: ; %bb.0: 1878; GCN-NEXT: global_load_ushort v0, v0, s[2:3] offset:-128 1879; GCN-NEXT: s_waitcnt vmcnt(0) 1880; GCN-NEXT: ; return to shader part epilog 1881 %zext.offset = zext i32 %voffset to i64 1882 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1883 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1884 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 1885 %load = load i16, i16 addrspace(1)* %gep1.cast 1886 %zextload = zext i16 %load to i32 1887 %cast.load = bitcast i32 %zextload to float 1888 ret float %cast.load 1889} 1890 1891; -------------------------------------------------------------------------------- 1892; Atomic load 1893; -------------------------------------------------------------------------------- 1894 1895define amdgpu_ps float @atomic_global_load_saddr_i32(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1896; GFX9-LABEL: atomic_global_load_saddr_i32: 1897; GFX9: ; %bb.0: 1898; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1899; GFX9-NEXT: global_load_dword v0, v0, s[2:3] glc 1900; GFX9-NEXT: s_waitcnt vmcnt(0) 1901; GFX9-NEXT: buffer_wbinvl1 1902; GFX9-NEXT: ; return to shader part epilog 1903; 1904; GFX10-LABEL: atomic_global_load_saddr_i32: 1905; GFX10: ; %bb.0: 1906; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1907; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1908; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc 1909; GFX10-NEXT: s_waitcnt vmcnt(0) 1910; GFX10-NEXT: buffer_gl0_inv 1911; GFX10-NEXT: buffer_gl1_inv 1912; GFX10-NEXT: ; return to shader part epilog 1913 %zext.offset = zext i32 %voffset to i64 1914 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1915 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)* 1916 %load = load atomic i32, i32 addrspace(1)* %gep0.cast seq_cst, align 4 1917 %cast.load = bitcast i32 %load to float 1918 ret float %cast.load 1919} 1920 1921define amdgpu_ps float @atomic_global_load_saddr_i32_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1922; GFX9-LABEL: atomic_global_load_saddr_i32_immneg128: 1923; GFX9: ; %bb.0: 1924; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1925; GFX9-NEXT: global_load_dword v0, v0, s[2:3] offset:-128 glc 1926; GFX9-NEXT: s_waitcnt vmcnt(0) 1927; GFX9-NEXT: buffer_wbinvl1 1928; GFX9-NEXT: ; return to shader part epilog 1929; 1930; GFX10-LABEL: atomic_global_load_saddr_i32_immneg128: 1931; GFX10: ; %bb.0: 1932; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1933; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1934; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:-128 glc dlc 1935; GFX10-NEXT: s_waitcnt vmcnt(0) 1936; GFX10-NEXT: buffer_gl0_inv 1937; GFX10-NEXT: buffer_gl1_inv 1938; GFX10-NEXT: ; return to shader part epilog 1939 %zext.offset = zext i32 %voffset to i64 1940 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1941 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1942 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)* 1943 %load = load atomic i32, i32 addrspace(1)* %gep1.cast seq_cst, align 4 1944 %cast.load = bitcast i32 %load to float 1945 ret float %cast.load 1946} 1947 1948define amdgpu_ps <2 x float> @atomic_global_load_saddr_i64(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1949; GFX9-LABEL: atomic_global_load_saddr_i64: 1950; GFX9: ; %bb.0: 1951; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1952; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] glc 1953; GFX9-NEXT: s_waitcnt vmcnt(0) 1954; GFX9-NEXT: buffer_wbinvl1 1955; GFX9-NEXT: ; return to shader part epilog 1956; 1957; GFX10-LABEL: atomic_global_load_saddr_i64: 1958; GFX10: ; %bb.0: 1959; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1960; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1961; GFX10-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] glc dlc 1962; GFX10-NEXT: s_waitcnt vmcnt(0) 1963; GFX10-NEXT: buffer_gl0_inv 1964; GFX10-NEXT: buffer_gl1_inv 1965; GFX10-NEXT: ; return to shader part epilog 1966 %zext.offset = zext i32 %voffset to i64 1967 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1968 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i64 addrspace(1)* 1969 %load = load atomic i64, i64 addrspace(1)* %gep0.cast seq_cst, align 8 1970 %cast.load = bitcast i64 %load to <2 x float> 1971 ret <2 x float> %cast.load 1972} 1973 1974define amdgpu_ps <2 x float> @atomic_global_load_saddr_i64_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 1975; GFX9-LABEL: atomic_global_load_saddr_i64_immneg128: 1976; GFX9: ; %bb.0: 1977; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1978; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 glc 1979; GFX9-NEXT: s_waitcnt vmcnt(0) 1980; GFX9-NEXT: buffer_wbinvl1 1981; GFX9-NEXT: ; return to shader part epilog 1982; 1983; GFX10-LABEL: atomic_global_load_saddr_i64_immneg128: 1984; GFX10: ; %bb.0: 1985; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1986; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1987; GFX10-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] offset:-128 glc dlc 1988; GFX10-NEXT: s_waitcnt vmcnt(0) 1989; GFX10-NEXT: buffer_gl0_inv 1990; GFX10-NEXT: buffer_gl1_inv 1991; GFX10-NEXT: ; return to shader part epilog 1992 %zext.offset = zext i32 %voffset to i64 1993 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 1994 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 1995 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i64 addrspace(1)* 1996 %load = load atomic i64, i64 addrspace(1)* %gep1.cast seq_cst, align 8 1997 %cast.load = bitcast i64 %load to <2 x float> 1998 ret <2 x float> %cast.load 1999} 2000 2001; -------------------------------------------------------------------------------- 2002; D16 load (low 16) 2003; -------------------------------------------------------------------------------- 2004 2005define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 2006; GCN-LABEL: global_load_saddr_i16_d16lo_undef_hi: 2007; GCN: ; %bb.0: 2008; GCN-NEXT: global_load_short_d16 v0, v0, s[2:3] 2009; GCN-NEXT: s_waitcnt vmcnt(0) 2010; GCN-NEXT: ; return to shader part epilog 2011 %zext.offset = zext i32 %voffset to i64 2012 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2013 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 2014 %load = load i16, i16 addrspace(1)* %gep0.cast 2015 %build = insertelement <2 x i16> undef, i16 %load, i32 0 2016 %cast = bitcast <2 x i16> %build to <2 x half> 2017 ret <2 x half> %cast 2018} 2019 2020define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 2021; GCN-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128: 2022; GCN: ; %bb.0: 2023; GCN-NEXT: global_load_short_d16 v0, v0, s[2:3] offset:-128 2024; GCN-NEXT: s_waitcnt vmcnt(0) 2025; GCN-NEXT: ; return to shader part epilog 2026 %zext.offset = zext i32 %voffset to i64 2027 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2028 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2029 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 2030 %load = load i16, i16 addrspace(1)* %gep1.cast 2031 %build = insertelement <2 x i16> undef, i16 %load, i32 0 2032 %cast = bitcast <2 x i16> %build to <2 x half> 2033 ret <2 x half> %cast 2034} 2035 2036define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zero_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 2037; GCN-LABEL: global_load_saddr_i16_d16lo_zero_hi: 2038; GCN: ; %bb.0: 2039; GCN-NEXT: v_mov_b32_e32 v1, 0 2040; GCN-NEXT: global_load_short_d16 v1, v0, s[2:3] 2041; GCN-NEXT: s_waitcnt vmcnt(0) 2042; GCN-NEXT: v_mov_b32_e32 v0, v1 2043; GCN-NEXT: ; return to shader part epilog 2044 %zext.offset = zext i32 %voffset to i64 2045 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2046 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 2047 %load = load i16, i16 addrspace(1)* %gep0.cast 2048 %build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 0 2049 %cast = bitcast <2 x i16> %build to <2 x half> 2050 ret <2 x half> %cast 2051} 2052 2053define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zero_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 2054; GCN-LABEL: global_load_saddr_i16_d16lo_zero_hi_immneg128: 2055; GCN: ; %bb.0: 2056; GCN-NEXT: v_mov_b32_e32 v1, 0 2057; GCN-NEXT: global_load_short_d16 v1, v0, s[2:3] offset:-128 2058; GCN-NEXT: s_waitcnt vmcnt(0) 2059; GCN-NEXT: v_mov_b32_e32 v0, v1 2060; GCN-NEXT: ; return to shader part epilog 2061 %zext.offset = zext i32 %voffset to i64 2062 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2063 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2064 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 2065 %load = load i16, i16 addrspace(1)* %gep1.cast 2066 %build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 0 2067 %cast = bitcast <2 x i16> %build to <2 x half> 2068 ret <2 x half> %cast 2069} 2070 2071define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_reg_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2072; GCN-LABEL: global_load_saddr_i16_d16lo_reg_hi: 2073; GCN: ; %bb.0: 2074; GCN-NEXT: global_load_short_d16 v1, v0, s[2:3] 2075; GCN-NEXT: s_waitcnt vmcnt(0) 2076; GCN-NEXT: v_mov_b32_e32 v0, v1 2077; GCN-NEXT: ; return to shader part epilog 2078 %zext.offset = zext i32 %voffset to i64 2079 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2080 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 2081 %load = load i16, i16 addrspace(1)* %gep0.cast 2082 %build = insertelement <2 x i16> %reg, i16 %load, i32 0 2083 %cast = bitcast <2 x i16> %build to <2 x half> 2084 ret <2 x half> %cast 2085} 2086 2087define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_reg_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2088; GCN-LABEL: global_load_saddr_i16_d16lo_reg_hi_immneg128: 2089; GCN: ; %bb.0: 2090; GCN-NEXT: global_load_short_d16 v1, v0, s[2:3] offset:-128 2091; GCN-NEXT: s_waitcnt vmcnt(0) 2092; GCN-NEXT: v_mov_b32_e32 v0, v1 2093; GCN-NEXT: ; return to shader part epilog 2094 %zext.offset = zext i32 %voffset to i64 2095 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2096 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2097 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 2098 %load = load i16, i16 addrspace(1)* %gep1.cast 2099 %build = insertelement <2 x i16> %reg, i16 %load, i32 0 2100 %cast = bitcast <2 x i16> %build to <2 x half> 2101 ret <2 x half> %cast 2102} 2103 2104define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zexti8_reg_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2105; GCN-LABEL: global_load_saddr_i16_d16lo_zexti8_reg_hi: 2106; GCN: ; %bb.0: 2107; GCN-NEXT: global_load_ubyte_d16 v1, v0, s[2:3] 2108; GCN-NEXT: s_waitcnt vmcnt(0) 2109; GCN-NEXT: v_mov_b32_e32 v0, v1 2110; GCN-NEXT: ; return to shader part epilog 2111 %zext.offset = zext i32 %voffset to i64 2112 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2113 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(1)* 2114 %load = load i8, i8 addrspace(1)* %gep0.cast 2115 %zext.load = zext i8 %load to i16 2116 %build = insertelement <2 x i16> %reg, i16 %zext.load, i32 0 2117 %cast = bitcast <2 x i16> %build to <2 x half> 2118 ret <2 x half> %cast 2119} 2120 2121define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2122; GCN-LABEL: global_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128: 2123; GCN: ; %bb.0: 2124; GCN-NEXT: global_load_ubyte_d16 v1, v0, s[2:3] offset:-128 2125; GCN-NEXT: s_waitcnt vmcnt(0) 2126; GCN-NEXT: v_mov_b32_e32 v0, v1 2127; GCN-NEXT: ; return to shader part epilog 2128 %zext.offset = zext i32 %voffset to i64 2129 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2130 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2131 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(1)* 2132 %load = load i8, i8 addrspace(1)* %gep1.cast 2133 %zext.load = zext i8 %load to i16 2134 %build = insertelement <2 x i16> %reg, i16 %zext.load, i32 0 2135 %cast = bitcast <2 x i16> %build to <2 x half> 2136 ret <2 x half> %cast 2137} 2138 2139define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_sexti8_reg_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2140; GCN-LABEL: global_load_saddr_i16_d16lo_sexti8_reg_hi: 2141; GCN: ; %bb.0: 2142; GCN-NEXT: global_load_sbyte_d16 v1, v0, s[2:3] 2143; GCN-NEXT: s_waitcnt vmcnt(0) 2144; GCN-NEXT: v_mov_b32_e32 v0, v1 2145; GCN-NEXT: ; return to shader part epilog 2146 %zext.offset = zext i32 %voffset to i64 2147 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2148 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(1)* 2149 %load = load i8, i8 addrspace(1)* %gep0.cast 2150 %sext.load = sext i8 %load to i16 2151 %build = insertelement <2 x i16> %reg, i16 %sext.load, i32 0 2152 %cast = bitcast <2 x i16> %build to <2 x half> 2153 ret <2 x half> %cast 2154} 2155 2156define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2157; GCN-LABEL: global_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128: 2158; GCN: ; %bb.0: 2159; GCN-NEXT: global_load_sbyte_d16 v1, v0, s[2:3] offset:-128 2160; GCN-NEXT: s_waitcnt vmcnt(0) 2161; GCN-NEXT: v_mov_b32_e32 v0, v1 2162; GCN-NEXT: ; return to shader part epilog 2163 %zext.offset = zext i32 %voffset to i64 2164 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2165 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2166 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(1)* 2167 %load = load i8, i8 addrspace(1)* %gep1.cast 2168 %sext.load = sext i8 %load to i16 2169 %build = insertelement <2 x i16> %reg, i16 %sext.load, i32 0 2170 %cast = bitcast <2 x i16> %build to <2 x half> 2171 ret <2 x half> %cast 2172} 2173 2174; -------------------------------------------------------------------------------- 2175; D16 hi load (hi16) 2176; -------------------------------------------------------------------------------- 2177 2178define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_undef_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 2179; GCN-LABEL: global_load_saddr_i16_d16hi_undef_hi: 2180; GCN: ; %bb.0: 2181; GCN-NEXT: global_load_short_d16_hi v0, v0, s[2:3] 2182; GCN-NEXT: s_waitcnt vmcnt(0) 2183; GCN-NEXT: ; return to shader part epilog 2184 %zext.offset = zext i32 %voffset to i64 2185 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2186 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 2187 %load = load i16, i16 addrspace(1)* %gep0.cast 2188 %build = insertelement <2 x i16> undef, i16 %load, i32 1 2189 %cast = bitcast <2 x i16> %build to <2 x half> 2190 ret <2 x half> %cast 2191} 2192 2193define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_undef_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 2194; GCN-LABEL: global_load_saddr_i16_d16hi_undef_hi_immneg128: 2195; GCN: ; %bb.0: 2196; GCN-NEXT: global_load_short_d16_hi v0, v0, s[2:3] offset:-128 2197; GCN-NEXT: s_waitcnt vmcnt(0) 2198; GCN-NEXT: ; return to shader part epilog 2199 %zext.offset = zext i32 %voffset to i64 2200 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2201 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2202 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 2203 %load = load i16, i16 addrspace(1)* %gep1.cast 2204 %build = insertelement <2 x i16> undef, i16 %load, i32 1 2205 %cast = bitcast <2 x i16> %build to <2 x half> 2206 ret <2 x half> %cast 2207} 2208 2209define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 2210; GCN-LABEL: global_load_saddr_i16_d16hi_zero_hi: 2211; GCN: ; %bb.0: 2212; GCN-NEXT: v_mov_b32_e32 v1, 0 2213; GCN-NEXT: global_load_short_d16_hi v1, v0, s[2:3] 2214; GCN-NEXT: s_waitcnt vmcnt(0) 2215; GCN-NEXT: v_mov_b32_e32 v0, v1 2216; GCN-NEXT: ; return to shader part epilog 2217 %zext.offset = zext i32 %voffset to i64 2218 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2219 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 2220 %load = load i16, i16 addrspace(1)* %gep0.cast 2221 %build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 1 2222 %cast = bitcast <2 x i16> %build to <2 x half> 2223 ret <2 x half> %cast 2224} 2225 2226define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset) { 2227; GCN-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128: 2228; GCN: ; %bb.0: 2229; GCN-NEXT: v_mov_b32_e32 v1, 0 2230; GCN-NEXT: global_load_short_d16_hi v1, v0, s[2:3] offset:-128 2231; GCN-NEXT: s_waitcnt vmcnt(0) 2232; GCN-NEXT: v_mov_b32_e32 v0, v1 2233; GCN-NEXT: ; return to shader part epilog 2234 %zext.offset = zext i32 %voffset to i64 2235 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2236 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2237 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 2238 %load = load i16, i16 addrspace(1)* %gep1.cast 2239 %build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 1 2240 %cast = bitcast <2 x i16> %build to <2 x half> 2241 ret <2 x half> %cast 2242} 2243 2244define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_reg_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2245; GCN-LABEL: global_load_saddr_i16_d16hi_reg_hi: 2246; GCN: ; %bb.0: 2247; GCN-NEXT: global_load_short_d16_hi v1, v0, s[2:3] 2248; GCN-NEXT: s_waitcnt vmcnt(0) 2249; GCN-NEXT: v_mov_b32_e32 v0, v1 2250; GCN-NEXT: ; return to shader part epilog 2251 %zext.offset = zext i32 %voffset to i64 2252 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2253 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i16 addrspace(1)* 2254 %load = load i16, i16 addrspace(1)* %gep0.cast 2255 %build = insertelement <2 x i16> %reg, i16 %load, i32 1 2256 %cast = bitcast <2 x i16> %build to <2 x half> 2257 ret <2 x half> %cast 2258} 2259 2260define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_reg_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2261; GCN-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128: 2262; GCN: ; %bb.0: 2263; GCN-NEXT: global_load_short_d16_hi v1, v0, s[2:3] offset:-128 2264; GCN-NEXT: s_waitcnt vmcnt(0) 2265; GCN-NEXT: v_mov_b32_e32 v0, v1 2266; GCN-NEXT: ; return to shader part epilog 2267 %zext.offset = zext i32 %voffset to i64 2268 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2269 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2270 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i16 addrspace(1)* 2271 %load = load i16, i16 addrspace(1)* %gep1.cast 2272 %build = insertelement <2 x i16> %reg, i16 %load, i32 1 2273 %cast = bitcast <2 x i16> %build to <2 x half> 2274 ret <2 x half> %cast 2275} 2276 2277define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zexti8_reg_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2278; GCN-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi: 2279; GCN: ; %bb.0: 2280; GCN-NEXT: global_load_ubyte_d16_hi v1, v0, s[2:3] 2281; GCN-NEXT: s_waitcnt vmcnt(0) 2282; GCN-NEXT: v_mov_b32_e32 v0, v1 2283; GCN-NEXT: ; return to shader part epilog 2284 %zext.offset = zext i32 %voffset to i64 2285 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2286 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(1)* 2287 %load = load i8, i8 addrspace(1)* %gep0.cast 2288 %zext.load = zext i8 %load to i16 2289 %build = insertelement <2 x i16> %reg, i16 %zext.load, i32 1 2290 %cast = bitcast <2 x i16> %build to <2 x half> 2291 ret <2 x half> %cast 2292} 2293 2294define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2295; GCN-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128: 2296; GCN: ; %bb.0: 2297; GCN-NEXT: global_load_ubyte_d16_hi v1, v0, s[2:3] offset:-128 2298; GCN-NEXT: s_waitcnt vmcnt(0) 2299; GCN-NEXT: v_mov_b32_e32 v0, v1 2300; GCN-NEXT: ; return to shader part epilog 2301 %zext.offset = zext i32 %voffset to i64 2302 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2303 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2304 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(1)* 2305 %load = load i8, i8 addrspace(1)* %gep1.cast 2306 %zext.load = zext i8 %load to i16 2307 %build = insertelement <2 x i16> %reg, i16 %zext.load, i32 1 2308 %cast = bitcast <2 x i16> %build to <2 x half> 2309 ret <2 x half> %cast 2310} 2311 2312define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_sexti8_reg_hi(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2313; GCN-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi: 2314; GCN: ; %bb.0: 2315; GCN-NEXT: global_load_sbyte_d16_hi v1, v0, s[2:3] 2316; GCN-NEXT: s_waitcnt vmcnt(0) 2317; GCN-NEXT: v_mov_b32_e32 v0, v1 2318; GCN-NEXT: ; return to shader part epilog 2319 %zext.offset = zext i32 %voffset to i64 2320 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2321 %gep0.cast = bitcast i8 addrspace(1)* %gep0 to i8 addrspace(1)* 2322 %load = load i8, i8 addrspace(1)* %gep0.cast 2323 %sext.load = sext i8 %load to i16 2324 %build = insertelement <2 x i16> %reg, i16 %sext.load, i32 1 2325 %cast = bitcast <2 x i16> %build to <2 x half> 2326 ret <2 x half> %cast 2327} 2328 2329define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, <2 x i16> %reg) { 2330; GCN-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128: 2331; GCN: ; %bb.0: 2332; GCN-NEXT: global_load_sbyte_d16_hi v1, v0, s[2:3] offset:-128 2333; GCN-NEXT: s_waitcnt vmcnt(0) 2334; GCN-NEXT: v_mov_b32_e32 v0, v1 2335; GCN-NEXT: ; return to shader part epilog 2336 %zext.offset = zext i32 %voffset to i64 2337 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 2338 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 2339 %gep1.cast = bitcast i8 addrspace(1)* %gep1 to i8 addrspace(1)* 2340 %load = load i8, i8 addrspace(1)* %gep1.cast 2341 %sext.load = sext i8 %load to i16 2342 %build = insertelement <2 x i16> %reg, i16 %sext.load, i32 1 2343 %cast = bitcast <2 x i16> %build to <2 x half> 2344 ret <2 x half> %cast 2345} 2346 2347; -------------------------------------------------------------------------------- 2348; or-with-constant as add 2349; -------------------------------------------------------------------------------- 2350 2351; Check add-as-or with split 64-bit or. 2352define amdgpu_ps float @global_load_saddr_i8_offset_or_i64_imm_offset_16(i8 addrspace(6)* inreg %sbase, i32 %idx) { 2353; GCN-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_16: 2354; GCN: ; %bb.0: 2355; GCN-NEXT: v_or_b32_e32 v0, 16, v0 2356; GCN-NEXT: v_mov_b32_e32 v1, 0 2357; GCN-NEXT: global_load_ubyte v0, v[0:1], off 2358; GCN-NEXT: s_waitcnt vmcnt(0) 2359; GCN-NEXT: ; return to shader part epilog 2360 %zext.idx = zext i32 %idx to i64 2361 %or = or i64 %zext.idx, 16 2362 %addr = inttoptr i64 %or to i8 addrspace(1)* 2363 %load = load i8, i8 addrspace(1)* %addr 2364 %zext = zext i8 %load to i32 2365 %to.vgpr = bitcast i32 %zext to float 2366 ret float %to.vgpr 2367} 2368 2369define amdgpu_ps float @global_load_saddr_i8_offset_or_i64_imm_offset_4160(i8 addrspace(6)* inreg %sbase, i32 %idx) { 2370; GCN-LABEL: global_load_saddr_i8_offset_or_i64_imm_offset_4160: 2371; GCN: ; %bb.0: 2372; GCN-NEXT: v_or_b32_e32 v0, 0x1040, v0 2373; GCN-NEXT: v_mov_b32_e32 v1, 0 2374; GCN-NEXT: global_load_ubyte v0, v[0:1], off 2375; GCN-NEXT: s_waitcnt vmcnt(0) 2376; GCN-NEXT: ; return to shader part epilog 2377 %zext.idx = zext i32 %idx to i64 2378 %or = or i64 %zext.idx, 4160 2379 %addr = inttoptr i64 %or to i8 addrspace(1)* 2380 %load = load i8, i8 addrspace(1)* %addr 2381 %zext = zext i8 %load to i32 2382 %to.vgpr = bitcast i32 %zext to float 2383 ret float %to.vgpr 2384} 2385 2386!0 = !{i32 0, i32 1073741824} ; (1 << 30) 2387!1 = !{i32 0, i32 1073741825} ; (1 << 30) + 1 2388