1; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
2; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
3
4; Does not apply to wave64
5; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
6; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
7
8; Does not apply to gfx1101
9; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
10; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1101 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,NOWORKAROUND %s
11
12; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
13; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,WORKAROUND %s
14
15; There aren't any stack objects, but we still enable the
16; private_segment_wavefront_offset to get to 16, and the workgroup ID
17; is in s14.
18
19; private_segment_buffer + workgroup_id_x = 5, + 11 padding
20
21; GCN-LABEL: {{^}}minimal_kernel_inputs:
22; WORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s15
23; NOWORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s0
24; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
25
26; GCN: .amdhsa_kernel minimal_kernel_inputs
27; WORKAROUND: .amdhsa_user_sgpr_count 15
28; NOWORKAROUND: .amdhsa_user_sgpr_count 0
29; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
30; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0
31; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
32; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
33; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
34; GCN-NEXT: .amdhsa_wavefront_size32
35; GCN-NEXT: .amdhsa_uses_dynamic_stack 0
36; GCN-NEXT: .amdhsa_enable_private_segment 0
37; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
38; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
39; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
40; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
41; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
42; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
43; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
44define amdgpu_kernel void @minimal_kernel_inputs() {
45  %id = call i32 @llvm.amdgcn.workgroup.id.x()
46  store volatile i32 %id, i32 addrspace(1)* undef
47  ret void
48}
49
50; GCN-LABEL: {{^}}minimal_kernel_inputs_with_stack:
51; WORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s15
52; NOWORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s0
53; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
54
55; GCN: .amdhsa_kernel minimal_kernel_inputs
56; WORKAROUND: .amdhsa_user_sgpr_count 15
57; NOWORKAROUND: .amdhsa_user_sgpr_count 0
58; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
59; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0
60; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
61; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
62; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
63; GCN-NEXT: .amdhsa_wavefront_size32
64; GCN-NEXT: .amdhsa_uses_dynamic_stack 0
65; GCN-NEXT: .amdhsa_enable_private_segment 1
66; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
67; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
68; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
69; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
70; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
71; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
72; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 0
73define amdgpu_kernel void @minimal_kernel_inputs_with_stack() {
74  %alloca = alloca i32, addrspace(5)
75  %id = call i32 @llvm.amdgcn.workgroup.id.x()
76  store volatile i32 %id, i32 addrspace(1)* undef
77  store volatile i32 0, i32 addrspace(5)* %alloca
78  ret void
79}
80
81; GCN-LABEL: {{^}}queue_ptr:
82; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
83
84; WORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s15
85; NOWORKAROUND: v_mov_b32_e32 [[V:v[0-9]+]], s2
86; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
87
88; GCN: .amdhsa_kernel queue_ptr
89; WORKAROUND: .amdhsa_user_sgpr_count 15
90; NOWORKAROUND: .amdhsa_user_sgpr_count 2
91; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
92; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1
93; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
94; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
95; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
96; GCN-NEXT: .amdhsa_wavefront_size32
97; GCN-NEXT: .amdhsa_uses_dynamic_stack 0
98; GCN-NEXT: .amdhsa_enable_private_segment 0
99; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
100; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
101; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
102; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
103; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
104; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
105; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 2
106define amdgpu_kernel void @queue_ptr() {
107  %queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
108  %load = load volatile i8, i8 addrspace(4)* %queue.ptr
109  %id = call i32 @llvm.amdgcn.workgroup.id.x()
110  store volatile i32 %id, i32 addrspace(1)* undef
111  ret void
112}
113
114; GCN-LABEL: {{^}}all_inputs:
115; WORKAROUND: v_mov_b32_e32 [[V_X:v[0-9]+]], s13
116; WORKAROUND: v_mov_b32_e32 [[V_Y:v[0-9]+]], s14
117; WORKAROUND: v_mov_b32_e32 [[V_Z:v[0-9]+]], s15
118
119; NOWORKAROUND: v_mov_b32_e32 [[V_X:v[0-9]+]], s8
120; NOWORKAROUND: v_mov_b32_e32 [[V_Y:v[0-9]+]], s9
121; NOWORKAROUND: v_mov_b32_e32 [[V_Z:v[0-9]+]], s10
122
123; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
124; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[2:3]
125; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5]
126
127; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s6
128; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s7
129
130; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_X]], off
131; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Y]], off
132; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Z]], off
133; GCN: global_store_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[DISPATCH_LO]]:[[DISPATCH_HI]]{{\]}}, off
134
135; GCN: .amdhsa_kernel all_inputs
136; WORKAROUND: .amdhsa_user_sgpr_count 13
137; NOWORKAROUND: .amdhsa_user_sgpr_count 8
138; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1
139; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1
140; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1
141; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 1
142; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
143; GCN-NEXT: .amdhsa_wavefront_size32
144; GCN-NEXT: .amdhsa_uses_dynamic_stack 0
145; GCN-NEXT: .amdhsa_enable_private_segment 1
146; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
147; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1
148; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
149; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
150; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
151; WORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13
152; NOWORKAROUND: ; COMPUTE_PGM_RSRC2:USER_SGPR: 8
153define amdgpu_kernel void @all_inputs() {
154  %alloca = alloca i32, addrspace(5)
155  store volatile i32 0, i32 addrspace(5)* %alloca
156
157  %dispatch.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
158  %load.dispatch = load volatile i8, i8 addrspace(4)* %dispatch.ptr
159
160  %queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
161  %load.queue = load volatile i8, i8 addrspace(4)* %queue.ptr
162
163  %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
164  %load.implicitarg = load volatile i8, i8 addrspace(4)* %implicitarg.ptr
165
166  %id.x = call i32 @llvm.amdgcn.workgroup.id.x()
167  store volatile i32 %id.x, i32 addrspace(1)* undef
168
169  %id.y = call i32 @llvm.amdgcn.workgroup.id.y()
170  store volatile i32 %id.y, i32 addrspace(1)* undef
171
172  %id.z = call i32 @llvm.amdgcn.workgroup.id.z()
173  store volatile i32 %id.z, i32 addrspace(1)* undef
174
175  %dispatch.id = call i64 @llvm.amdgcn.dispatch.id()
176  store volatile i64 %dispatch.id, i64 addrspace(1)* undef
177
178  ret void
179}
180
181declare i32 @llvm.amdgcn.workgroup.id.x() #0
182declare i32 @llvm.amdgcn.workgroup.id.y() #0
183declare i32 @llvm.amdgcn.workgroup.id.z() #0
184declare align 4 i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
185declare align 4 i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
186declare align 4 i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
187declare align 4 i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
188declare i64 @llvm.amdgcn.dispatch.id() #0
189
190attributes #0 = { nounwind readnone speculatable willreturn }
191