1; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s 2; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s 3; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s 4; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s 5 6; There aren't any stack objects, but we still enable the 7; private_segment_wavefront_offset to get to 16, and the workgroup ID 8; is in s14. 9 10; private_segment_buffer + workgroup_id_x = 5, + 11 padding 11 12; GCN-LABEL: {{^}}minimal_kernel_inputs: 13; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 14; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off 15 16; GCN: .amdhsa_kernel minimal_kernel_inputs 17; GCN: .amdhsa_user_sgpr_count 15 18; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 19; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0 20; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 21; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 22; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 23; GCN-NEXT: .amdhsa_wavefront_size32 1 24; GCN-NEXT: .amdhsa_enable_private_segment 0 25; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 26; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 27; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 28; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 29; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 30; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 31define amdgpu_kernel void @minimal_kernel_inputs() { 32 %id = call i32 @llvm.amdgcn.workgroup.id.x() 33 store volatile i32 %id, i32 addrspace(1)* undef 34 ret void 35} 36 37; GCN-LABEL: {{^}}minimal_kernel_inputs_with_stack: 38; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 39; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off 40 41; GCN: .amdhsa_kernel minimal_kernel_inputs 42; GCN: .amdhsa_user_sgpr_count 15 43; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 44; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0 45; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 46; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 47; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 48; GCN-NEXT: .amdhsa_wavefront_size32 1 49; GCN-NEXT: .amdhsa_enable_private_segment 1 50; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 51; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 52; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 53; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 54; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 55; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 56define amdgpu_kernel void @minimal_kernel_inputs_with_stack() { 57 %alloca = alloca i32, addrspace(5) 58 %id = call i32 @llvm.amdgcn.workgroup.id.x() 59 store volatile i32 %id, i32 addrspace(1)* undef 60 store volatile i32 0, i32 addrspace(5)* %alloca 61 ret void 62} 63 64; GCN-LABEL: {{^}}queue_ptr: 65; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1] 66 67; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 68; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off 69 70; GCN: .amdhsa_kernel queue_ptr 71; GCN: .amdhsa_user_sgpr_count 15 72; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 73; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1 74; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 75; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 76; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 77; GCN-NEXT: .amdhsa_wavefront_size32 1 78; GCN-NEXT: .amdhsa_enable_private_segment 0 79; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 80; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 81; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 82; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 83; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 84; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 85define amdgpu_kernel void @queue_ptr() { 86 %queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 87 %load = load volatile i8, i8 addrspace(4)* %queue.ptr 88 %id = call i32 @llvm.amdgcn.workgroup.id.x() 89 store volatile i32 %id, i32 addrspace(1)* undef 90 ret void 91} 92 93; GCN-LABEL: {{^}}all_inputs: 94; GCN: v_mov_b32_e32 [[V_X:v[0-9]+]], s13 95; GCN: v_mov_b32_e32 [[V_Y:v[0-9]+]], s14 96; GCN: v_mov_b32_e32 [[V_Z:v[0-9]+]], s15 97 98; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1] 99; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[2:3] 100; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5] 101 102; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s6 103; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s7 104 105; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_X]], off 106; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Y]], off 107; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Z]], off 108; GCN: global_store_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[DISPATCH_LO]]:[[DISPATCH_HI]]{{\]}}, off 109 110; GCN: .amdhsa_kernel all_inputs 111; GCN: .amdhsa_user_sgpr_count 13 112; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1 113; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1 114; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1 115; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 1 116; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 117; GCN-NEXT: .amdhsa_wavefront_size32 1 118; GCN-NEXT: .amdhsa_enable_private_segment 1 119; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 120; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1 121; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1 122; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 123; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 124; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 125define amdgpu_kernel void @all_inputs() { 126 %alloca = alloca i32, addrspace(5) 127 store volatile i32 0, i32 addrspace(5)* %alloca 128 129 %dispatch.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 130 %load.dispatch = load volatile i8, i8 addrspace(4)* %dispatch.ptr 131 132 %queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() 133 %load.queue = load volatile i8, i8 addrspace(4)* %queue.ptr 134 135 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 136 %load.implicitarg = load volatile i8, i8 addrspace(4)* %implicitarg.ptr 137 138 %id.x = call i32 @llvm.amdgcn.workgroup.id.x() 139 store volatile i32 %id.x, i32 addrspace(1)* undef 140 141 %id.y = call i32 @llvm.amdgcn.workgroup.id.y() 142 store volatile i32 %id.y, i32 addrspace(1)* undef 143 144 %id.z = call i32 @llvm.amdgcn.workgroup.id.z() 145 store volatile i32 %id.z, i32 addrspace(1)* undef 146 147 %dispatch.id = call i64 @llvm.amdgcn.dispatch.id() 148 store volatile i64 %dispatch.id, i64 addrspace(1)* undef 149 150 ret void 151} 152 153declare i32 @llvm.amdgcn.workgroup.id.x() #0 154declare i32 @llvm.amdgcn.workgroup.id.y() #0 155declare i32 @llvm.amdgcn.workgroup.id.z() #0 156declare align 4 i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0 157declare align 4 i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 158declare align 4 i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 159declare align 4 i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0 160declare i64 @llvm.amdgcn.dispatch.id() #0 161 162attributes #0 = { nounwind readnone speculatable willreturn } 163