1; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s 2; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s 3; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s 4; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s 5 6; There aren't any stack objects, but we still enable the 7; private_segment_wavefront_offset to get to 16, and the workgroup ID 8; is in s14. 9 10; private_segment_buffer + workgroup_id_x = 5, + 11 padding 11 12; GCN-LABEL: {{^}}minimal_kernel_inputs: 13; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 14; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off 15 16; GCN: .amdhsa_kernel minimal_kernel_inputs 17; GCN: .amdhsa_user_sgpr_count 15 18; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 19; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0 20; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 21; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 22; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 23; GCN-NEXT: .amdhsa_wavefront_size32 1 24; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 25; GCN-NEXT: .amdhsa_enable_private_segment 0 26; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 27; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 28; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 29; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 30; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 31; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 32define amdgpu_kernel void @minimal_kernel_inputs() { 33 %id = call i32 @llvm.amdgcn.workgroup.id.x() 34 store volatile i32 %id, i32 addrspace(1)* undef 35 ret void 36} 37 38; GCN-LABEL: {{^}}minimal_kernel_inputs_with_stack: 39; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 40; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off 41 42; GCN: .amdhsa_kernel minimal_kernel_inputs 43; GCN: .amdhsa_user_sgpr_count 15 44; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 45; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0 46; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 47; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 48; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 49; GCN-NEXT: .amdhsa_wavefront_size32 1 50; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 51; GCN-NEXT: .amdhsa_enable_private_segment 1 52; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 53; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 54; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 55; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 56; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 57; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 58define amdgpu_kernel void @minimal_kernel_inputs_with_stack() { 59 %alloca = alloca i32, addrspace(5) 60 %id = call i32 @llvm.amdgcn.workgroup.id.x() 61 store volatile i32 %id, i32 addrspace(1)* undef 62 store volatile i32 0, i32 addrspace(5)* %alloca 63 ret void 64} 65 66; GCN-LABEL: {{^}}queue_ptr: 67; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1] 68 69; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15 70; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off 71 72; GCN: .amdhsa_kernel queue_ptr 73; GCN: .amdhsa_user_sgpr_count 15 74; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 75; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1 76; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0 77; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0 78; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 79; GCN-NEXT: .amdhsa_wavefront_size32 1 80; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 81; GCN-NEXT: .amdhsa_enable_private_segment 0 82; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 83; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0 84; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0 85; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 86; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 87; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15 88define amdgpu_kernel void @queue_ptr() { 89 %queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 90 %load = load volatile i8, i8 addrspace(4)* %queue.ptr 91 %id = call i32 @llvm.amdgcn.workgroup.id.x() 92 store volatile i32 %id, i32 addrspace(1)* undef 93 ret void 94} 95 96; GCN-LABEL: {{^}}all_inputs: 97; GCN: v_mov_b32_e32 [[V_X:v[0-9]+]], s13 98; GCN: v_mov_b32_e32 [[V_Y:v[0-9]+]], s14 99; GCN: v_mov_b32_e32 [[V_Z:v[0-9]+]], s15 100 101; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1] 102; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[2:3] 103; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5] 104 105; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s6 106; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s7 107 108; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_X]], off 109; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Y]], off 110; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Z]], off 111; GCN: global_store_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[DISPATCH_LO]]:[[DISPATCH_HI]]{{\]}}, off 112 113; GCN: .amdhsa_kernel all_inputs 114; GCN: .amdhsa_user_sgpr_count 13 115; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1 116; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1 117; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1 118; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 1 119; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0 120; GCN-NEXT: .amdhsa_wavefront_size32 1 121; GCN-NEXT: .amdhsa_uses_dynamic_stack 0 122; GCN-NEXT: .amdhsa_enable_private_segment 1 123; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1 124; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1 125; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1 126; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0 127; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0 128; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13 129define amdgpu_kernel void @all_inputs() { 130 %alloca = alloca i32, addrspace(5) 131 store volatile i32 0, i32 addrspace(5)* %alloca 132 133 %dispatch.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 134 %load.dispatch = load volatile i8, i8 addrspace(4)* %dispatch.ptr 135 136 %queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() 137 %load.queue = load volatile i8, i8 addrspace(4)* %queue.ptr 138 139 %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 140 %load.implicitarg = load volatile i8, i8 addrspace(4)* %implicitarg.ptr 141 142 %id.x = call i32 @llvm.amdgcn.workgroup.id.x() 143 store volatile i32 %id.x, i32 addrspace(1)* undef 144 145 %id.y = call i32 @llvm.amdgcn.workgroup.id.y() 146 store volatile i32 %id.y, i32 addrspace(1)* undef 147 148 %id.z = call i32 @llvm.amdgcn.workgroup.id.z() 149 store volatile i32 %id.z, i32 addrspace(1)* undef 150 151 %dispatch.id = call i64 @llvm.amdgcn.dispatch.id() 152 store volatile i64 %dispatch.id, i64 addrspace(1)* undef 153 154 ret void 155} 156 157declare i32 @llvm.amdgcn.workgroup.id.x() #0 158declare i32 @llvm.amdgcn.workgroup.id.y() #0 159declare i32 @llvm.amdgcn.workgroup.id.z() #0 160declare align 4 i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0 161declare align 4 i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 162declare align 4 i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 163declare align 4 i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0 164declare i64 @llvm.amdgcn.dispatch.id() #0 165 166attributes #0 = { nounwind readnone speculatable willreturn } 167