1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
3
4define amdgpu_kernel void @divergent_or3_b32(<3 x i32> addrspace(1)* %arg) {
5; GCN-LABEL: divergent_or3_b32:
6; GCN:       ; %bb.0: ; %bb
7; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
8; GCN-NEXT:    v_lshlrev_b32_e32 v3, 4, v0
9; GCN-NEXT:    s_waitcnt lgkmcnt(0)
10; GCN-NEXT:    global_load_dwordx3 v[0:2], v3, s[0:1]
11; GCN-NEXT:    s_waitcnt vmcnt(0)
12; GCN-NEXT:    v_or3_b32 v0, v1, v0, v2
13; GCN-NEXT:    v_not_b32_e32 v0, v0
14; GCN-NEXT:    global_store_dword v3, v0, s[0:1]
15; GCN-NEXT:    s_endpgm
16bb:
17  %i = tail call i32 @llvm.amdgcn.workitem.id.x()
18  %i1 = zext i32 %i to i64
19  %i2 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 %i1
20  %i3 = load <3 x i32>, <3 x i32> addrspace(1)* %i2, align 16
21  %i4 = extractelement <3 x i32> %i3, i64 0
22  %i5 = extractelement <3 x i32> %i3, i64 1
23  %i6 = extractelement <3 x i32> %i3, i64 2
24  %i7 = or i32 %i5, %i4
25  %i8 = or i32 %i7, %i6
26  %i9 = xor i32 %i8, -1
27  %i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %i2, i64 0, i64 0
28  store i32 %i9, i32 addrspace(1)* %i10, align 16
29  ret void
30}
31
32define amdgpu_kernel void @divergent_or3_b64(<3 x i64> addrspace(1)* %arg) {
33; GCN-LABEL: divergent_or3_b64:
34; GCN:       ; %bb.0: ; %bb
35; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
36; GCN-NEXT:    v_lshlrev_b32_e32 v6, 5, v0
37; GCN-NEXT:    s_waitcnt lgkmcnt(0)
38; GCN-NEXT:    global_load_dwordx2 v[4:5], v6, s[0:1] offset:16
39; GCN-NEXT:    global_load_dwordx4 v[0:3], v6, s[0:1]
40; GCN-NEXT:    s_waitcnt vmcnt(0)
41; GCN-NEXT:    v_or3_b32 v1, v3, v1, v5
42; GCN-NEXT:    v_or3_b32 v0, v2, v0, v4
43; GCN-NEXT:    v_not_b32_e32 v0, v0
44; GCN-NEXT:    v_not_b32_e32 v1, v1
45; GCN-NEXT:    global_store_dwordx2 v6, v[0:1], s[0:1]
46; GCN-NEXT:    s_endpgm
47bb:
48  %i = tail call i32 @llvm.amdgcn.workitem.id.x()
49  %i1 = zext i32 %i to i64
50  %i2 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 %i1
51  %i3 = load <3 x i64>, <3 x i64> addrspace(1)* %i2, align 32
52  %i4 = extractelement <3 x i64> %i3, i64 0
53  %i5 = extractelement <3 x i64> %i3, i64 1
54  %i6 = extractelement <3 x i64> %i3, i64 2
55  %i7 = or i64 %i5, %i4
56  %i8 = or i64 %i7, %i6
57  %i9 = xor i64 %i8, -1
58  %i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %i2, i64 0, i64 0
59  store i64 %i9, i64 addrspace(1)* %i10, align 32
60  ret void
61}
62
63define amdgpu_kernel void @divergent_and3_b32(<3 x i32> addrspace(1)* %arg) {
64; GCN-LABEL: divergent_and3_b32:
65; GCN:       ; %bb.0: ; %bb
66; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
67; GCN-NEXT:    v_lshlrev_b32_e32 v3, 4, v0
68; GCN-NEXT:    s_waitcnt lgkmcnt(0)
69; GCN-NEXT:    global_load_dwordx3 v[0:2], v3, s[0:1]
70; GCN-NEXT:    s_waitcnt vmcnt(0)
71; GCN-NEXT:    v_and_b32_e32 v0, v1, v0
72; GCN-NEXT:    v_and_b32_e32 v0, v0, v2
73; GCN-NEXT:    v_not_b32_e32 v0, v0
74; GCN-NEXT:    global_store_dword v3, v0, s[0:1]
75; GCN-NEXT:    s_endpgm
76bb:
77  %i = tail call i32 @llvm.amdgcn.workitem.id.x()
78  %i1 = zext i32 %i to i64
79  %i2 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 %i1
80  %i3 = load <3 x i32>, <3 x i32> addrspace(1)* %i2, align 16
81  %i4 = extractelement <3 x i32> %i3, i64 0
82  %i5 = extractelement <3 x i32> %i3, i64 1
83  %i6 = extractelement <3 x i32> %i3, i64 2
84  %i7 = and i32 %i5, %i4
85  %i8 = and i32 %i7, %i6
86  %i9 = xor i32 %i8, -1
87  %i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %i2, i64 0, i64 0
88  store i32 %i9, i32 addrspace(1)* %i10, align 16
89  ret void
90}
91
92define amdgpu_kernel void @divergent_and3_b64(<3 x i64> addrspace(1)* %arg) {
93; GCN-LABEL: divergent_and3_b64:
94; GCN:       ; %bb.0: ; %bb
95; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
96; GCN-NEXT:    v_lshlrev_b32_e32 v6, 5, v0
97; GCN-NEXT:    s_waitcnt lgkmcnt(0)
98; GCN-NEXT:    global_load_dwordx2 v[4:5], v6, s[0:1] offset:16
99; GCN-NEXT:    global_load_dwordx4 v[0:3], v6, s[0:1]
100; GCN-NEXT:    s_waitcnt vmcnt(0)
101; GCN-NEXT:    v_and_b32_e32 v1, v3, v1
102; GCN-NEXT:    v_and_b32_e32 v0, v2, v0
103; GCN-NEXT:    v_and_b32_e32 v1, v1, v5
104; GCN-NEXT:    v_and_b32_e32 v0, v0, v4
105; GCN-NEXT:    v_not_b32_e32 v0, v0
106; GCN-NEXT:    v_not_b32_e32 v1, v1
107; GCN-NEXT:    global_store_dwordx2 v6, v[0:1], s[0:1]
108; GCN-NEXT:    s_endpgm
109bb:
110  %i = tail call i32 @llvm.amdgcn.workitem.id.x()
111  %i1 = zext i32 %i to i64
112  %i2 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 %i1
113  %i3 = load <3 x i64>, <3 x i64> addrspace(1)* %i2, align 32
114  %i4 = extractelement <3 x i64> %i3, i64 0
115  %i5 = extractelement <3 x i64> %i3, i64 1
116  %i6 = extractelement <3 x i64> %i3, i64 2
117  %i7 = and i64 %i5, %i4
118  %i8 = and i64 %i7, %i6
119  %i9 = xor i64 %i8, -1
120  %i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %i2, i64 0, i64 0
121  store i64 %i9, i64 addrspace(1)* %i10, align 32
122  ret void
123}
124
125define amdgpu_kernel void @divergent_xor3_b32(<3 x i32> addrspace(1)* %arg) {
126; GCN-LABEL: divergent_xor3_b32:
127; GCN:       ; %bb.0: ; %bb
128; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
129; GCN-NEXT:    v_lshlrev_b32_e32 v3, 4, v0
130; GCN-NEXT:    s_waitcnt lgkmcnt(0)
131; GCN-NEXT:    global_load_dwordx3 v[0:2], v3, s[0:1]
132; GCN-NEXT:    s_waitcnt vmcnt(0)
133; GCN-NEXT:    v_xor_b32_e32 v0, v1, v0
134; GCN-NEXT:    v_xnor_b32_e32 v0, v0, v2
135; GCN-NEXT:    global_store_dword v3, v0, s[0:1]
136; GCN-NEXT:    s_endpgm
137bb:
138  %i = tail call i32 @llvm.amdgcn.workitem.id.x()
139  %i1 = zext i32 %i to i64
140  %i2 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 %i1
141  %i3 = load <3 x i32>, <3 x i32> addrspace(1)* %i2, align 16
142  %i4 = extractelement <3 x i32> %i3, i64 0
143  %i5 = extractelement <3 x i32> %i3, i64 1
144  %i6 = extractelement <3 x i32> %i3, i64 2
145  %i7 = xor i32 %i5, %i4
146  %i8 = xor i32 %i7, %i6
147  %i9 = xor i32 %i8, -1
148  %i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %i2, i64 0, i64 0
149  store i32 %i9, i32 addrspace(1)* %i10, align 16
150  ret void
151}
152
153define amdgpu_kernel void @divergent_xor3_b64(<3 x i64> addrspace(1)* %arg) {
154; GCN-LABEL: divergent_xor3_b64:
155; GCN:       ; %bb.0: ; %bb
156; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
157; GCN-NEXT:    v_lshlrev_b32_e32 v6, 5, v0
158; GCN-NEXT:    s_waitcnt lgkmcnt(0)
159; GCN-NEXT:    global_load_dwordx2 v[4:5], v6, s[0:1] offset:16
160; GCN-NEXT:    global_load_dwordx4 v[0:3], v6, s[0:1]
161; GCN-NEXT:    s_waitcnt vmcnt(0)
162; GCN-NEXT:    v_xor_b32_e32 v1, v3, v1
163; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
164; GCN-NEXT:    v_xnor_b32_e32 v0, v0, v4
165; GCN-NEXT:    v_xnor_b32_e32 v1, v1, v5
166; GCN-NEXT:    global_store_dwordx2 v6, v[0:1], s[0:1]
167; GCN-NEXT:    s_endpgm
168bb:
169  %i = tail call i32 @llvm.amdgcn.workitem.id.x()
170  %i1 = zext i32 %i to i64
171  %i2 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 %i1
172  %i3 = load <3 x i64>, <3 x i64> addrspace(1)* %i2, align 32
173  %i4 = extractelement <3 x i64> %i3, i64 0
174  %i5 = extractelement <3 x i64> %i3, i64 1
175  %i6 = extractelement <3 x i64> %i3, i64 2
176  %i7 = xor i64 %i5, %i4
177  %i8 = xor i64 %i7, %i6
178  %i9 = xor i64 %i8, -1
179  %i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %i2, i64 0, i64 0
180  store i64 %i9, i64 addrspace(1)* %i10, align 32
181  ret void
182}
183
184define amdgpu_kernel void @uniform_or3_b32(<3 x i32> addrspace(1)* %arg) {
185; GCN-LABEL: uniform_or3_b32:
186; GCN:       ; %bb.0: ; %bb
187; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
188; GCN-NEXT:    v_mov_b32_e32 v0, 0
189; GCN-NEXT:    s_waitcnt lgkmcnt(0)
190; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
191; GCN-NEXT:    s_waitcnt lgkmcnt(0)
192; GCN-NEXT:    s_or_b32 s0, s1, s0
193; GCN-NEXT:    s_nor_b32 s0, s0, s2
194; GCN-NEXT:    v_mov_b32_e32 v1, s0
195; GCN-NEXT:    global_store_dword v0, v1, s[4:5]
196; GCN-NEXT:    s_endpgm
197bb:
198  %i3 = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 16
199  %i4 = extractelement <3 x i32> %i3, i64 0
200  %i5 = extractelement <3 x i32> %i3, i64 1
201  %i6 = extractelement <3 x i32> %i3, i64 2
202  %i7 = or i32 %i5, %i4
203  %i8 = or i32 %i7, %i6
204  %i9 = xor i32 %i8, -1
205  %i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 0, i64 0
206  store i32 %i9, i32 addrspace(1)* %i10, align 16
207  ret void
208}
209
210define amdgpu_kernel void @uniform_or3_b64(<3 x i64> addrspace(1)* %arg) {
211; GCN-LABEL: uniform_or3_b64:
212; GCN:       ; %bb.0: ; %bb
213; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
214; GCN-NEXT:    v_mov_b32_e32 v2, 0
215; GCN-NEXT:    s_waitcnt lgkmcnt(0)
216; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
217; GCN-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x10
218; GCN-NEXT:    s_waitcnt lgkmcnt(0)
219; GCN-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
220; GCN-NEXT:    s_nor_b64 s[0:1], s[0:1], s[6:7]
221; GCN-NEXT:    v_mov_b32_e32 v0, s0
222; GCN-NEXT:    v_mov_b32_e32 v1, s1
223; GCN-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
224; GCN-NEXT:    s_endpgm
225bb:
226  %i3 = load <3 x i64>, <3 x i64> addrspace(1)* %arg, align 32
227  %i4 = extractelement <3 x i64> %i3, i64 0
228  %i5 = extractelement <3 x i64> %i3, i64 1
229  %i6 = extractelement <3 x i64> %i3, i64 2
230  %i7 = or i64 %i5, %i4
231  %i8 = or i64 %i7, %i6
232  %i9 = xor i64 %i8, -1
233  %i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 0, i64 0
234  store i64 %i9, i64 addrspace(1)* %i10, align 32
235  ret void
236}
237
238define amdgpu_kernel void @uniform_and3_b32(<3 x i32> addrspace(1)* %arg) {
239; GCN-LABEL: uniform_and3_b32:
240; GCN:       ; %bb.0: ; %bb
241; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
242; GCN-NEXT:    v_mov_b32_e32 v0, 0
243; GCN-NEXT:    s_waitcnt lgkmcnt(0)
244; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
245; GCN-NEXT:    s_waitcnt lgkmcnt(0)
246; GCN-NEXT:    s_and_b32 s0, s1, s0
247; GCN-NEXT:    s_nand_b32 s0, s0, s2
248; GCN-NEXT:    v_mov_b32_e32 v1, s0
249; GCN-NEXT:    global_store_dword v0, v1, s[4:5]
250; GCN-NEXT:    s_endpgm
251bb:
252  %i3 = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 16
253  %i4 = extractelement <3 x i32> %i3, i64 0
254  %i5 = extractelement <3 x i32> %i3, i64 1
255  %i6 = extractelement <3 x i32> %i3, i64 2
256  %i7 = and i32 %i5, %i4
257  %i8 = and i32 %i7, %i6
258  %i9 = xor i32 %i8, -1
259  %i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 0, i64 0
260  store i32 %i9, i32 addrspace(1)* %i10, align 16
261  ret void
262}
263
264define amdgpu_kernel void @uniform_and3_b64(<3 x i64> addrspace(1)* %arg) {
265; GCN-LABEL: uniform_and3_b64:
266; GCN:       ; %bb.0: ; %bb
267; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
268; GCN-NEXT:    v_mov_b32_e32 v2, 0
269; GCN-NEXT:    s_waitcnt lgkmcnt(0)
270; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
271; GCN-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x10
272; GCN-NEXT:    s_waitcnt lgkmcnt(0)
273; GCN-NEXT:    s_and_b64 s[0:1], s[2:3], s[0:1]
274; GCN-NEXT:    s_nand_b64 s[0:1], s[0:1], s[6:7]
275; GCN-NEXT:    v_mov_b32_e32 v0, s0
276; GCN-NEXT:    v_mov_b32_e32 v1, s1
277; GCN-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
278; GCN-NEXT:    s_endpgm
279bb:
280  %i3 = load <3 x i64>, <3 x i64> addrspace(1)* %arg, align 32
281  %i4 = extractelement <3 x i64> %i3, i64 0
282  %i5 = extractelement <3 x i64> %i3, i64 1
283  %i6 = extractelement <3 x i64> %i3, i64 2
284  %i7 = and i64 %i5, %i4
285  %i8 = and i64 %i7, %i6
286  %i9 = xor i64 %i8, -1
287  %i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 0, i64 0
288  store i64 %i9, i64 addrspace(1)* %i10, align 32
289  ret void
290}
291
292define amdgpu_kernel void @uniform_xor3_b32(<3 x i32> addrspace(1)* %arg) {
293; GCN-LABEL: uniform_xor3_b32:
294; GCN:       ; %bb.0: ; %bb
295; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
296; GCN-NEXT:    v_mov_b32_e32 v0, 0
297; GCN-NEXT:    s_waitcnt lgkmcnt(0)
298; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
299; GCN-NEXT:    s_waitcnt lgkmcnt(0)
300; GCN-NEXT:    s_xor_b32 s0, s1, s0
301; GCN-NEXT:    s_xnor_b32 s0, s0, s2
302; GCN-NEXT:    v_mov_b32_e32 v1, s0
303; GCN-NEXT:    global_store_dword v0, v1, s[4:5]
304; GCN-NEXT:    s_endpgm
305bb:
306  %i3 = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 16
307  %i4 = extractelement <3 x i32> %i3, i64 0
308  %i5 = extractelement <3 x i32> %i3, i64 1
309  %i6 = extractelement <3 x i32> %i3, i64 2
310  %i7 = xor i32 %i5, %i4
311  %i8 = xor i32 %i7, %i6
312  %i9 = xor i32 %i8, -1
313  %i10 = getelementptr inbounds <3 x i32>, <3 x i32> addrspace(1)* %arg, i64 0, i64 0
314  store i32 %i9, i32 addrspace(1)* %i10, align 16
315  ret void
316}
317
318define amdgpu_kernel void @uniform_xor3_b64(<3 x i64> addrspace(1)* %arg) {
319; GCN-LABEL: uniform_xor3_b64:
320; GCN:       ; %bb.0: ; %bb
321; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
322; GCN-NEXT:    v_mov_b32_e32 v2, 0
323; GCN-NEXT:    s_waitcnt lgkmcnt(0)
324; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
325; GCN-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x10
326; GCN-NEXT:    s_waitcnt lgkmcnt(0)
327; GCN-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
328; GCN-NEXT:    s_xnor_b64 s[0:1], s[0:1], s[6:7]
329; GCN-NEXT:    v_mov_b32_e32 v0, s0
330; GCN-NEXT:    v_mov_b32_e32 v1, s1
331; GCN-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
332; GCN-NEXT:    s_endpgm
333bb:
334  %i3 = load <3 x i64>, <3 x i64> addrspace(1)* %arg, align 32
335  %i4 = extractelement <3 x i64> %i3, i64 0
336  %i5 = extractelement <3 x i64> %i3, i64 1
337  %i6 = extractelement <3 x i64> %i3, i64 2
338  %i7 = xor i64 %i5, %i4
339  %i8 = xor i64 %i7, %i6
340  %i9 = xor i64 %i8, -1
341  %i10 = getelementptr inbounds <3 x i64>, <3 x i64> addrspace(1)* %arg, i64 0, i64 0
342  store i64 %i9, i64 addrspace(1)* %i10, align 32
343  ret void
344}
345
346declare i32 @llvm.amdgcn.workitem.id.x()
347