1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 4 5; FUNC-LABEL: {{^}}v_fsub_f32: 6; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 7define void @v_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 8 %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 9 %a = load float, float addrspace(1)* %in, align 4 10 %b = load float, float addrspace(1)* %b_ptr, align 4 11 %result = fsub float %a, %b 12 store float %result, float addrspace(1)* %out, align 4 13 ret void 14} 15 16; FUNC-LABEL: {{^}}s_fsub_f32: 17; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W 18 19; SI: v_sub_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 20define void @s_fsub_f32(float addrspace(1)* %out, float %a, float %b) { 21 %sub = fsub float %a, %b 22 store float %sub, float addrspace(1)* %out, align 4 23 ret void 24} 25 26declare float @llvm.r600.load.input(i32) readnone 27 28declare void @llvm.AMDGPU.store.output(float, i32) 29 30; FUNC-LABEL: {{^}}fsub_v2f32: 31; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z 32; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y 33 34; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 35; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 36define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { 37 %sub = fsub <2 x float> %a, %b 38 store <2 x float> %sub, <2 x float> addrspace(1)* %out, align 8 39 ret void 40} 41 42; FUNC-LABEL: {{^}}v_fsub_v4f32: 43; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 44; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 45; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 46; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} 47 48; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 49; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 50; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 51; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 52define void @v_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { 53 %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1 54 %a = load <4 x float>, <4 x float> addrspace(1)* %in, align 16 55 %b = load <4 x float>, <4 x float> addrspace(1)* %b_ptr, align 16 56 %result = fsub <4 x float> %a, %b 57 store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16 58 ret void 59} 60 61; FUNC-LABEL: {{^}}s_fsub_v4f32: 62; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 63; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 64; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 65; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 66; SI: s_endpgm 67define void @s_fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) { 68 %result = fsub <4 x float> %a, %b 69 store <4 x float> %result, <4 x float> addrspace(1)* %out, align 16 70 ret void 71} 72 73; FUNC-LABEL: {{^}}v_fneg_fsub_f32: 74; SI: v_subrev_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} 75; SI: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]] 76define void @v_fneg_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 77 %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 78 %a = load float, float addrspace(1)* %in, align 4 79 %b = load float, float addrspace(1)* %b_ptr, align 4 80 %result = fsub float %a, %b 81 %neg.result = fsub float -0.0, %result 82 store float %neg.result, float addrspace(1)* %out, align 4 83 ret void 84} 85 86; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_f32: 87; SI: v_subrev_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} 88; SI-NOT: xor 89define void @v_fneg_fsub_nsz_f32(float addrspace(1)* %out, float addrspace(1)* %in) { 90 %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 91 %a = load float, float addrspace(1)* %in, align 4 92 %b = load float, float addrspace(1)* %b_ptr, align 4 93 %result = fsub nsz float %a, %b 94 %neg.result = fsub float -0.0, %result 95 store float %neg.result, float addrspace(1)* %out, align 4 96 ret void 97} 98 99; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_attribute_f32: 100; SI: v_subrev_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} 101; SI-NOT: xor 102define void @v_fneg_fsub_nsz_attribute_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { 103 %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 104 %a = load float, float addrspace(1)* %in, align 4 105 %b = load float, float addrspace(1)* %b_ptr, align 4 106 %result = fsub float %a, %b 107 %neg.result = fsub float -0.0, %result 108 store float %neg.result, float addrspace(1)* %out, align 4 109 ret void 110} 111 112; For some reason the attribute has a string "true" or "false", so 113; make sure it is disabled and the fneg is not folded if it is not 114; "true". 115; FUNC-LABEL: {{^}}v_fneg_fsub_nsz_false_attribute_f32: 116; SI: v_subrev_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} 117; SI: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]] 118define void @v_fneg_fsub_nsz_false_attribute_f32(float addrspace(1)* %out, float addrspace(1)* %in) #1 { 119 %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 120 %a = load float, float addrspace(1)* %in, align 4 121 %b = load float, float addrspace(1)* %b_ptr, align 4 122 %result = fsub float %a, %b 123 %neg.result = fsub float -0.0, %result 124 store float %neg.result, float addrspace(1)* %out, align 4 125 ret void 126} 127 128attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" } 129attributes #1 = { nounwind "no-signed-zeros-fp-math"="false" } 130