1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SIVI %s 2; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=VI -check-prefix=SIVI %s 3; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX89 -check-prefix=GFX9 %s 4 5; GCN-LABEL: {{^}}fsub_f16: 6; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 7; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] 8; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 9; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 10; SI: v_subrev_f32_e32 v[[R_F32:[0-9]+]], v[[B_F32]], v[[A_F32]] 11; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 12; GFX89: v_subrev_f16_e32 v[[R_F16:[0-9]+]], v[[B_F16]], v[[A_F16]] 13; GCN: buffer_store_short v[[R_F16]] 14; GCN: s_endpgm 15define amdgpu_kernel void @fsub_f16( 16 half addrspace(1)* %r, 17 half addrspace(1)* %a, 18 half addrspace(1)* %b) { 19entry: 20 %a.val = load half, half addrspace(1)* %a 21 %b.val = load half, half addrspace(1)* %b 22 %r.val = fsub half %a.val, %b.val 23 store half %r.val, half addrspace(1)* %r 24 ret void 25} 26 27; GCN-LABEL: {{^}}fsub_f16_imm_a: 28; GCN: buffer_load_ushort v[[B_F16:[0-9]+]] 29; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] 30; SI: v_sub_f32_e32 v[[R_F32:[0-9]+]], 1.0, v[[B_F32]] 31; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 32; GFX89: v_sub_f16_e32 v[[R_F16:[0-9]+]], 1.0, v[[B_F16]] 33; GCN: buffer_store_short v[[R_F16]] 34; GCN: s_endpgm 35define amdgpu_kernel void @fsub_f16_imm_a( 36 half addrspace(1)* %r, 37 half addrspace(1)* %b) { 38entry: 39 %b.val = load half, half addrspace(1)* %b 40 %r.val = fsub half 1.0, %b.val 41 store half %r.val, half addrspace(1)* %r 42 ret void 43} 44 45; GCN-LABEL: {{^}}fsub_f16_imm_b: 46; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 47; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] 48; SI: v_add_f32_e32 v[[R_F32:[0-9]+]], -2.0, v[[A_F32]] 49; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] 50; GFX89: v_add_f16_e32 v[[R_F16:[0-9]+]], -2.0, v[[A_F16]] 51; GCN: buffer_store_short v[[R_F16]] 52; GCN: s_endpgm 53define amdgpu_kernel void @fsub_f16_imm_b( 54 half addrspace(1)* %r, 55 half addrspace(1)* %a) { 56entry: 57 %a.val = load half, half addrspace(1)* %a 58 %r.val = fsub half %a.val, 2.0 59 store half %r.val, half addrspace(1)* %r 60 ret void 61} 62 63; GCN-LABEL: {{^}}fsub_v2f16: 64; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] 65; GCN: buffer_load_dword v[[B_V2_F16:[0-9]+]] 66; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 67; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 68; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] 69; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 70 71; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] 72; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] 73; SI: v_subrev_f32_e32 v[[R_F32_0:[0-9]+]], v[[B_F32_0]], v[[A_F32_0]] 74; SI: v_subrev_f32_e32 v[[R_F32_1:[0-9]+]], v[[B_F32_1]], v[[A_F32_1]] 75; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] 76; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] 77; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 78; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] 79 80; VI-DAG: v_subrev_f16_e32 v[[R_F16_0:[0-9]+]], v[[B_V2_F16]], v[[A_V2_F16]] 81; VI-DAG: v_sub_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 82; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] 83 84; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] neg_lo:[0,1] neg_hi:[0,1] 85 86; GCN: buffer_store_dword v[[R_V2_F16]] 87; GCN: s_endpgm 88 89define amdgpu_kernel void @fsub_v2f16( 90 <2 x half> addrspace(1)* %r, 91 <2 x half> addrspace(1)* %a, 92 <2 x half> addrspace(1)* %b) { 93entry: 94 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 95 %b.val = load <2 x half>, <2 x half> addrspace(1)* %b 96 %r.val = fsub <2 x half> %a.val, %b.val 97 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 98 ret void 99} 100 101; GCN-LABEL: {{^}}fsub_v2f16_imm_a: 102; GCN-DAG: buffer_load_dword v[[B_V2_F16:[0-9]+]] 103 104; SI: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]] 105; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]] 106; SI: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]] 107; SI: v_sub_f32_e32 v[[R_F32_0:[0-9]+]], 1.0, v[[B_F32_0]] 108; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] 109; SI: v_sub_f32_e32 v[[R_F32_1:[0-9]+]], 2.0, v[[B_F32_1]] 110; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] 111; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 112; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] 113 114; VI-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 0x4000 115; VI-DAG: v_sub_f16_sdwa v[[R_F16_HI:[0-9]+]], [[CONST2]], v[[B_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 116; VI-DAG: v_sub_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[B_V2_F16]] 117; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] 118 119; GFX9: s_mov_b32 [[K:s[0-9]+]], 0x40003c00 120; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[B_V2_F16]], [[K]] neg_lo:[1,0] neg_hi:[1,0] 121 122; GCN: buffer_store_dword v[[R_V2_F16]] 123; GCN: s_endpgm 124 125define amdgpu_kernel void @fsub_v2f16_imm_a( 126 <2 x half> addrspace(1)* %r, 127 <2 x half> addrspace(1)* %b) { 128entry: 129 %b.val = load <2 x half>, <2 x half> addrspace(1)* %b 130 %r.val = fsub <2 x half> <half 1.0, half 2.0>, %b.val 131 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 132 ret void 133} 134 135; GCN-LABEL: {{^}}fsub_v2f16_imm_b: 136; GCN-DAG: buffer_load_dword v[[A_V2_F16:[0-9]+]] 137 138; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] 139; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] 140; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] 141; SI: v_add_f32_e32 v[[R_F32_0:[0-9]+]], -2.0, v[[A_F32_0]] 142; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] 143; SI: v_add_f32_e32 v[[R_F32_1:[0-9]+]], -1.0, v[[A_F32_1]] 144; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] 145; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 146; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] 147 148; VI-DAG: v_mov_b32_e32 [[CONSTM1:v[0-9]+]], 0xbc00 149; VI-DAG: v_add_f16_sdwa v[[R_F16_HI:[0-9]+]], v[[A_V2_F16]], [[CONSTM1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 150; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], -2.0, v[[A_V2_F16]] 151; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]] 152 153; GFX9: s_mov_b32 [[K:s[0-9]+]], 0xbc00c000 154; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], [[K]]{{$}} 155 156; GCN: buffer_store_dword v[[R_V2_F16]] 157; GCN: s_endpgm 158 159define amdgpu_kernel void @fsub_v2f16_imm_b( 160 <2 x half> addrspace(1)* %r, 161 <2 x half> addrspace(1)* %a) { 162entry: 163 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a 164 %r.val = fsub <2 x half> %a.val, <half 2.0, half 1.0> 165 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 166 ret void 167} 168