1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,SI 3; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,VI 4; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,GFX9 5; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,R600 6 7declare i32 @llvm.fshr.i32(i32, i32, i32) 8declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) 9declare <3 x i32> @llvm.fshr.v3i32(<3 x i32>, <3 x i32>, <3 x i32>) 10declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 11declare i16 @llvm.fshr.i16(i16, i16, i16) 12declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>) 13declare <3 x i16> @llvm.fshr.v3i16(<3 x i16>, <3 x i16>, <3 x i16>) 14declare <4 x i16> @llvm.fshr.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) 15declare i64 @llvm.fshr.i64(i64, i64, i64) 16declare <2 x i64> @llvm.fshr.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) 17declare i24 @llvm.fshr.i24(i24, i24, i24) 18declare <2 x i24> @llvm.fshr.v2i24(<2 x i24>, <2 x i24>, <2 x i24>) 19 20define amdgpu_kernel void @fshr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %z) { 21; SI-LABEL: fshr_i32: 22; SI: ; %bb.0: ; %entry 23; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 24; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb 25; SI-NEXT: s_mov_b32 s7, 0xf000 26; SI-NEXT: s_mov_b32 s6, -1 27; SI-NEXT: s_waitcnt lgkmcnt(0) 28; SI-NEXT: v_mov_b32_e32 v0, s1 29; SI-NEXT: v_mov_b32_e32 v1, s2 30; SI-NEXT: v_alignbit_b32 v0, s0, v0, v1 31; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 32; SI-NEXT: s_endpgm 33; 34; VI-LABEL: fshr_i32: 35; VI: ; %bb.0: ; %entry 36; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 37; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c 38; VI-NEXT: s_waitcnt lgkmcnt(0) 39; VI-NEXT: v_mov_b32_e32 v0, s1 40; VI-NEXT: v_mov_b32_e32 v1, s2 41; VI-NEXT: v_alignbit_b32 v2, s0, v0, v1 42; VI-NEXT: v_mov_b32_e32 v0, s4 43; VI-NEXT: v_mov_b32_e32 v1, s5 44; VI-NEXT: flat_store_dword v[0:1], v2 45; VI-NEXT: s_endpgm 46; 47; GFX9-LABEL: fshr_i32: 48; GFX9: ; %bb.0: ; %entry 49; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 50; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c 51; GFX9-NEXT: s_waitcnt lgkmcnt(0) 52; GFX9-NEXT: v_mov_b32_e32 v0, s1 53; GFX9-NEXT: v_mov_b32_e32 v1, s2 54; GFX9-NEXT: v_alignbit_b32 v2, s0, v0, v1 55; GFX9-NEXT: v_mov_b32_e32 v0, s4 56; GFX9-NEXT: v_mov_b32_e32 v1, s5 57; GFX9-NEXT: global_store_dword v[0:1], v2, off 58; GFX9-NEXT: s_endpgm 59; 60; R600-LABEL: fshr_i32: 61; R600: ; %bb.0: ; %entry 62; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] 63; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 64; R600-NEXT: CF_END 65; R600-NEXT: PAD 66; R600-NEXT: ALU clause starting at 4: 67; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 68; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) 69; R600-NEXT: BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X, 70entry: 71 %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z) 72 store i32 %0, i32 addrspace(1)* %in 73 ret void 74} 75 76define amdgpu_kernel void @fshr_i32_imm(i32 addrspace(1)* %in, i32 %x, i32 %y) { 77; SI-LABEL: fshr_i32_imm: 78; SI: ; %bb.0: ; %entry 79; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 80; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb 81; SI-NEXT: s_mov_b32 s7, 0xf000 82; SI-NEXT: s_mov_b32 s6, -1 83; SI-NEXT: s_waitcnt lgkmcnt(0) 84; SI-NEXT: v_mov_b32_e32 v0, s1 85; SI-NEXT: v_alignbit_b32 v0, s0, v0, 7 86; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 87; SI-NEXT: s_endpgm 88; 89; VI-LABEL: fshr_i32_imm: 90; VI: ; %bb.0: ; %entry 91; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 92; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 93; VI-NEXT: s_waitcnt lgkmcnt(0) 94; VI-NEXT: v_mov_b32_e32 v0, s1 95; VI-NEXT: v_alignbit_b32 v2, s0, v0, 7 96; VI-NEXT: v_mov_b32_e32 v0, s2 97; VI-NEXT: v_mov_b32_e32 v1, s3 98; VI-NEXT: flat_store_dword v[0:1], v2 99; VI-NEXT: s_endpgm 100; 101; GFX9-LABEL: fshr_i32_imm: 102; GFX9: ; %bb.0: ; %entry 103; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 104; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 105; GFX9-NEXT: s_waitcnt lgkmcnt(0) 106; GFX9-NEXT: v_mov_b32_e32 v0, s1 107; GFX9-NEXT: v_alignbit_b32 v2, s0, v0, 7 108; GFX9-NEXT: v_mov_b32_e32 v0, s2 109; GFX9-NEXT: v_mov_b32_e32 v1, s3 110; GFX9-NEXT: global_store_dword v[0:1], v2, off 111; GFX9-NEXT: s_endpgm 112; 113; R600-LABEL: fshr_i32_imm: 114; R600: ; %bb.0: ; %entry 115; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] 116; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 117; R600-NEXT: CF_END 118; R600-NEXT: PAD 119; R600-NEXT: ALU clause starting at 4: 120; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 121; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) 122; R600-NEXT: BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x, 123; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00) 124entry: 125 %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7) 126 store i32 %0, i32 addrspace(1)* %in 127 ret void 128} 129 130define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) { 131; SI-LABEL: fshr_v2i32: 132; SI: ; %bb.0: ; %entry 133; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 134; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb 135; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd 136; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xf 137; SI-NEXT: s_mov_b32 s7, 0xf000 138; SI-NEXT: s_mov_b32 s6, -1 139; SI-NEXT: s_waitcnt lgkmcnt(0) 140; SI-NEXT: v_mov_b32_e32 v0, s9 141; SI-NEXT: s_and_b32 s1, s1, 31 142; SI-NEXT: v_mov_b32_e32 v1, s1 143; SI-NEXT: s_and_b32 s0, s0, 31 144; SI-NEXT: v_alignbit_b32 v1, s3, v0, v1 145; SI-NEXT: v_cmp_eq_u32_e64 vcc, s1, 0 146; SI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc 147; SI-NEXT: v_mov_b32_e32 v0, s8 148; SI-NEXT: v_mov_b32_e32 v2, s0 149; SI-NEXT: v_alignbit_b32 v2, s2, v0, v2 150; SI-NEXT: v_cmp_eq_u32_e64 vcc, s0, 0 151; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 152; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 153; SI-NEXT: s_endpgm 154; 155; VI-LABEL: fshr_v2i32: 156; VI: ; %bb.0: ; %entry 157; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 158; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c 159; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34 160; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x3c 161; VI-NEXT: s_waitcnt lgkmcnt(0) 162; VI-NEXT: v_mov_b32_e32 v0, s7 163; VI-NEXT: s_and_b32 s1, s1, 31 164; VI-NEXT: v_mov_b32_e32 v1, s1 165; VI-NEXT: s_cmp_eq_u32 s1, 0 166; VI-NEXT: s_cselect_b64 vcc, -1, 0 167; VI-NEXT: s_and_b32 s0, s0, 31 168; VI-NEXT: v_alignbit_b32 v1, s5, v0, v1 169; VI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc 170; VI-NEXT: s_cmp_eq_u32 s0, 0 171; VI-NEXT: v_mov_b32_e32 v0, s6 172; VI-NEXT: v_mov_b32_e32 v2, s0 173; VI-NEXT: v_alignbit_b32 v2, s4, v0, v2 174; VI-NEXT: s_cselect_b64 vcc, -1, 0 175; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 176; VI-NEXT: v_mov_b32_e32 v2, s2 177; VI-NEXT: v_mov_b32_e32 v3, s3 178; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] 179; VI-NEXT: s_endpgm 180; 181; GFX9-LABEL: fshr_v2i32: 182; GFX9: ; %bb.0: ; %entry 183; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 184; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c 185; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x34 186; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x3c 187; GFX9-NEXT: s_waitcnt lgkmcnt(0) 188; GFX9-NEXT: v_mov_b32_e32 v0, s7 189; GFX9-NEXT: s_and_b32 s1, s1, 31 190; GFX9-NEXT: v_mov_b32_e32 v1, s1 191; GFX9-NEXT: s_cmp_eq_u32 s1, 0 192; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 193; GFX9-NEXT: s_and_b32 s0, s0, 31 194; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, v1 195; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc 196; GFX9-NEXT: s_cmp_eq_u32 s0, 0 197; GFX9-NEXT: v_mov_b32_e32 v0, s6 198; GFX9-NEXT: v_mov_b32_e32 v2, s0 199; GFX9-NEXT: v_alignbit_b32 v2, s4, v0, v2 200; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 201; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 202; GFX9-NEXT: v_mov_b32_e32 v2, s2 203; GFX9-NEXT: v_mov_b32_e32 v3, s3 204; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off 205; GFX9-NEXT: s_endpgm 206; 207; R600-LABEL: fshr_v2i32: 208; R600: ; %bb.0: ; %entry 209; R600-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[] 210; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 211; R600-NEXT: CF_END 212; R600-NEXT: PAD 213; R600-NEXT: ALU clause starting at 4: 214; R600-NEXT: AND_INT * T0.W, KC0[4].X, literal.x, 215; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00) 216; R600-NEXT: BIT_ALIGN_INT T1.W, KC0[3].X, KC0[3].Z, PV.W, 217; R600-NEXT: SETE_INT * T0.W, PV.W, 0.0, 218; R600-NEXT: CNDE_INT T0.Y, PS, PV.W, KC0[3].Z, 219; R600-NEXT: AND_INT * T0.W, KC0[3].W, literal.x, 220; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00) 221; R600-NEXT: BIT_ALIGN_INT T1.W, KC0[2].W, KC0[3].Y, PV.W, 222; R600-NEXT: SETE_INT * T0.W, PV.W, 0.0, 223; R600-NEXT: CNDE_INT T0.X, PS, PV.W, KC0[3].Y, 224; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 225; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) 226entry: 227 %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z) 228 store <2 x i32> %0, <2 x i32> addrspace(1)* %in 229 ret void 230} 231 232define amdgpu_kernel void @fshr_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) { 233; SI-LABEL: fshr_v2i32_imm: 234; SI: ; %bb.0: ; %entry 235; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 236; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb 237; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd 238; SI-NEXT: s_mov_b32 s7, 0xf000 239; SI-NEXT: s_mov_b32 s6, -1 240; SI-NEXT: s_waitcnt lgkmcnt(0) 241; SI-NEXT: v_mov_b32_e32 v0, s1 242; SI-NEXT: v_alignbit_b32 v1, s3, v0, 9 243; SI-NEXT: v_mov_b32_e32 v0, s0 244; SI-NEXT: v_alignbit_b32 v0, s2, v0, 7 245; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 246; SI-NEXT: s_endpgm 247; 248; VI-LABEL: fshr_v2i32_imm: 249; VI: ; %bb.0: ; %entry 250; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 251; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c 252; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 253; VI-NEXT: s_waitcnt lgkmcnt(0) 254; VI-NEXT: v_mov_b32_e32 v0, s1 255; VI-NEXT: v_mov_b32_e32 v2, s0 256; VI-NEXT: v_alignbit_b32 v1, s5, v0, 9 257; VI-NEXT: v_alignbit_b32 v0, s4, v2, 7 258; VI-NEXT: v_mov_b32_e32 v2, s2 259; VI-NEXT: v_mov_b32_e32 v3, s3 260; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] 261; VI-NEXT: s_endpgm 262; 263; GFX9-LABEL: fshr_v2i32_imm: 264; GFX9: ; %bb.0: ; %entry 265; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 266; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c 267; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 268; GFX9-NEXT: s_waitcnt lgkmcnt(0) 269; GFX9-NEXT: v_mov_b32_e32 v0, s1 270; GFX9-NEXT: v_mov_b32_e32 v2, s0 271; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, 9 272; GFX9-NEXT: v_alignbit_b32 v0, s4, v2, 7 273; GFX9-NEXT: v_mov_b32_e32 v2, s2 274; GFX9-NEXT: v_mov_b32_e32 v3, s3 275; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off 276; GFX9-NEXT: s_endpgm 277; 278; R600-LABEL: fshr_v2i32_imm: 279; R600: ; %bb.0: ; %entry 280; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] 281; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 282; R600-NEXT: CF_END 283; R600-NEXT: PAD 284; R600-NEXT: ALU clause starting at 4: 285; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x, 286; R600-NEXT: 9(1.261169e-44), 0(0.000000e+00) 287; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x, 288; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00) 289; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 290; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) 291entry: 292 %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>) 293 store <2 x i32> %0, <2 x i32> addrspace(1)* %in 294 ret void 295} 296 297define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { 298; SI-LABEL: fshr_v4i32: 299; SI: ; %bb.0: ; %entry 300; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 301; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd 302; SI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x11 303; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x15 304; SI-NEXT: s_mov_b32 s7, 0xf000 305; SI-NEXT: s_mov_b32 s6, -1 306; SI-NEXT: s_waitcnt lgkmcnt(0) 307; SI-NEXT: v_mov_b32_e32 v0, s15 308; SI-NEXT: s_and_b32 s3, s3, 31 309; SI-NEXT: v_mov_b32_e32 v1, s3 310; SI-NEXT: v_alignbit_b32 v1, s11, v0, v1 311; SI-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 312; SI-NEXT: s_and_b32 s2, s2, 31 313; SI-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc 314; SI-NEXT: v_mov_b32_e32 v0, s14 315; SI-NEXT: v_mov_b32_e32 v1, s2 316; SI-NEXT: v_alignbit_b32 v1, s10, v0, v1 317; SI-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0 318; SI-NEXT: s_and_b32 s1, s1, 31 319; SI-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc 320; SI-NEXT: v_mov_b32_e32 v0, s13 321; SI-NEXT: v_mov_b32_e32 v1, s1 322; SI-NEXT: s_and_b32 s0, s0, 31 323; SI-NEXT: v_alignbit_b32 v1, s9, v0, v1 324; SI-NEXT: v_cmp_eq_u32_e64 vcc, s1, 0 325; SI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc 326; SI-NEXT: v_mov_b32_e32 v0, s12 327; SI-NEXT: v_mov_b32_e32 v4, s0 328; SI-NEXT: v_alignbit_b32 v4, s8, v0, v4 329; SI-NEXT: v_cmp_eq_u32_e64 vcc, s0, 0 330; SI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 331; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 332; SI-NEXT: s_endpgm 333; 334; VI-LABEL: fshr_v4i32: 335; VI: ; %bb.0: ; %entry 336; VI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x24 337; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 338; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x44 339; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x54 340; VI-NEXT: s_waitcnt lgkmcnt(0) 341; VI-NEXT: v_mov_b32_e32 v0, s11 342; VI-NEXT: s_and_b32 s3, s3, 31 343; VI-NEXT: v_mov_b32_e32 v1, s3 344; VI-NEXT: s_cmp_eq_u32 s3, 0 345; VI-NEXT: s_cselect_b64 vcc, -1, 0 346; VI-NEXT: s_and_b32 s2, s2, 31 347; VI-NEXT: v_alignbit_b32 v1, s7, v0, v1 348; VI-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc 349; VI-NEXT: s_cmp_eq_u32 s2, 0 350; VI-NEXT: v_mov_b32_e32 v0, s10 351; VI-NEXT: v_mov_b32_e32 v1, s2 352; VI-NEXT: s_cselect_b64 vcc, -1, 0 353; VI-NEXT: s_and_b32 s1, s1, 31 354; VI-NEXT: v_alignbit_b32 v1, s6, v0, v1 355; VI-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc 356; VI-NEXT: s_cmp_eq_u32 s1, 0 357; VI-NEXT: v_mov_b32_e32 v0, s9 358; VI-NEXT: v_mov_b32_e32 v1, s1 359; VI-NEXT: s_cselect_b64 vcc, -1, 0 360; VI-NEXT: s_and_b32 s0, s0, 31 361; VI-NEXT: v_alignbit_b32 v1, s5, v0, v1 362; VI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc 363; VI-NEXT: s_cmp_eq_u32 s0, 0 364; VI-NEXT: v_mov_b32_e32 v0, s8 365; VI-NEXT: v_mov_b32_e32 v4, s0 366; VI-NEXT: v_alignbit_b32 v4, s4, v0, v4 367; VI-NEXT: s_cselect_b64 vcc, -1, 0 368; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 369; VI-NEXT: v_mov_b32_e32 v4, s12 370; VI-NEXT: v_mov_b32_e32 v5, s13 371; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] 372; VI-NEXT: s_endpgm 373; 374; GFX9-LABEL: fshr_v4i32: 375; GFX9: ; %bb.0: ; %entry 376; GFX9-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x24 377; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 378; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x44 379; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x54 380; GFX9-NEXT: s_waitcnt lgkmcnt(0) 381; GFX9-NEXT: v_mov_b32_e32 v0, s11 382; GFX9-NEXT: s_and_b32 s3, s3, 31 383; GFX9-NEXT: v_mov_b32_e32 v1, s3 384; GFX9-NEXT: s_cmp_eq_u32 s3, 0 385; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 386; GFX9-NEXT: s_and_b32 s2, s2, 31 387; GFX9-NEXT: v_alignbit_b32 v1, s7, v0, v1 388; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc 389; GFX9-NEXT: s_cmp_eq_u32 s2, 0 390; GFX9-NEXT: v_mov_b32_e32 v0, s10 391; GFX9-NEXT: v_mov_b32_e32 v1, s2 392; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 393; GFX9-NEXT: s_and_b32 s1, s1, 31 394; GFX9-NEXT: v_alignbit_b32 v1, s6, v0, v1 395; GFX9-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc 396; GFX9-NEXT: s_cmp_eq_u32 s1, 0 397; GFX9-NEXT: v_mov_b32_e32 v0, s9 398; GFX9-NEXT: v_mov_b32_e32 v1, s1 399; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 400; GFX9-NEXT: s_and_b32 s0, s0, 31 401; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, v1 402; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc 403; GFX9-NEXT: s_cmp_eq_u32 s0, 0 404; GFX9-NEXT: v_mov_b32_e32 v0, s8 405; GFX9-NEXT: v_mov_b32_e32 v4, s0 406; GFX9-NEXT: v_alignbit_b32 v4, s4, v0, v4 407; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 408; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 409; GFX9-NEXT: v_mov_b32_e32 v4, s12 410; GFX9-NEXT: v_mov_b32_e32 v5, s13 411; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off 412; GFX9-NEXT: s_endpgm 413; 414; R600-LABEL: fshr_v4i32: 415; R600: ; %bb.0: ; %entry 416; R600-NEXT: ALU 20, @4, KC0[CB0:0-32], KC1[] 417; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1 418; R600-NEXT: CF_END 419; R600-NEXT: PAD 420; R600-NEXT: ALU clause starting at 4: 421; R600-NEXT: AND_INT T0.W, KC0[5].Z, literal.x, 422; R600-NEXT: AND_INT * T1.W, KC0[6].X, literal.x, 423; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00) 424; R600-NEXT: SETE_INT T0.Z, PS, 0.0, 425; R600-NEXT: BIT_ALIGN_INT * T1.W, KC0[4].X, KC0[5].X, PS, 426; R600-NEXT: AND_INT * T2.W, KC0[5].W, literal.x, 427; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00) 428; R600-NEXT: SETE_INT T1.Z, PV.W, 0.0, 429; R600-NEXT: BIT_ALIGN_INT * T2.W, KC0[3].W, KC0[4].W, PV.W, 430; R600-NEXT: CNDE_INT * T1.W, T0.Z, T1.W, KC0[5].X, 431; R600-NEXT: CNDE_INT T1.Z, T1.Z, T2.W, KC0[4].W, 432; R600-NEXT: BIT_ALIGN_INT T2.W, KC0[3].Z, KC0[4].Z, T0.W, 433; R600-NEXT: SETE_INT * T0.W, T0.W, 0.0, 434; R600-NEXT: CNDE_INT T1.Y, PS, PV.W, KC0[4].Z, 435; R600-NEXT: AND_INT * T0.W, KC0[5].Y, literal.x, 436; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00) 437; R600-NEXT: BIT_ALIGN_INT T2.W, KC0[3].Y, KC0[4].Y, PV.W, 438; R600-NEXT: SETE_INT * T0.W, PV.W, 0.0, 439; R600-NEXT: CNDE_INT T1.X, PS, PV.W, KC0[4].Y, 440; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 441; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) 442entry: 443 %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) 444 store <4 x i32> %0, <4 x i32> addrspace(1)* %in 445 ret void 446} 447 448define amdgpu_kernel void @fshr_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) { 449; SI-LABEL: fshr_v4i32_imm: 450; SI: ; %bb.0: ; %entry 451; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 452; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd 453; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 454; SI-NEXT: s_mov_b32 s7, 0xf000 455; SI-NEXT: s_mov_b32 s6, -1 456; SI-NEXT: s_waitcnt lgkmcnt(0) 457; SI-NEXT: v_mov_b32_e32 v0, s3 458; SI-NEXT: v_alignbit_b32 v3, s11, v0, 1 459; SI-NEXT: v_mov_b32_e32 v0, s2 460; SI-NEXT: v_alignbit_b32 v2, s10, v0, 9 461; SI-NEXT: v_mov_b32_e32 v0, s1 462; SI-NEXT: v_alignbit_b32 v1, s9, v0, 7 463; SI-NEXT: v_mov_b32_e32 v0, s0 464; SI-NEXT: v_alignbit_b32 v0, s8, v0, 1 465; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 466; SI-NEXT: s_endpgm 467; 468; VI-LABEL: fshr_v4i32_imm: 469; VI: ; %bb.0: ; %entry 470; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24 471; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 472; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x44 473; VI-NEXT: s_waitcnt lgkmcnt(0) 474; VI-NEXT: v_mov_b32_e32 v4, s8 475; VI-NEXT: v_mov_b32_e32 v5, s9 476; VI-NEXT: v_mov_b32_e32 v0, s3 477; VI-NEXT: v_mov_b32_e32 v1, s2 478; VI-NEXT: v_alignbit_b32 v3, s7, v0, 1 479; VI-NEXT: v_mov_b32_e32 v0, s1 480; VI-NEXT: v_alignbit_b32 v2, s6, v1, 9 481; VI-NEXT: v_alignbit_b32 v1, s5, v0, 7 482; VI-NEXT: v_mov_b32_e32 v0, s0 483; VI-NEXT: v_alignbit_b32 v0, s4, v0, 1 484; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] 485; VI-NEXT: s_endpgm 486; 487; GFX9-LABEL: fshr_v4i32_imm: 488; GFX9: ; %bb.0: ; %entry 489; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24 490; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 491; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x44 492; GFX9-NEXT: s_waitcnt lgkmcnt(0) 493; GFX9-NEXT: v_mov_b32_e32 v4, s8 494; GFX9-NEXT: v_mov_b32_e32 v5, s9 495; GFX9-NEXT: v_mov_b32_e32 v0, s3 496; GFX9-NEXT: v_mov_b32_e32 v1, s2 497; GFX9-NEXT: v_alignbit_b32 v3, s7, v0, 1 498; GFX9-NEXT: v_mov_b32_e32 v0, s1 499; GFX9-NEXT: v_alignbit_b32 v2, s6, v1, 9 500; GFX9-NEXT: v_alignbit_b32 v1, s5, v0, 7 501; GFX9-NEXT: v_mov_b32_e32 v0, s0 502; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, 1 503; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off 504; GFX9-NEXT: s_endpgm 505; 506; R600-LABEL: fshr_v4i32_imm: 507; R600: ; %bb.0: ; %entry 508; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 509; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 510; R600-NEXT: CF_END 511; R600-NEXT: PAD 512; R600-NEXT: ALU clause starting at 4: 513; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1, 514; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x, 515; R600-NEXT: 9(1.261169e-44), 0(0.000000e+00) 516; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x, 517; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00) 518; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, 1, 519; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 520; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00) 521entry: 522 %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>) 523 store <4 x i32> %0, <4 x i32> addrspace(1)* %in 524 ret void 525} 526 527define i32 @v_fshr_i32(i32 %src0, i32 %src1, i32 %src2) { 528; GFX89-LABEL: v_fshr_i32: 529; GFX89: ; %bb.0: 530; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 531; GFX89-NEXT: v_alignbit_b32 v0, v0, v1, v2 532; GFX89-NEXT: s_setpc_b64 s[30:31] 533; 534; R600-LABEL: v_fshr_i32: 535; R600: ; %bb.0: 536; R600-NEXT: CF_END 537; R600-NEXT: PAD 538 %ret = call i32 @llvm.fshr.i32(i32 %src0, i32 %src1, i32 %src2) 539 ret i32 %ret 540} 541 542define <2 x i32> @v_fshr_v2i32(<2 x i32> %src0, <2 x i32> %src1, <2 x i32> %src2) { 543; GFX89-LABEL: v_fshr_v2i32: 544; GFX89: ; %bb.0: 545; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 546; GFX89-NEXT: v_and_b32_e32 v4, 31, v4 547; GFX89-NEXT: v_alignbit_b32 v0, v0, v2, v4 548; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 549; GFX89-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 550; GFX89-NEXT: v_and_b32_e32 v2, 31, v5 551; GFX89-NEXT: v_alignbit_b32 v1, v1, v3, v2 552; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 553; GFX89-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 554; GFX89-NEXT: s_setpc_b64 s[30:31] 555; 556; R600-LABEL: v_fshr_v2i32: 557; R600: ; %bb.0: 558; R600-NEXT: CF_END 559; R600-NEXT: PAD 560 %ret = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %src0, <2 x i32> %src1, <2 x i32> %src2) 561 ret <2 x i32> %ret 562} 563 564define <3 x i32> @v_fshr_v3i32(<3 x i32> %src0, <3 x i32> %src1, <3 x i32> %src2) { 565; GFX89-LABEL: v_fshr_v3i32: 566; GFX89: ; %bb.0: 567; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 568; GFX89-NEXT: v_and_b32_e32 v6, 31, v6 569; GFX89-NEXT: v_alignbit_b32 v0, v0, v3, v6 570; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 571; GFX89-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 572; GFX89-NEXT: v_and_b32_e32 v3, 31, v7 573; GFX89-NEXT: v_alignbit_b32 v1, v1, v4, v3 574; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 575; GFX89-NEXT: v_and_b32_e32 v3, 31, v8 576; GFX89-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc 577; GFX89-NEXT: v_alignbit_b32 v2, v2, v5, v3 578; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 579; GFX89-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc 580; GFX89-NEXT: s_setpc_b64 s[30:31] 581; 582; R600-LABEL: v_fshr_v3i32: 583; R600: ; %bb.0: 584; R600-NEXT: CF_END 585; R600-NEXT: PAD 586 %ret = call <3 x i32> @llvm.fshr.v3i32(<3 x i32> %src0, <3 x i32> %src1, <3 x i32> %src2) 587 ret <3 x i32> %ret 588} 589 590define <4 x i32> @v_fshr_v4i32(<4 x i32> %src0, <4 x i32> %src1, <4 x i32> %src2) { 591; GFX89-LABEL: v_fshr_v4i32: 592; GFX89: ; %bb.0: 593; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 594; GFX89-NEXT: v_and_b32_e32 v8, 31, v8 595; GFX89-NEXT: v_alignbit_b32 v0, v0, v4, v8 596; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8 597; GFX89-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 598; GFX89-NEXT: v_and_b32_e32 v4, 31, v9 599; GFX89-NEXT: v_alignbit_b32 v1, v1, v5, v4 600; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 601; GFX89-NEXT: v_and_b32_e32 v4, 31, v10 602; GFX89-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc 603; GFX89-NEXT: v_alignbit_b32 v2, v2, v6, v4 604; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 605; GFX89-NEXT: v_and_b32_e32 v4, 31, v11 606; GFX89-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc 607; GFX89-NEXT: v_alignbit_b32 v3, v3, v7, v4 608; GFX89-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 609; GFX89-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 610; GFX89-NEXT: s_setpc_b64 s[30:31] 611; 612; R600-LABEL: v_fshr_v4i32: 613; R600: ; %bb.0: 614; R600-NEXT: CF_END 615; R600-NEXT: PAD 616 %ret = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %src0, <4 x i32> %src1, <4 x i32> %src2) 617 ret <4 x i32> %ret 618} 619 620define i16 @v_fshr_i16(i16 %src0, i16 %src1, i16 %src2) { 621; SI-LABEL: v_fshr_i16: 622; SI: ; %bb.0: 623; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 624; SI-NEXT: v_and_b32_e32 v2, 15, v2 625; SI-NEXT: v_and_b32_e32 v3, 0xffff, v1 626; SI-NEXT: v_sub_i32_e32 v4, vcc, 16, v2 627; SI-NEXT: v_lshr_b32_e32 v3, v3, v2 628; SI-NEXT: v_lshl_b32_e32 v0, v0, v4 629; SI-NEXT: v_or_b32_e32 v0, v0, v3 630; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 631; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 632; SI-NEXT: s_setpc_b64 s[30:31] 633; 634; VI-LABEL: v_fshr_i16: 635; VI: ; %bb.0: 636; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 637; VI-NEXT: v_and_b32_e32 v2, 15, v2 638; VI-NEXT: v_sub_u16_e32 v4, 16, v2 639; VI-NEXT: v_lshrrev_b16_e32 v3, v2, v1 640; VI-NEXT: v_lshlrev_b16_e32 v0, v4, v0 641; VI-NEXT: v_or_b32_e32 v0, v0, v3 642; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 643; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 644; VI-NEXT: s_setpc_b64 s[30:31] 645; 646; GFX9-LABEL: v_fshr_i16: 647; GFX9: ; %bb.0: 648; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 649; GFX9-NEXT: v_and_b32_e32 v2, 15, v2 650; GFX9-NEXT: v_sub_u16_e32 v4, 16, v2 651; GFX9-NEXT: v_lshrrev_b16_e32 v3, v2, v1 652; GFX9-NEXT: v_lshlrev_b16_e32 v0, v4, v0 653; GFX9-NEXT: v_or_b32_e32 v0, v0, v3 654; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 655; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 656; GFX9-NEXT: s_setpc_b64 s[30:31] 657; 658; R600-LABEL: v_fshr_i16: 659; R600: ; %bb.0: 660; R600-NEXT: CF_END 661; R600-NEXT: PAD 662 %ret = call i16 @llvm.fshr.i16(i16 %src0, i16 %src1, i16 %src2) 663 ret i16 %ret 664} 665 666define <2 x i16> @v_fshr_v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2) { 667; SI-LABEL: v_fshr_v2i16: 668; SI: ; %bb.0: 669; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 670; SI-NEXT: s_mov_b32 s4, 0xffff 671; SI-NEXT: v_and_b32_e32 v5, 15, v5 672; SI-NEXT: v_and_b32_e32 v7, s4, v3 673; SI-NEXT: v_sub_i32_e32 v8, vcc, 16, v5 674; SI-NEXT: v_lshr_b32_e32 v7, v7, v5 675; SI-NEXT: v_lshl_b32_e32 v1, v1, v8 676; SI-NEXT: v_or_b32_e32 v1, v1, v7 677; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 678; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 679; SI-NEXT: v_and_b32_e32 v3, 15, v4 680; SI-NEXT: v_sub_i32_e32 v5, vcc, 16, v3 681; SI-NEXT: v_and_b32_e32 v6, s4, v2 682; SI-NEXT: v_lshr_b32_e32 v4, v6, v3 683; SI-NEXT: v_lshl_b32_e32 v0, v0, v5 684; SI-NEXT: v_or_b32_e32 v0, v0, v4 685; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 686; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 687; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 688; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 689; SI-NEXT: v_or_b32_e32 v0, v0, v1 690; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 691; SI-NEXT: s_setpc_b64 s[30:31] 692; 693; VI-LABEL: v_fshr_v2i16: 694; VI: ; %bb.0: 695; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 696; VI-NEXT: v_and_b32_e32 v3, 0xf000f, v2 697; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1 698; VI-NEXT: v_bfe_u32 v2, v2, 16, 4 699; VI-NEXT: v_lshrrev_b16_e32 v4, v3, v1 700; VI-NEXT: v_lshrrev_b16_sdwa v6, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD 701; VI-NEXT: v_or_b32_e32 v4, v4, v6 702; VI-NEXT: v_sub_u16_e32 v6, 16, v2 703; VI-NEXT: v_sub_u16_e32 v7, 16, v3 704; VI-NEXT: v_lshlrev_b16_sdwa v6, v6, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 705; VI-NEXT: v_lshlrev_b16_e32 v0, v7, v0 706; VI-NEXT: v_or_b32_e32 v0, v0, v6 707; VI-NEXT: v_or_b32_e32 v0, v0, v4 708; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 709; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 710; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 711; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 712; VI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc 713; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 714; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 715; VI-NEXT: s_setpc_b64 s[30:31] 716; 717; GFX9-LABEL: v_fshr_v2i16: 718; GFX9: ; %bb.0: 719; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 720; GFX9-NEXT: v_and_b32_e32 v2, 0xf000f, v2 721; GFX9-NEXT: v_pk_sub_i16 v4, 16, v2 op_sel_hi:[0,1] 722; GFX9-NEXT: v_pk_lshlrev_b16 v0, v4, v0 723; GFX9-NEXT: v_pk_lshrrev_b16 v3, v2, v1 724; GFX9-NEXT: v_or_b32_e32 v0, v0, v3 725; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 726; GFX9-NEXT: v_mov_b32_e32 v4, 0 727; GFX9-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc 728; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 729; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 730; GFX9-NEXT: v_cmp_eq_u16_sdwa s[4:5], v2, v4 src0_sel:WORD_1 src1_sel:DWORD 731; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5] 732; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v3 733; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1 734; GFX9-NEXT: s_setpc_b64 s[30:31] 735; 736; R600-LABEL: v_fshr_v2i16: 737; R600: ; %bb.0: 738; R600-NEXT: CF_END 739; R600-NEXT: PAD 740 %ret = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2) 741 ret <2 x i16> %ret 742} 743 744define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2) { 745; SI-LABEL: v_fshr_v3i16: 746; SI: ; %bb.0: 747; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 748; SI-NEXT: s_mov_b32 s4, 0xffff 749; SI-NEXT: v_and_b32_e32 v7, 15, v7 750; SI-NEXT: v_and_b32_e32 v12, s4, v4 751; SI-NEXT: v_sub_i32_e32 v13, vcc, 16, v7 752; SI-NEXT: v_lshr_b32_e32 v12, v12, v7 753; SI-NEXT: v_lshl_b32_e32 v1, v1, v13 754; SI-NEXT: v_or_b32_e32 v1, v1, v12 755; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7 756; SI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc 757; SI-NEXT: v_and_b32_e32 v4, 15, v6 758; SI-NEXT: v_sub_i32_e32 v7, vcc, 16, v4 759; SI-NEXT: v_and_b32_e32 v11, s4, v3 760; SI-NEXT: v_lshr_b32_e32 v6, v11, v4 761; SI-NEXT: v_lshl_b32_e32 v0, v0, v7 762; SI-NEXT: v_or_b32_e32 v0, v0, v6 763; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 764; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 765; SI-NEXT: v_and_b32_e32 v3, 15, v8 766; SI-NEXT: v_sub_i32_e32 v6, vcc, 16, v3 767; SI-NEXT: v_and_b32_e32 v10, s4, v5 768; SI-NEXT: v_lshr_b32_e32 v4, v10, v3 769; SI-NEXT: v_lshl_b32_e32 v2, v2, v6 770; SI-NEXT: v_mov_b32_e32 v9, 0xffff 771; SI-NEXT: v_or_b32_e32 v2, v2, v4 772; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 773; SI-NEXT: v_cndmask_b32_e32 v3, v2, v5, vcc 774; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 775; SI-NEXT: v_and_b32_e32 v0, v9, v0 776; SI-NEXT: v_or_b32_e32 v0, v0, v1 777; SI-NEXT: v_and_b32_e32 v2, v9, v3 778; SI-NEXT: v_alignbit_b32 v1, v3, v1, 16 779; SI-NEXT: s_setpc_b64 s[30:31] 780; 781; VI-LABEL: v_fshr_v3i16: 782; VI: ; %bb.0: 783; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 784; VI-NEXT: v_mov_b32_e32 v6, 15 785; VI-NEXT: v_and_b32_sdwa v6, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 786; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v2 787; VI-NEXT: v_lshrrev_b16_e32 v8, v6, v7 788; VI-NEXT: v_sub_u16_e32 v6, 16, v6 789; VI-NEXT: v_lshlrev_b16_sdwa v6, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 790; VI-NEXT: v_or_b32_e32 v6, v6, v8 791; VI-NEXT: v_bfe_u32 v8, v4, 16, 4 792; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v8 793; VI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc 794; VI-NEXT: v_and_b32_e32 v7, 15, v5 795; VI-NEXT: v_lshrrev_b16_e32 v8, v7, v3 796; VI-NEXT: v_sub_u16_e32 v7, 16, v7 797; VI-NEXT: v_lshlrev_b16_e32 v1, v7, v1 798; VI-NEXT: v_and_b32_e32 v5, 15, v5 799; VI-NEXT: v_or_b32_e32 v1, v1, v8 800; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 801; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 802; VI-NEXT: v_and_b32_e32 v3, 15, v4 803; VI-NEXT: v_lshrrev_b16_e32 v5, v3, v2 804; VI-NEXT: v_sub_u16_e32 v3, 16, v3 805; VI-NEXT: v_lshlrev_b16_e32 v0, v3, v0 806; VI-NEXT: v_and_b32_e32 v3, 0xf000f, v4 807; VI-NEXT: v_or_b32_e32 v0, v0, v5 808; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 809; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 810; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6 811; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 812; VI-NEXT: s_setpc_b64 s[30:31] 813; 814; GFX9-LABEL: v_fshr_v3i16: 815; GFX9: ; %bb.0: 816; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 817; GFX9-NEXT: v_mov_b32_e32 v7, 15 818; GFX9-NEXT: v_and_b32_e32 v6, 15, v4 819; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff 820; GFX9-NEXT: v_and_b32_sdwa v7, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 821; GFX9-NEXT: v_and_b32_e32 v6, v8, v6 822; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6 823; GFX9-NEXT: v_pk_lshrrev_b16 v7, v6, v2 824; GFX9-NEXT: v_pk_sub_i16 v6, 16, v6 op_sel_hi:[0,1] 825; GFX9-NEXT: s_mov_b32 s6, 0xf000f 826; GFX9-NEXT: v_pk_lshlrev_b16 v0, v6, v0 827; GFX9-NEXT: v_and_b32_e32 v4, s6, v4 828; GFX9-NEXT: v_or_b32_e32 v0, v0, v7 829; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4 830; GFX9-NEXT: v_mov_b32_e32 v7, 0 831; GFX9-NEXT: v_cndmask_b32_e32 v6, v0, v2, vcc 832; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 833; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 834; GFX9-NEXT: v_cmp_eq_u16_sdwa s[4:5], v4, v7 src0_sel:WORD_1 src1_sel:DWORD 835; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] 836; GFX9-NEXT: v_and_b32_e32 v2, 15, v5 837; GFX9-NEXT: v_and_b32_e32 v2, v8, v2 838; GFX9-NEXT: v_pk_lshrrev_b16 v4, v2, v3 839; GFX9-NEXT: v_pk_sub_i16 v2, 16, v2 840; GFX9-NEXT: v_pk_lshlrev_b16 v1, v2, v1 841; GFX9-NEXT: v_and_b32_e32 v2, s6, v5 842; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2 843; GFX9-NEXT: v_or_b32_e32 v1, v1, v4 844; GFX9-NEXT: v_and_b32_e32 v2, v8, v6 845; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 846; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v2 847; GFX9-NEXT: s_setpc_b64 s[30:31] 848; 849; R600-LABEL: v_fshr_v3i16: 850; R600: ; %bb.0: 851; R600-NEXT: CF_END 852; R600-NEXT: PAD 853 %ret = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2) 854 ret <3 x i16> %ret 855} 856 857define <4 x i16> @v_fshr_v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2) { 858; SI-LABEL: v_fshr_v4i16: 859; SI: ; %bb.0: 860; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 861; SI-NEXT: s_mov_b32 s4, 0xffff 862; SI-NEXT: v_and_b32_e32 v9, 15, v9 863; SI-NEXT: v_and_b32_e32 v16, s4, v5 864; SI-NEXT: v_sub_i32_e32 v17, vcc, 16, v9 865; SI-NEXT: v_lshr_b32_e32 v16, v16, v9 866; SI-NEXT: v_lshl_b32_e32 v1, v1, v17 867; SI-NEXT: v_or_b32_e32 v1, v1, v16 868; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 869; SI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc 870; SI-NEXT: v_and_b32_e32 v5, 15, v8 871; SI-NEXT: v_sub_i32_e32 v9, vcc, 16, v5 872; SI-NEXT: v_and_b32_e32 v15, s4, v4 873; SI-NEXT: v_lshr_b32_e32 v8, v15, v5 874; SI-NEXT: v_lshl_b32_e32 v0, v0, v9 875; SI-NEXT: v_or_b32_e32 v0, v0, v8 876; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 877; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 878; SI-NEXT: v_and_b32_e32 v4, 15, v11 879; SI-NEXT: v_sub_i32_e32 v8, vcc, 16, v4 880; SI-NEXT: v_and_b32_e32 v14, s4, v7 881; SI-NEXT: v_lshr_b32_e32 v5, v14, v4 882; SI-NEXT: v_lshl_b32_e32 v3, v3, v8 883; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 884; SI-NEXT: v_or_b32_e32 v3, v3, v5 885; SI-NEXT: v_and_b32_e32 v4, 15, v10 886; SI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 887; SI-NEXT: v_sub_i32_e32 v7, vcc, 16, v4 888; SI-NEXT: v_and_b32_e32 v13, s4, v6 889; SI-NEXT: v_lshr_b32_e32 v5, v13, v4 890; SI-NEXT: v_lshl_b32_e32 v2, v2, v7 891; SI-NEXT: v_or_b32_e32 v2, v2, v5 892; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 893; SI-NEXT: v_mov_b32_e32 v12, 0xffff 894; SI-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc 895; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 896; SI-NEXT: v_and_b32_e32 v2, v12, v2 897; SI-NEXT: v_or_b32_e32 v2, v2, v3 898; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 899; SI-NEXT: v_and_b32_e32 v0, v12, v0 900; SI-NEXT: v_or_b32_e32 v0, v0, v1 901; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 902; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 903; SI-NEXT: s_setpc_b64 s[30:31] 904; 905; VI-LABEL: v_fshr_v4i16: 906; VI: ; %bb.0: 907; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 908; VI-NEXT: v_mov_b32_e32 v6, 15 909; VI-NEXT: v_and_b32_sdwa v7, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 910; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v3 911; VI-NEXT: v_lshrrev_b16_e32 v9, v7, v8 912; VI-NEXT: v_sub_u16_e32 v7, 16, v7 913; VI-NEXT: v_lshlrev_b16_sdwa v7, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 914; VI-NEXT: v_or_b32_e32 v7, v7, v9 915; VI-NEXT: v_bfe_u32 v9, v5, 16, 4 916; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 917; VI-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc 918; VI-NEXT: v_and_b32_sdwa v6, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 919; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v2 920; VI-NEXT: v_lshrrev_b16_e32 v9, v6, v8 921; VI-NEXT: v_sub_u16_e32 v6, 16, v6 922; VI-NEXT: v_lshlrev_b16_sdwa v6, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 923; VI-NEXT: v_or_b32_e32 v6, v6, v9 924; VI-NEXT: v_bfe_u32 v9, v4, 16, 4 925; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v9 926; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc 927; VI-NEXT: v_and_b32_e32 v8, 15, v5 928; VI-NEXT: v_lshrrev_b16_e32 v9, v8, v3 929; VI-NEXT: v_sub_u16_e32 v8, 16, v8 930; VI-NEXT: s_mov_b32 s4, 0xf000f 931; VI-NEXT: v_lshlrev_b16_e32 v1, v8, v1 932; VI-NEXT: v_and_b32_e32 v5, s4, v5 933; VI-NEXT: v_or_b32_e32 v1, v1, v9 934; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 935; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 936; VI-NEXT: v_and_b32_e32 v3, 15, v4 937; VI-NEXT: v_lshrrev_b16_e32 v5, v3, v2 938; VI-NEXT: v_sub_u16_e32 v3, 16, v3 939; VI-NEXT: v_lshlrev_b16_e32 v0, v3, v0 940; VI-NEXT: v_and_b32_e32 v3, s4, v4 941; VI-NEXT: v_or_b32_e32 v0, v0, v5 942; VI-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 943; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 944; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6 945; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 946; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7 947; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 948; VI-NEXT: s_setpc_b64 s[30:31] 949; 950; GFX9-LABEL: v_fshr_v4i16: 951; GFX9: ; %bb.0: 952; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 953; GFX9-NEXT: v_mov_b32_e32 v7, 15 954; GFX9-NEXT: v_and_b32_e32 v6, 15, v5 955; GFX9-NEXT: v_mov_b32_e32 v9, 0xffff 956; GFX9-NEXT: v_and_b32_sdwa v8, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 957; GFX9-NEXT: v_and_b32_e32 v6, v9, v6 958; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6 959; GFX9-NEXT: v_pk_lshrrev_b16 v8, v6, v3 960; GFX9-NEXT: v_pk_sub_i16 v6, 16, v6 op_sel_hi:[0,1] 961; GFX9-NEXT: s_mov_b32 s6, 0xf000f 962; GFX9-NEXT: v_pk_lshlrev_b16 v1, v6, v1 963; GFX9-NEXT: v_and_b32_e32 v5, s6, v5 964; GFX9-NEXT: v_or_b32_e32 v1, v1, v8 965; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5 966; GFX9-NEXT: v_mov_b32_e32 v8, 0 967; GFX9-NEXT: v_cndmask_b32_e32 v6, v1, v3, vcc 968; GFX9-NEXT: v_cmp_eq_u16_sdwa s[4:5], v5, v8 src0_sel:WORD_1 src1_sel:DWORD 969; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 970; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 971; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] 972; GFX9-NEXT: v_and_b32_e32 v3, 15, v4 973; GFX9-NEXT: v_and_b32_sdwa v5, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 974; GFX9-NEXT: v_and_b32_e32 v3, v9, v3 975; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3 976; GFX9-NEXT: v_pk_lshrrev_b16 v5, v3, v2 977; GFX9-NEXT: v_pk_sub_i16 v3, 16, v3 op_sel_hi:[0,1] 978; GFX9-NEXT: v_pk_lshlrev_b16 v0, v3, v0 979; GFX9-NEXT: v_and_b32_e32 v3, s6, v4 980; GFX9-NEXT: v_or_b32_e32 v0, v0, v5 981; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3 982; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v2, vcc 983; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 984; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 985; GFX9-NEXT: v_cmp_eq_u16_sdwa s[4:5], v3, v8 src0_sel:WORD_1 src1_sel:DWORD 986; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] 987; GFX9-NEXT: v_and_b32_e32 v2, v9, v4 988; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v2 989; GFX9-NEXT: v_and_b32_e32 v2, v9, v6 990; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2 991; GFX9-NEXT: s_setpc_b64 s[30:31] 992; 993; R600-LABEL: v_fshr_v4i16: 994; R600: ; %bb.0: 995; R600-NEXT: CF_END 996; R600-NEXT: PAD 997 %ret = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2) 998 ret <4 x i16> %ret 999} 1000 1001define i64 @v_fshr_i64(i64 %src0, i64 %src1, i64 %src2) { 1002; SI-LABEL: v_fshr_i64: 1003; SI: ; %bb.0: 1004; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1005; SI-NEXT: v_and_b32_e32 v4, 63, v4 1006; SI-NEXT: v_sub_i32_e32 v7, vcc, 64, v4 1007; SI-NEXT: v_lshr_b64 v[5:6], v[2:3], v4 1008; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v7 1009; SI-NEXT: v_or_b32_e32 v0, v0, v5 1010; SI-NEXT: v_mov_b32_e32 v5, 0 1011; SI-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5] 1012; SI-NEXT: v_or_b32_e32 v1, v1, v6 1013; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 1014; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 1015; SI-NEXT: s_setpc_b64 s[30:31] 1016; 1017; VI-LABEL: v_fshr_i64: 1018; VI: ; %bb.0: 1019; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1020; VI-NEXT: v_and_b32_e32 v4, 63, v4 1021; VI-NEXT: v_sub_u32_e32 v7, vcc, 64, v4 1022; VI-NEXT: v_lshrrev_b64 v[5:6], v4, v[2:3] 1023; VI-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1] 1024; VI-NEXT: v_or_b32_e32 v0, v0, v5 1025; VI-NEXT: v_mov_b32_e32 v5, 0 1026; VI-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5] 1027; VI-NEXT: v_or_b32_e32 v1, v1, v6 1028; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 1029; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 1030; VI-NEXT: s_setpc_b64 s[30:31] 1031; 1032; GFX9-LABEL: v_fshr_i64: 1033; GFX9: ; %bb.0: 1034; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1035; GFX9-NEXT: v_and_b32_e32 v4, 63, v4 1036; GFX9-NEXT: v_sub_u32_e32 v7, 64, v4 1037; GFX9-NEXT: v_lshrrev_b64 v[5:6], v4, v[2:3] 1038; GFX9-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1] 1039; GFX9-NEXT: v_or_b32_e32 v0, v0, v5 1040; GFX9-NEXT: v_mov_b32_e32 v5, 0 1041; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5] 1042; GFX9-NEXT: v_or_b32_e32 v1, v1, v6 1043; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 1044; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc 1045; GFX9-NEXT: s_setpc_b64 s[30:31] 1046; 1047; R600-LABEL: v_fshr_i64: 1048; R600: ; %bb.0: 1049; R600-NEXT: CF_END 1050; R600-NEXT: PAD 1051 %ret = call i64 @llvm.fshr.i64(i64 %src0, i64 %src1, i64 %src2) 1052 ret i64 %ret 1053} 1054 1055define <2 x i64> @v_fshr_v2i64(<2 x i64> %src0, <2 x i64> %src1, <2 x i64> %src2) { 1056; SI-LABEL: v_fshr_v2i64: 1057; SI: ; %bb.0: 1058; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1059; SI-NEXT: v_and_b32_e32 v8, 63, v8 1060; SI-NEXT: v_sub_i32_e32 v9, vcc, 64, v8 1061; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v9 1062; SI-NEXT: v_lshr_b64 v[11:12], v[4:5], v8 1063; SI-NEXT: v_mov_b32_e32 v9, 0 1064; SI-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] 1065; SI-NEXT: v_or_b32_e32 v0, v0, v11 1066; SI-NEXT: v_and_b32_e32 v8, 63, v10 1067; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 1068; SI-NEXT: v_sub_i32_e64 v4, s[4:5], 64, v8 1069; SI-NEXT: v_or_b32_e32 v1, v1, v12 1070; SI-NEXT: v_lshr_b64 v[10:11], v[6:7], v8 1071; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v4 1072; SI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc 1073; SI-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] 1074; SI-NEXT: v_or_b32_e32 v3, v3, v11 1075; SI-NEXT: v_or_b32_e32 v2, v2, v10 1076; SI-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc 1077; SI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 1078; SI-NEXT: s_setpc_b64 s[30:31] 1079; 1080; VI-LABEL: v_fshr_v2i64: 1081; VI: ; %bb.0: 1082; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1083; VI-NEXT: v_and_b32_e32 v8, 63, v8 1084; VI-NEXT: v_sub_u32_e32 v9, vcc, 64, v8 1085; VI-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1] 1086; VI-NEXT: v_lshrrev_b64 v[11:12], v8, v[4:5] 1087; VI-NEXT: v_mov_b32_e32 v9, 0 1088; VI-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] 1089; VI-NEXT: v_or_b32_e32 v0, v0, v11 1090; VI-NEXT: v_and_b32_e32 v8, 63, v10 1091; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 1092; VI-NEXT: v_sub_u32_e64 v4, s[4:5], 64, v8 1093; VI-NEXT: v_or_b32_e32 v1, v1, v12 1094; VI-NEXT: v_lshrrev_b64 v[10:11], v8, v[6:7] 1095; VI-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3] 1096; VI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc 1097; VI-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] 1098; VI-NEXT: v_or_b32_e32 v3, v3, v11 1099; VI-NEXT: v_or_b32_e32 v2, v2, v10 1100; VI-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc 1101; VI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 1102; VI-NEXT: s_setpc_b64 s[30:31] 1103; 1104; GFX9-LABEL: v_fshr_v2i64: 1105; GFX9: ; %bb.0: 1106; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1107; GFX9-NEXT: v_and_b32_e32 v8, 63, v8 1108; GFX9-NEXT: v_sub_u32_e32 v9, 64, v8 1109; GFX9-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1] 1110; GFX9-NEXT: v_lshrrev_b64 v[11:12], v8, v[4:5] 1111; GFX9-NEXT: v_mov_b32_e32 v9, 0 1112; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] 1113; GFX9-NEXT: v_or_b32_e32 v0, v0, v11 1114; GFX9-NEXT: v_and_b32_e32 v8, 63, v10 1115; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 1116; GFX9-NEXT: v_sub_u32_e32 v4, 64, v8 1117; GFX9-NEXT: v_or_b32_e32 v1, v1, v12 1118; GFX9-NEXT: v_lshrrev_b64 v[10:11], v8, v[6:7] 1119; GFX9-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3] 1120; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc 1121; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] 1122; GFX9-NEXT: v_or_b32_e32 v3, v3, v11 1123; GFX9-NEXT: v_or_b32_e32 v2, v2, v10 1124; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc 1125; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc 1126; GFX9-NEXT: s_setpc_b64 s[30:31] 1127; 1128; R600-LABEL: v_fshr_v2i64: 1129; R600: ; %bb.0: 1130; R600-NEXT: CF_END 1131; R600-NEXT: PAD 1132 %ret = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %src0, <2 x i64> %src1, <2 x i64> %src2) 1133 ret <2 x i64> %ret 1134} 1135 1136define i24 @v_fshr_i24(i24 %src0, i24 %src1, i24 %src2) { 1137; SI-LABEL: v_fshr_i24: 1138; SI: ; %bb.0: 1139; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1140; SI-NEXT: s_mov_b32 s4, 0xffffff 1141; SI-NEXT: v_and_b32_e32 v2, s4, v2 1142; SI-NEXT: s_mov_b32 s5, 0xaaaaaaab 1143; SI-NEXT: v_mul_hi_u32 v3, v2, s5 1144; SI-NEXT: v_and_b32_e32 v4, s4, v1 1145; SI-NEXT: v_lshrrev_b32_e32 v3, 4, v3 1146; SI-NEXT: v_mul_lo_u32 v3, v3, 24 1147; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 1148; SI-NEXT: v_lshr_b32_e32 v3, v4, v2 1149; SI-NEXT: v_sub_i32_e32 v4, vcc, 24, v2 1150; SI-NEXT: v_and_b32_e32 v4, s4, v4 1151; SI-NEXT: v_lshl_b32_e32 v0, v0, v4 1152; SI-NEXT: v_or_b32_e32 v0, v0, v3 1153; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 1154; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 1155; SI-NEXT: s_setpc_b64 s[30:31] 1156; 1157; VI-LABEL: v_fshr_i24: 1158; VI: ; %bb.0: 1159; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1160; VI-NEXT: s_mov_b32 s4, 0xffffff 1161; VI-NEXT: v_and_b32_e32 v2, s4, v2 1162; VI-NEXT: s_mov_b32 s5, 0xaaaaaaab 1163; VI-NEXT: v_mul_hi_u32 v3, v2, s5 1164; VI-NEXT: v_and_b32_e32 v4, s4, v1 1165; VI-NEXT: v_lshrrev_b32_e32 v3, 4, v3 1166; VI-NEXT: v_mul_lo_u32 v3, v3, 24 1167; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v3 1168; VI-NEXT: v_lshrrev_b32_e32 v3, v2, v4 1169; VI-NEXT: v_sub_u32_e32 v4, vcc, 24, v2 1170; VI-NEXT: v_and_b32_e32 v4, s4, v4 1171; VI-NEXT: v_lshlrev_b32_e32 v0, v4, v0 1172; VI-NEXT: v_or_b32_e32 v0, v0, v3 1173; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 1174; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 1175; VI-NEXT: s_setpc_b64 s[30:31] 1176; 1177; GFX9-LABEL: v_fshr_i24: 1178; GFX9: ; %bb.0: 1179; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1180; GFX9-NEXT: s_mov_b32 s4, 0xffffff 1181; GFX9-NEXT: v_and_b32_e32 v2, s4, v2 1182; GFX9-NEXT: s_mov_b32 s5, 0xaaaaaaab 1183; GFX9-NEXT: v_mul_hi_u32 v3, v2, s5 1184; GFX9-NEXT: v_and_b32_e32 v4, s4, v1 1185; GFX9-NEXT: v_lshrrev_b32_e32 v3, 4, v3 1186; GFX9-NEXT: v_mul_lo_u32 v3, v3, 24 1187; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3 1188; GFX9-NEXT: v_lshrrev_b32_e32 v3, v2, v4 1189; GFX9-NEXT: v_sub_u32_e32 v4, 24, v2 1190; GFX9-NEXT: v_and_b32_e32 v4, s4, v4 1191; GFX9-NEXT: v_lshl_or_b32 v0, v0, v4, v3 1192; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 1193; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 1194; GFX9-NEXT: s_setpc_b64 s[30:31] 1195; 1196; R600-LABEL: v_fshr_i24: 1197; R600: ; %bb.0: 1198; R600-NEXT: CF_END 1199; R600-NEXT: PAD 1200 %ret = call i24 @llvm.fshr.i24(i24 %src0, i24 %src1, i24 %src2) 1201 ret i24 %ret 1202} 1203 1204define <2 x i24> @v_fshr_v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2) { 1205; SI-LABEL: v_fshr_v2i24: 1206; SI: ; %bb.0: 1207; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1208; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 1209; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16 1210; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20 1211; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4 1212; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12 1213; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 1214; SI-NEXT: s_mov_b32 s4, 0xffffff 1215; SI-NEXT: s_mov_b32 s5, 0xaaaaaaab 1216; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0 1217; SI-NEXT: v_add_i32_e32 v8, vcc, 4, v0 1218; SI-NEXT: v_add_i32_e32 v9, vcc, 5, v0 1219; SI-NEXT: v_add_i32_e32 v10, vcc, 2, v0 1220; SI-NEXT: s_waitcnt vmcnt(5) 1221; SI-NEXT: v_and_b32_e32 v14, s4, v1 1222; SI-NEXT: s_waitcnt vmcnt(4) 1223; SI-NEXT: v_and_b32_e32 v2, s4, v2 1224; SI-NEXT: v_mul_hi_u32 v12, v2, s5 1225; SI-NEXT: s_waitcnt vmcnt(3) 1226; SI-NEXT: v_and_b32_e32 v3, s4, v3 1227; SI-NEXT: v_mul_hi_u32 v13, v3, s5 1228; SI-NEXT: s_waitcnt vmcnt(1) 1229; SI-NEXT: v_and_b32_e32 v11, s4, v5 1230; SI-NEXT: v_lshrrev_b32_e32 v12, 4, v12 1231; SI-NEXT: v_mul_lo_u32 v12, v12, 24 1232; SI-NEXT: v_lshrrev_b32_e32 v13, 4, v13 1233; SI-NEXT: v_mul_lo_u32 v13, v13, 24 1234; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v12 1235; SI-NEXT: v_lshr_b32_e32 v12, v14, v2 1236; SI-NEXT: v_sub_i32_e32 v3, vcc, v3, v13 1237; SI-NEXT: v_sub_i32_e32 v13, vcc, 24, v2 1238; SI-NEXT: v_sub_i32_e32 v14, vcc, 24, v3 1239; SI-NEXT: v_and_b32_e32 v13, s4, v13 1240; SI-NEXT: s_waitcnt vmcnt(0) 1241; SI-NEXT: v_lshl_b32_e32 v6, v6, v13 1242; SI-NEXT: v_and_b32_e32 v14, 0xffffff, v14 1243; SI-NEXT: v_lshr_b32_e32 v11, v11, v3 1244; SI-NEXT: v_lshl_b32_e32 v4, v4, v14 1245; SI-NEXT: v_or_b32_e32 v6, v6, v12 1246; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 1247; SI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc 1248; SI-NEXT: v_or_b32_e32 v4, v4, v11 1249; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 1250; SI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc 1251; SI-NEXT: buffer_store_byte v2, v7, s[0:3], 0 offen 1252; SI-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen 1253; SI-NEXT: v_lshrrev_b32_e32 v0, 8, v2 1254; SI-NEXT: s_waitcnt expcnt(1) 1255; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 1256; SI-NEXT: s_waitcnt expcnt(0) 1257; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 1258; SI-NEXT: buffer_store_byte v0, v8, s[0:3], 0 offen 1259; SI-NEXT: buffer_store_byte v2, v9, s[0:3], 0 offen 1260; SI-NEXT: buffer_store_byte v1, v10, s[0:3], 0 offen 1261; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1262; SI-NEXT: s_setpc_b64 s[30:31] 1263; 1264; VI-LABEL: v_fshr_v2i24: 1265; VI: ; %bb.0: 1266; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1267; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 1268; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16 1269; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20 1270; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4 1271; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12 1272; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 1273; VI-NEXT: s_mov_b32 s4, 0xffffff 1274; VI-NEXT: s_mov_b32 s5, 0xaaaaaaab 1275; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v0 1276; VI-NEXT: v_add_u32_e32 v8, vcc, 4, v0 1277; VI-NEXT: v_add_u32_e32 v9, vcc, 5, v0 1278; VI-NEXT: v_add_u32_e32 v10, vcc, 2, v0 1279; VI-NEXT: s_waitcnt vmcnt(5) 1280; VI-NEXT: v_and_b32_e32 v14, s4, v1 1281; VI-NEXT: s_waitcnt vmcnt(4) 1282; VI-NEXT: v_and_b32_e32 v2, s4, v2 1283; VI-NEXT: v_mul_hi_u32 v12, v2, s5 1284; VI-NEXT: s_waitcnt vmcnt(3) 1285; VI-NEXT: v_and_b32_e32 v3, s4, v3 1286; VI-NEXT: v_mul_hi_u32 v13, v3, s5 1287; VI-NEXT: s_waitcnt vmcnt(1) 1288; VI-NEXT: v_and_b32_e32 v11, s4, v5 1289; VI-NEXT: v_lshrrev_b32_e32 v12, 4, v12 1290; VI-NEXT: v_mul_lo_u32 v12, v12, 24 1291; VI-NEXT: v_lshrrev_b32_e32 v13, 4, v13 1292; VI-NEXT: v_mul_lo_u32 v13, v13, 24 1293; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v12 1294; VI-NEXT: v_lshrrev_b32_e32 v12, v2, v14 1295; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v13 1296; VI-NEXT: v_sub_u32_e32 v13, vcc, 24, v2 1297; VI-NEXT: v_sub_u32_e32 v14, vcc, 24, v3 1298; VI-NEXT: v_and_b32_e32 v13, s4, v13 1299; VI-NEXT: s_waitcnt vmcnt(0) 1300; VI-NEXT: v_lshlrev_b32_e32 v6, v13, v6 1301; VI-NEXT: v_and_b32_e32 v14, 0xffffff, v14 1302; VI-NEXT: v_lshrrev_b32_e32 v11, v3, v11 1303; VI-NEXT: v_lshlrev_b32_e32 v4, v14, v4 1304; VI-NEXT: v_or_b32_e32 v6, v6, v12 1305; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 1306; VI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc 1307; VI-NEXT: v_or_b32_e32 v4, v4, v11 1308; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 1309; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc 1310; VI-NEXT: buffer_store_byte v2, v7, s[0:3], 0 offen 1311; VI-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen 1312; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v2 1313; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 1314; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 1315; VI-NEXT: buffer_store_byte v0, v8, s[0:3], 0 offen 1316; VI-NEXT: buffer_store_byte v2, v9, s[0:3], 0 offen 1317; VI-NEXT: buffer_store_byte v1, v10, s[0:3], 0 offen 1318; VI-NEXT: s_waitcnt vmcnt(0) 1319; VI-NEXT: s_setpc_b64 s[30:31] 1320; 1321; GFX9-LABEL: v_fshr_v2i24: 1322; GFX9: ; %bb.0: 1323; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1324; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:16 1325; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:20 1326; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:4 1327; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:12 1328; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 1329; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:8 1330; GFX9-NEXT: s_mov_b32 s4, 0xffffff 1331; GFX9-NEXT: s_mov_b32 s5, 0xaaaaaaab 1332; GFX9-NEXT: s_waitcnt vmcnt(5) 1333; GFX9-NEXT: v_and_b32_e32 v1, s4, v1 1334; GFX9-NEXT: v_mul_hi_u32 v6, v1, s5 1335; GFX9-NEXT: s_waitcnt vmcnt(4) 1336; GFX9-NEXT: v_and_b32_e32 v2, s4, v2 1337; GFX9-NEXT: v_mul_hi_u32 v7, v2, s5 1338; GFX9-NEXT: s_waitcnt vmcnt(2) 1339; GFX9-NEXT: v_and_b32_e32 v9, s4, v4 1340; GFX9-NEXT: v_lshrrev_b32_e32 v6, 4, v6 1341; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24 1342; GFX9-NEXT: v_lshrrev_b32_e32 v7, 4, v7 1343; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24 1344; GFX9-NEXT: s_waitcnt vmcnt(0) 1345; GFX9-NEXT: v_and_b32_e32 v10, s4, v8 1346; GFX9-NEXT: v_sub_u32_e32 v1, v1, v6 1347; GFX9-NEXT: v_lshrrev_b32_e32 v6, v1, v10 1348; GFX9-NEXT: v_sub_u32_e32 v2, v2, v7 1349; GFX9-NEXT: v_sub_u32_e32 v7, 24, v1 1350; GFX9-NEXT: v_sub_u32_e32 v10, 24, v2 1351; GFX9-NEXT: v_and_b32_e32 v7, s4, v7 1352; GFX9-NEXT: v_lshrrev_b32_e32 v9, v2, v9 1353; GFX9-NEXT: v_and_b32_e32 v10, 0xffffff, v10 1354; GFX9-NEXT: v_lshl_or_b32 v5, v5, v7, v6 1355; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 1356; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc 1357; GFX9-NEXT: v_lshl_or_b32 v3, v3, v10, v9 1358; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 1359; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc 1360; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v2 1361; GFX9-NEXT: buffer_store_byte v2, v0, s[0:3], 0 offen offset:3 1362; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], 0 offen offset:2 1363; GFX9-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen 1364; GFX9-NEXT: buffer_store_byte_d16_hi v2, v0, s[0:3], 0 offen offset:5 1365; GFX9-NEXT: buffer_store_byte v3, v0, s[0:3], 0 offen offset:4 1366; GFX9-NEXT: s_waitcnt vmcnt(0) 1367; GFX9-NEXT: s_setpc_b64 s[30:31] 1368; 1369; R600-LABEL: v_fshr_v2i24: 1370; R600: ; %bb.0: 1371; R600-NEXT: CF_END 1372; R600-NEXT: PAD 1373 %ret = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2) 1374 ret <2 x i24> %ret 1375} 1376