1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,SI
3; RUN: llc < %s -march=amdgcn -mcpu=tonga  -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,VI
4; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,GFX9
5; RUN: llc < %s -march=r600 -mcpu=redwood  -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,R600
6
7declare i32 @llvm.fshr.i32(i32, i32, i32)
8declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
9declare <3 x i32> @llvm.fshr.v3i32(<3 x i32>, <3 x i32>, <3 x i32>)
10declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
11declare i16 @llvm.fshr.i16(i16, i16, i16)
12declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
13declare <3 x i16> @llvm.fshr.v3i16(<3 x i16>, <3 x i16>, <3 x i16>)
14declare <4 x i16> @llvm.fshr.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
15declare i64 @llvm.fshr.i64(i64, i64, i64)
16declare <2 x i64> @llvm.fshr.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
17declare i24 @llvm.fshr.i24(i24, i24, i24)
18declare <2 x i24> @llvm.fshr.v2i24(<2 x i24>, <2 x i24>, <2 x i24>)
19
20define amdgpu_kernel void @fshr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %z) {
21; SI-LABEL: fshr_i32:
22; SI:       ; %bb.0: ; %entry
23; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
24; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
25; SI-NEXT:    s_load_dword s0, s[0:1], 0xd
26; SI-NEXT:    s_mov_b32 s7, 0xf000
27; SI-NEXT:    s_mov_b32 s6, -1
28; SI-NEXT:    s_waitcnt lgkmcnt(0)
29; SI-NEXT:    v_mov_b32_e32 v0, s3
30; SI-NEXT:    v_mov_b32_e32 v1, s0
31; SI-NEXT:    v_alignbit_b32 v0, s2, v0, v1
32; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
33; SI-NEXT:    s_endpgm
34;
35; VI-LABEL: fshr_i32:
36; VI:       ; %bb.0: ; %entry
37; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
38; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
39; VI-NEXT:    s_load_dword s0, s[0:1], 0x34
40; VI-NEXT:    s_waitcnt lgkmcnt(0)
41; VI-NEXT:    v_mov_b32_e32 v0, s5
42; VI-NEXT:    v_mov_b32_e32 v1, s0
43; VI-NEXT:    v_alignbit_b32 v2, s4, v0, v1
44; VI-NEXT:    v_mov_b32_e32 v0, s2
45; VI-NEXT:    v_mov_b32_e32 v1, s3
46; VI-NEXT:    flat_store_dword v[0:1], v2
47; VI-NEXT:    s_endpgm
48;
49; GFX9-LABEL: fshr_i32:
50; GFX9:       ; %bb.0: ; %entry
51; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
52; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
53; GFX9-NEXT:    s_load_dword s0, s[0:1], 0x34
54; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
55; GFX9-NEXT:    v_mov_b32_e32 v0, s5
56; GFX9-NEXT:    v_mov_b32_e32 v1, s0
57; GFX9-NEXT:    v_alignbit_b32 v2, s4, v0, v1
58; GFX9-NEXT:    v_mov_b32_e32 v0, s2
59; GFX9-NEXT:    v_mov_b32_e32 v1, s3
60; GFX9-NEXT:    global_store_dword v[0:1], v2, off
61; GFX9-NEXT:    s_endpgm
62;
63; R600-LABEL: fshr_i32:
64; R600:       ; %bb.0: ; %entry
65; R600-NEXT:    ALU 2, @4, KC0[CB0:0-32], KC1[]
66; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
67; R600-NEXT:    CF_END
68; R600-NEXT:    PAD
69; R600-NEXT:    ALU clause starting at 4:
70; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
71; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
72; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X,
73entry:
74  %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
75  store i32 %0, i32 addrspace(1)* %in
76  ret void
77}
78
79define amdgpu_kernel void @fshr_i32_imm(i32 addrspace(1)* %in, i32 %x, i32 %y) {
80; SI-LABEL: fshr_i32_imm:
81; SI:       ; %bb.0: ; %entry
82; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
83; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
84; SI-NEXT:    s_mov_b32 s7, 0xf000
85; SI-NEXT:    s_mov_b32 s6, -1
86; SI-NEXT:    s_waitcnt lgkmcnt(0)
87; SI-NEXT:    v_mov_b32_e32 v0, s1
88; SI-NEXT:    v_alignbit_b32 v0, s0, v0, 7
89; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
90; SI-NEXT:    s_endpgm
91;
92; VI-LABEL: fshr_i32_imm:
93; VI:       ; %bb.0: ; %entry
94; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
95; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
96; VI-NEXT:    s_waitcnt lgkmcnt(0)
97; VI-NEXT:    v_mov_b32_e32 v0, s1
98; VI-NEXT:    v_alignbit_b32 v2, s0, v0, 7
99; VI-NEXT:    v_mov_b32_e32 v0, s2
100; VI-NEXT:    v_mov_b32_e32 v1, s3
101; VI-NEXT:    flat_store_dword v[0:1], v2
102; VI-NEXT:    s_endpgm
103;
104; GFX9-LABEL: fshr_i32_imm:
105; GFX9:       ; %bb.0: ; %entry
106; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
107; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
108; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
109; GFX9-NEXT:    v_mov_b32_e32 v0, s1
110; GFX9-NEXT:    v_alignbit_b32 v2, s0, v0, 7
111; GFX9-NEXT:    v_mov_b32_e32 v0, s2
112; GFX9-NEXT:    v_mov_b32_e32 v1, s3
113; GFX9-NEXT:    global_store_dword v[0:1], v2, off
114; GFX9-NEXT:    s_endpgm
115;
116; R600-LABEL: fshr_i32_imm:
117; R600:       ; %bb.0: ; %entry
118; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
119; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
120; R600-NEXT:    CF_END
121; R600-NEXT:    PAD
122; R600-NEXT:    ALU clause starting at 4:
123; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
124; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
125; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,
126; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)
127entry:
128  %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7)
129  store i32 %0, i32 addrspace(1)* %in
130  ret void
131}
132
133define amdgpu_kernel void @fshr_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
134; SI-LABEL: fshr_v2i32:
135; SI:       ; %bb.0: ; %entry
136; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
137; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
138; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
139; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xf
140; SI-NEXT:    s_mov_b32 s7, 0xf000
141; SI-NEXT:    s_mov_b32 s6, -1
142; SI-NEXT:    s_waitcnt lgkmcnt(0)
143; SI-NEXT:    v_mov_b32_e32 v0, s9
144; SI-NEXT:    v_mov_b32_e32 v1, s1
145; SI-NEXT:    v_alignbit_b32 v1, s3, v0, v1
146; SI-NEXT:    v_mov_b32_e32 v0, s8
147; SI-NEXT:    v_mov_b32_e32 v2, s0
148; SI-NEXT:    v_alignbit_b32 v0, s2, v0, v2
149; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
150; SI-NEXT:    s_endpgm
151;
152; VI-LABEL: fshr_v2i32:
153; VI:       ; %bb.0: ; %entry
154; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
155; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
156; VI-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
157; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
158; VI-NEXT:    s_waitcnt lgkmcnt(0)
159; VI-NEXT:    v_mov_b32_e32 v0, s7
160; VI-NEXT:    v_mov_b32_e32 v1, s1
161; VI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
162; VI-NEXT:    v_mov_b32_e32 v0, s6
163; VI-NEXT:    v_mov_b32_e32 v2, s0
164; VI-NEXT:    v_alignbit_b32 v0, s4, v0, v2
165; VI-NEXT:    v_mov_b32_e32 v2, s2
166; VI-NEXT:    v_mov_b32_e32 v3, s3
167; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
168; VI-NEXT:    s_endpgm
169;
170; GFX9-LABEL: fshr_v2i32:
171; GFX9:       ; %bb.0: ; %entry
172; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
173; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
174; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
175; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
176; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
177; GFX9-NEXT:    v_mov_b32_e32 v0, s7
178; GFX9-NEXT:    v_mov_b32_e32 v1, s1
179; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, v1
180; GFX9-NEXT:    v_mov_b32_e32 v0, s6
181; GFX9-NEXT:    v_mov_b32_e32 v2, s0
182; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v2
183; GFX9-NEXT:    v_mov_b32_e32 v2, s2
184; GFX9-NEXT:    v_mov_b32_e32 v3, s3
185; GFX9-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
186; GFX9-NEXT:    s_endpgm
187;
188; R600-LABEL: fshr_v2i32:
189; R600:       ; %bb.0: ; %entry
190; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
191; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
192; R600-NEXT:    CF_END
193; R600-NEXT:    PAD
194; R600-NEXT:    ALU clause starting at 4:
195; R600-NEXT:     MOV * T0.W, KC0[4].X,
196; R600-NEXT:     BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].Z, PV.W,
197; R600-NEXT:     MOV * T0.W, KC0[3].W,
198; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, PV.W,
199; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
200; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
201entry:
202  %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
203  store <2 x i32> %0, <2 x i32> addrspace(1)* %in
204  ret void
205}
206
207define amdgpu_kernel void @fshr_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
208; SI-LABEL: fshr_v2i32_imm:
209; SI:       ; %bb.0: ; %entry
210; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
211; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
212; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
213; SI-NEXT:    s_mov_b32 s7, 0xf000
214; SI-NEXT:    s_mov_b32 s6, -1
215; SI-NEXT:    s_waitcnt lgkmcnt(0)
216; SI-NEXT:    v_mov_b32_e32 v0, s1
217; SI-NEXT:    v_alignbit_b32 v1, s3, v0, 9
218; SI-NEXT:    v_mov_b32_e32 v0, s0
219; SI-NEXT:    v_alignbit_b32 v0, s2, v0, 7
220; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
221; SI-NEXT:    s_endpgm
222;
223; VI-LABEL: fshr_v2i32_imm:
224; VI:       ; %bb.0: ; %entry
225; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
226; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
227; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
228; VI-NEXT:    s_waitcnt lgkmcnt(0)
229; VI-NEXT:    v_mov_b32_e32 v0, s1
230; VI-NEXT:    v_mov_b32_e32 v2, s0
231; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 9
232; VI-NEXT:    v_alignbit_b32 v0, s4, v2, 7
233; VI-NEXT:    v_mov_b32_e32 v2, s2
234; VI-NEXT:    v_mov_b32_e32 v3, s3
235; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
236; VI-NEXT:    s_endpgm
237;
238; GFX9-LABEL: fshr_v2i32_imm:
239; GFX9:       ; %bb.0: ; %entry
240; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
241; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
242; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
243; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
244; GFX9-NEXT:    v_mov_b32_e32 v0, s1
245; GFX9-NEXT:    v_mov_b32_e32 v2, s0
246; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 9
247; GFX9-NEXT:    v_alignbit_b32 v0, s4, v2, 7
248; GFX9-NEXT:    v_mov_b32_e32 v2, s2
249; GFX9-NEXT:    v_mov_b32_e32 v3, s3
250; GFX9-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
251; GFX9-NEXT:    s_endpgm
252;
253; R600-LABEL: fshr_v2i32_imm:
254; R600:       ; %bb.0: ; %entry
255; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
256; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
257; R600-NEXT:    CF_END
258; R600-NEXT:    PAD
259; R600-NEXT:    ALU clause starting at 4:
260; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
261; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)
262; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
263; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)
264; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
265; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
266entry:
267  %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
268  store <2 x i32> %0, <2 x i32> addrspace(1)* %in
269  ret void
270}
271
272define amdgpu_kernel void @fshr_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
273; SI-LABEL: fshr_v4i32:
274; SI:       ; %bb.0: ; %entry
275; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
276; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
277; SI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x11
278; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x15
279; SI-NEXT:    s_mov_b32 s7, 0xf000
280; SI-NEXT:    s_mov_b32 s6, -1
281; SI-NEXT:    s_waitcnt lgkmcnt(0)
282; SI-NEXT:    v_mov_b32_e32 v0, s15
283; SI-NEXT:    v_mov_b32_e32 v1, s3
284; SI-NEXT:    v_alignbit_b32 v3, s11, v0, v1
285; SI-NEXT:    v_mov_b32_e32 v0, s14
286; SI-NEXT:    v_mov_b32_e32 v1, s2
287; SI-NEXT:    v_alignbit_b32 v2, s10, v0, v1
288; SI-NEXT:    v_mov_b32_e32 v0, s13
289; SI-NEXT:    v_mov_b32_e32 v1, s1
290; SI-NEXT:    v_alignbit_b32 v1, s9, v0, v1
291; SI-NEXT:    v_mov_b32_e32 v0, s12
292; SI-NEXT:    v_mov_b32_e32 v4, s0
293; SI-NEXT:    v_alignbit_b32 v0, s8, v0, v4
294; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
295; SI-NEXT:    s_endpgm
296;
297; VI-LABEL: fshr_v4i32:
298; VI:       ; %bb.0: ; %entry
299; VI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
300; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
301; VI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
302; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
303; VI-NEXT:    s_waitcnt lgkmcnt(0)
304; VI-NEXT:    v_mov_b32_e32 v0, s11
305; VI-NEXT:    v_mov_b32_e32 v1, s3
306; VI-NEXT:    v_alignbit_b32 v3, s7, v0, v1
307; VI-NEXT:    v_mov_b32_e32 v0, s10
308; VI-NEXT:    v_mov_b32_e32 v1, s2
309; VI-NEXT:    v_alignbit_b32 v2, s6, v0, v1
310; VI-NEXT:    v_mov_b32_e32 v0, s9
311; VI-NEXT:    v_mov_b32_e32 v1, s1
312; VI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
313; VI-NEXT:    v_mov_b32_e32 v0, s8
314; VI-NEXT:    v_mov_b32_e32 v4, s0
315; VI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
316; VI-NEXT:    v_mov_b32_e32 v4, s12
317; VI-NEXT:    v_mov_b32_e32 v5, s13
318; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
319; VI-NEXT:    s_endpgm
320;
321; GFX9-LABEL: fshr_v4i32:
322; GFX9:       ; %bb.0: ; %entry
323; GFX9-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
324; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
325; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
326; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
327; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
328; GFX9-NEXT:    v_mov_b32_e32 v0, s11
329; GFX9-NEXT:    v_mov_b32_e32 v1, s3
330; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, v1
331; GFX9-NEXT:    v_mov_b32_e32 v0, s10
332; GFX9-NEXT:    v_mov_b32_e32 v1, s2
333; GFX9-NEXT:    v_alignbit_b32 v2, s6, v0, v1
334; GFX9-NEXT:    v_mov_b32_e32 v0, s9
335; GFX9-NEXT:    v_mov_b32_e32 v1, s1
336; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, v1
337; GFX9-NEXT:    v_mov_b32_e32 v0, s8
338; GFX9-NEXT:    v_mov_b32_e32 v4, s0
339; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v4
340; GFX9-NEXT:    v_mov_b32_e32 v4, s12
341; GFX9-NEXT:    v_mov_b32_e32 v5, s13
342; GFX9-NEXT:    global_store_dwordx4 v[4:5], v[0:3], off
343; GFX9-NEXT:    s_endpgm
344;
345; R600-LABEL: fshr_v4i32:
346; R600:       ; %bb.0: ; %entry
347; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
348; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
349; R600-NEXT:    CF_END
350; R600-NEXT:    PAD
351; R600-NEXT:    ALU clause starting at 4:
352; R600-NEXT:     MOV * T0.W, KC0[6].X,
353; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, PV.W,
354; R600-NEXT:     MOV * T1.W, KC0[5].W,
355; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, PV.W,
356; R600-NEXT:     MOV * T1.W, KC0[5].Z,
357; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, PV.W,
358; R600-NEXT:     MOV * T1.W, KC0[5].Y,
359; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, PV.W,
360; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
361; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
362entry:
363  %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
364  store <4 x i32> %0, <4 x i32> addrspace(1)* %in
365  ret void
366}
367
368define amdgpu_kernel void @fshr_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
369; SI-LABEL: fshr_v4i32_imm:
370; SI:       ; %bb.0: ; %entry
371; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
372; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
373; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
374; SI-NEXT:    s_mov_b32 s7, 0xf000
375; SI-NEXT:    s_mov_b32 s6, -1
376; SI-NEXT:    s_waitcnt lgkmcnt(0)
377; SI-NEXT:    v_mov_b32_e32 v0, s3
378; SI-NEXT:    v_alignbit_b32 v3, s11, v0, 1
379; SI-NEXT:    v_mov_b32_e32 v0, s2
380; SI-NEXT:    v_alignbit_b32 v2, s10, v0, 9
381; SI-NEXT:    v_mov_b32_e32 v0, s1
382; SI-NEXT:    v_alignbit_b32 v1, s9, v0, 7
383; SI-NEXT:    v_mov_b32_e32 v0, s0
384; SI-NEXT:    v_alignbit_b32 v0, s8, v0, 1
385; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
386; SI-NEXT:    s_endpgm
387;
388; VI-LABEL: fshr_v4i32_imm:
389; VI:       ; %bb.0: ; %entry
390; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
391; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
392; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x44
393; VI-NEXT:    s_waitcnt lgkmcnt(0)
394; VI-NEXT:    v_mov_b32_e32 v4, s8
395; VI-NEXT:    v_mov_b32_e32 v5, s9
396; VI-NEXT:    v_mov_b32_e32 v0, s3
397; VI-NEXT:    v_mov_b32_e32 v1, s2
398; VI-NEXT:    v_alignbit_b32 v3, s7, v0, 1
399; VI-NEXT:    v_mov_b32_e32 v0, s1
400; VI-NEXT:    v_alignbit_b32 v2, s6, v1, 9
401; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 7
402; VI-NEXT:    v_mov_b32_e32 v0, s0
403; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
404; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
405; VI-NEXT:    s_endpgm
406;
407; GFX9-LABEL: fshr_v4i32_imm:
408; GFX9:       ; %bb.0: ; %entry
409; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
410; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
411; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x44
412; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
413; GFX9-NEXT:    v_mov_b32_e32 v4, s8
414; GFX9-NEXT:    v_mov_b32_e32 v5, s9
415; GFX9-NEXT:    v_mov_b32_e32 v0, s3
416; GFX9-NEXT:    v_mov_b32_e32 v1, s2
417; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, 1
418; GFX9-NEXT:    v_mov_b32_e32 v0, s1
419; GFX9-NEXT:    v_alignbit_b32 v2, s6, v1, 9
420; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 7
421; GFX9-NEXT:    v_mov_b32_e32 v0, s0
422; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 1
423; GFX9-NEXT:    global_store_dwordx4 v[4:5], v[0:3], off
424; GFX9-NEXT:    s_endpgm
425;
426; R600-LABEL: fshr_v4i32_imm:
427; R600:       ; %bb.0: ; %entry
428; R600-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
429; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
430; R600-NEXT:    CF_END
431; R600-NEXT:    PAD
432; R600-NEXT:    ALU clause starting at 4:
433; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1,
434; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,
435; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)
436; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,
437; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)
438; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, 1,
439; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
440; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
441entry:
442  %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
443  store <4 x i32> %0, <4 x i32> addrspace(1)* %in
444  ret void
445}
446
447define i32 @v_fshr_i32(i32 %src0, i32 %src1, i32 %src2) {
448; GFX89-LABEL: v_fshr_i32:
449; GFX89:       ; %bb.0:
450; GFX89-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
451; GFX89-NEXT:    v_alignbit_b32 v0, v0, v1, v2
452; GFX89-NEXT:    s_setpc_b64 s[30:31]
453;
454; R600-LABEL: v_fshr_i32:
455; R600:       ; %bb.0:
456; R600-NEXT:    CF_END
457; R600-NEXT:    PAD
458  %ret = call i32 @llvm.fshr.i32(i32 %src0, i32 %src1, i32 %src2)
459  ret i32 %ret
460}
461
462define <2 x i32> @v_fshr_v2i32(<2 x i32> %src0, <2 x i32> %src1, <2 x i32> %src2) {
463; GFX89-LABEL: v_fshr_v2i32:
464; GFX89:       ; %bb.0:
465; GFX89-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
466; GFX89-NEXT:    v_alignbit_b32 v0, v0, v2, v4
467; GFX89-NEXT:    v_alignbit_b32 v1, v1, v3, v5
468; GFX89-NEXT:    s_setpc_b64 s[30:31]
469;
470; R600-LABEL: v_fshr_v2i32:
471; R600:       ; %bb.0:
472; R600-NEXT:    CF_END
473; R600-NEXT:    PAD
474  %ret = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %src0, <2 x i32> %src1, <2 x i32> %src2)
475  ret <2 x i32> %ret
476}
477
478define <3 x i32> @v_fshr_v3i32(<3 x i32> %src0, <3 x i32> %src1, <3 x i32> %src2) {
479; GFX89-LABEL: v_fshr_v3i32:
480; GFX89:       ; %bb.0:
481; GFX89-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
482; GFX89-NEXT:    v_alignbit_b32 v0, v0, v3, v6
483; GFX89-NEXT:    v_alignbit_b32 v1, v1, v4, v7
484; GFX89-NEXT:    v_alignbit_b32 v2, v2, v5, v8
485; GFX89-NEXT:    s_setpc_b64 s[30:31]
486;
487; R600-LABEL: v_fshr_v3i32:
488; R600:       ; %bb.0:
489; R600-NEXT:    CF_END
490; R600-NEXT:    PAD
491  %ret = call <3 x i32> @llvm.fshr.v3i32(<3 x i32> %src0, <3 x i32> %src1, <3 x i32> %src2)
492  ret <3 x i32> %ret
493}
494
495define <4 x i32> @v_fshr_v4i32(<4 x i32> %src0, <4 x i32> %src1, <4 x i32> %src2) {
496; GFX89-LABEL: v_fshr_v4i32:
497; GFX89:       ; %bb.0:
498; GFX89-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
499; GFX89-NEXT:    v_alignbit_b32 v0, v0, v4, v8
500; GFX89-NEXT:    v_alignbit_b32 v1, v1, v5, v9
501; GFX89-NEXT:    v_alignbit_b32 v2, v2, v6, v10
502; GFX89-NEXT:    v_alignbit_b32 v3, v3, v7, v11
503; GFX89-NEXT:    s_setpc_b64 s[30:31]
504;
505; R600-LABEL: v_fshr_v4i32:
506; R600:       ; %bb.0:
507; R600-NEXT:    CF_END
508; R600-NEXT:    PAD
509  %ret = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %src0, <4 x i32> %src1, <4 x i32> %src2)
510  ret <4 x i32> %ret
511}
512
513define i16 @v_fshr_i16(i16 %src0, i16 %src1, i16 %src2) {
514; SI-LABEL: v_fshr_i16:
515; SI:       ; %bb.0:
516; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
517; SI-NEXT:    v_or_b32_e32 v2, 16, v2
518; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
519; SI-NEXT:    v_alignbit_b32 v0, v0, v1, v2
520; SI-NEXT:    s_setpc_b64 s[30:31]
521;
522; VI-LABEL: v_fshr_i16:
523; VI:       ; %bb.0:
524; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
525; VI-NEXT:    v_xor_b32_e32 v3, -1, v2
526; VI-NEXT:    v_and_b32_e32 v2, 15, v2
527; VI-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
528; VI-NEXT:    v_and_b32_e32 v3, 15, v3
529; VI-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
530; VI-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
531; VI-NEXT:    v_or_b32_e32 v0, v0, v1
532; VI-NEXT:    s_setpc_b64 s[30:31]
533;
534; GFX9-LABEL: v_fshr_i16:
535; GFX9:       ; %bb.0:
536; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
537; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v2
538; GFX9-NEXT:    v_and_b32_e32 v2, 15, v2
539; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
540; GFX9-NEXT:    v_and_b32_e32 v3, 15, v3
541; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
542; GFX9-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
543; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
544; GFX9-NEXT:    s_setpc_b64 s[30:31]
545;
546; R600-LABEL: v_fshr_i16:
547; R600:       ; %bb.0:
548; R600-NEXT:    CF_END
549; R600-NEXT:    PAD
550  %ret = call i16 @llvm.fshr.i16(i16 %src0, i16 %src1, i16 %src2)
551  ret i16 %ret
552}
553
554define <2 x i16> @v_fshr_v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2) {
555; SI-LABEL: v_fshr_v2i16:
556; SI:       ; %bb.0:
557; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
558; SI-NEXT:    v_or_b32_e32 v5, 16, v5
559; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
560; SI-NEXT:    v_alignbit_b32 v1, v1, v3, v5
561; SI-NEXT:    v_or_b32_e32 v3, 16, v4
562; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
563; SI-NEXT:    v_alignbit_b32 v0, v0, v2, v3
564; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
565; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
566; SI-NEXT:    v_or_b32_e32 v0, v0, v1
567; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
568; SI-NEXT:    s_setpc_b64 s[30:31]
569;
570; VI-LABEL: v_fshr_v2i16:
571; VI:       ; %bb.0:
572; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
573; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
574; VI-NEXT:    v_and_b32_e32 v4, 15, v3
575; VI-NEXT:    v_mov_b32_e32 v5, 1
576; VI-NEXT:    v_xor_b32_e32 v3, -1, v3
577; VI-NEXT:    v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
578; VI-NEXT:    v_and_b32_e32 v3, 15, v3
579; VI-NEXT:    v_lshrrev_b16_sdwa v4, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
580; VI-NEXT:    v_lshlrev_b16_e32 v3, v3, v5
581; VI-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
582; VI-NEXT:    v_xor_b32_e32 v4, -1, v2
583; VI-NEXT:    v_and_b32_e32 v2, 15, v2
584; VI-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
585; VI-NEXT:    v_and_b32_e32 v4, 15, v4
586; VI-NEXT:    v_lshlrev_b16_e32 v0, v4, v0
587; VI-NEXT:    v_lshrrev_b16_e32 v1, v2, v1
588; VI-NEXT:    v_or_b32_e32 v0, v0, v1
589; VI-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
590; VI-NEXT:    s_setpc_b64 s[30:31]
591;
592; GFX9-LABEL: v_fshr_v2i16:
593; GFX9:       ; %bb.0:
594; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
595; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v2
596; GFX9-NEXT:    s_mov_b32 s4, 0xf000f
597; GFX9-NEXT:    v_and_b32_e32 v2, s4, v2
598; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 1, v0 op_sel_hi:[0,1]
599; GFX9-NEXT:    v_and_b32_e32 v3, s4, v3
600; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v3, v0
601; GFX9-NEXT:    v_pk_lshrrev_b16 v1, v2, v1
602; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
603; GFX9-NEXT:    s_setpc_b64 s[30:31]
604;
605; R600-LABEL: v_fshr_v2i16:
606; R600:       ; %bb.0:
607; R600-NEXT:    CF_END
608; R600-NEXT:    PAD
609  %ret = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2)
610  ret <2 x i16> %ret
611}
612
613define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2) {
614; SI-LABEL: v_fshr_v3i16:
615; SI:       ; %bb.0:
616; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
617; SI-NEXT:    v_or_b32_e32 v7, 16, v7
618; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
619; SI-NEXT:    v_alignbit_b32 v1, v1, v4, v7
620; SI-NEXT:    v_or_b32_e32 v4, 16, v6
621; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
622; SI-NEXT:    v_alignbit_b32 v0, v0, v3, v4
623; SI-NEXT:    s_mov_b32 s4, 0xffff
624; SI-NEXT:    v_or_b32_e32 v3, 16, v8
625; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v5
626; SI-NEXT:    v_alignbit_b32 v3, v2, v4, v3
627; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
628; SI-NEXT:    v_and_b32_e32 v0, s4, v0
629; SI-NEXT:    v_or_b32_e32 v0, v0, v1
630; SI-NEXT:    v_and_b32_e32 v2, s4, v3
631; SI-NEXT:    v_alignbit_b32 v1, v3, v1, 16
632; SI-NEXT:    s_setpc_b64 s[30:31]
633;
634; VI-LABEL: v_fshr_v3i16:
635; VI:       ; %bb.0:
636; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
637; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
638; VI-NEXT:    v_and_b32_e32 v7, 15, v6
639; VI-NEXT:    v_mov_b32_e32 v8, 1
640; VI-NEXT:    v_xor_b32_e32 v6, -1, v6
641; VI-NEXT:    v_lshlrev_b16_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
642; VI-NEXT:    v_and_b32_e32 v6, 15, v6
643; VI-NEXT:    v_lshrrev_b16_sdwa v7, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
644; VI-NEXT:    v_lshlrev_b16_e32 v6, v6, v8
645; VI-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
646; VI-NEXT:    v_xor_b32_e32 v7, -1, v5
647; VI-NEXT:    v_and_b32_e32 v5, 15, v5
648; VI-NEXT:    v_lshlrev_b16_e32 v1, 1, v1
649; VI-NEXT:    v_and_b32_e32 v7, 15, v7
650; VI-NEXT:    v_lshlrev_b16_e32 v1, v7, v1
651; VI-NEXT:    v_lshrrev_b16_e32 v3, v5, v3
652; VI-NEXT:    v_or_b32_e32 v1, v1, v3
653; VI-NEXT:    v_xor_b32_e32 v3, -1, v4
654; VI-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
655; VI-NEXT:    v_and_b32_e32 v3, 15, v3
656; VI-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
657; VI-NEXT:    v_and_b32_e32 v3, 15, v4
658; VI-NEXT:    v_lshrrev_b16_e32 v2, v3, v2
659; VI-NEXT:    v_or_b32_e32 v0, v0, v2
660; VI-NEXT:    v_or_b32_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
661; VI-NEXT:    s_setpc_b64 s[30:31]
662;
663; GFX9-LABEL: v_fshr_v3i16:
664; GFX9:       ; %bb.0:
665; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
666; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
667; GFX9-NEXT:    v_and_b32_e32 v7, 15, v6
668; GFX9-NEXT:    v_mov_b32_e32 v8, 1
669; GFX9-NEXT:    v_xor_b32_e32 v6, -1, v6
670; GFX9-NEXT:    v_lshlrev_b16_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
671; GFX9-NEXT:    v_and_b32_e32 v6, 15, v6
672; GFX9-NEXT:    v_lshrrev_b16_sdwa v7, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
673; GFX9-NEXT:    v_lshlrev_b16_e32 v6, v6, v8
674; GFX9-NEXT:    v_or_b32_e32 v6, v6, v7
675; GFX9-NEXT:    v_xor_b32_e32 v7, -1, v5
676; GFX9-NEXT:    v_and_b32_e32 v5, 15, v5
677; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 1, v1
678; GFX9-NEXT:    v_and_b32_e32 v7, 15, v7
679; GFX9-NEXT:    v_lshlrev_b16_e32 v1, v7, v1
680; GFX9-NEXT:    v_lshrrev_b16_e32 v3, v5, v3
681; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
682; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v4
683; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
684; GFX9-NEXT:    v_and_b32_e32 v3, 15, v3
685; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
686; GFX9-NEXT:    v_and_b32_e32 v3, 15, v4
687; GFX9-NEXT:    v_lshrrev_b16_e32 v2, v3, v2
688; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
689; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
690; GFX9-NEXT:    v_lshl_or_b32 v0, v6, 16, v0
691; GFX9-NEXT:    s_setpc_b64 s[30:31]
692;
693; R600-LABEL: v_fshr_v3i16:
694; R600:       ; %bb.0:
695; R600-NEXT:    CF_END
696; R600-NEXT:    PAD
697  %ret = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2)
698  ret <3 x i16> %ret
699}
700
701define <4 x i16> @v_fshr_v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2) {
702; SI-LABEL: v_fshr_v4i16:
703; SI:       ; %bb.0:
704; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
705; SI-NEXT:    v_or_b32_e32 v9, 16, v9
706; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
707; SI-NEXT:    v_alignbit_b32 v1, v1, v5, v9
708; SI-NEXT:    v_or_b32_e32 v5, 16, v8
709; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
710; SI-NEXT:    v_alignbit_b32 v0, v0, v4, v5
711; SI-NEXT:    v_or_b32_e32 v4, 16, v11
712; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v7
713; SI-NEXT:    v_alignbit_b32 v3, v3, v5, v4
714; SI-NEXT:    v_or_b32_e32 v4, 16, v10
715; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v6
716; SI-NEXT:    s_mov_b32 s4, 0xffff
717; SI-NEXT:    v_alignbit_b32 v2, v2, v5, v4
718; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
719; SI-NEXT:    v_and_b32_e32 v2, s4, v2
720; SI-NEXT:    v_or_b32_e32 v2, v2, v3
721; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
722; SI-NEXT:    v_and_b32_e32 v0, s4, v0
723; SI-NEXT:    v_or_b32_e32 v0, v0, v1
724; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 16
725; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
726; SI-NEXT:    s_setpc_b64 s[30:31]
727;
728; VI-LABEL: v_fshr_v4i16:
729; VI:       ; %bb.0:
730; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
731; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
732; VI-NEXT:    v_and_b32_e32 v7, 15, v6
733; VI-NEXT:    v_xor_b32_e32 v6, -1, v6
734; VI-NEXT:    v_mov_b32_e32 v8, 1
735; VI-NEXT:    v_lshlrev_b16_sdwa v9, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
736; VI-NEXT:    v_and_b32_e32 v6, 15, v6
737; VI-NEXT:    v_lshrrev_b16_sdwa v7, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
738; VI-NEXT:    v_lshlrev_b16_e32 v6, v6, v9
739; VI-NEXT:    v_or_b32_sdwa v6, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
740; VI-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
741; VI-NEXT:    v_and_b32_e32 v9, 15, v7
742; VI-NEXT:    v_xor_b32_e32 v7, -1, v7
743; VI-NEXT:    v_lshlrev_b16_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
744; VI-NEXT:    v_and_b32_e32 v7, 15, v7
745; VI-NEXT:    v_lshlrev_b16_e32 v7, v7, v8
746; VI-NEXT:    v_xor_b32_e32 v8, -1, v5
747; VI-NEXT:    v_and_b32_e32 v5, 15, v5
748; VI-NEXT:    v_lshlrev_b16_e32 v1, 1, v1
749; VI-NEXT:    v_and_b32_e32 v8, 15, v8
750; VI-NEXT:    v_lshlrev_b16_e32 v1, v8, v1
751; VI-NEXT:    v_lshrrev_b16_e32 v3, v5, v3
752; VI-NEXT:    v_or_b32_e32 v1, v1, v3
753; VI-NEXT:    v_xor_b32_e32 v3, -1, v4
754; VI-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
755; VI-NEXT:    v_and_b32_e32 v3, 15, v3
756; VI-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
757; VI-NEXT:    v_and_b32_e32 v3, 15, v4
758; VI-NEXT:    v_lshrrev_b16_sdwa v9, v9, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
759; VI-NEXT:    v_lshrrev_b16_e32 v2, v3, v2
760; VI-NEXT:    v_or_b32_sdwa v7, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
761; VI-NEXT:    v_or_b32_e32 v0, v0, v2
762; VI-NEXT:    v_or_b32_sdwa v0, v0, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
763; VI-NEXT:    v_or_b32_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
764; VI-NEXT:    s_setpc_b64 s[30:31]
765;
766; GFX9-LABEL: v_fshr_v4i16:
767; GFX9:       ; %bb.0:
768; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
769; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
770; GFX9-NEXT:    v_and_b32_e32 v7, 15, v6
771; GFX9-NEXT:    v_xor_b32_e32 v6, -1, v6
772; GFX9-NEXT:    v_mov_b32_e32 v8, 1
773; GFX9-NEXT:    v_lshlrev_b16_sdwa v9, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
774; GFX9-NEXT:    v_and_b32_e32 v6, 15, v6
775; GFX9-NEXT:    v_lshrrev_b16_sdwa v7, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
776; GFX9-NEXT:    v_lshlrev_b16_e32 v6, v6, v9
777; GFX9-NEXT:    v_or_b32_e32 v6, v6, v7
778; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
779; GFX9-NEXT:    v_and_b32_e32 v9, 15, v7
780; GFX9-NEXT:    v_xor_b32_e32 v7, -1, v7
781; GFX9-NEXT:    v_lshlrev_b16_sdwa v8, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
782; GFX9-NEXT:    v_and_b32_e32 v7, 15, v7
783; GFX9-NEXT:    v_lshlrev_b16_e32 v7, v7, v8
784; GFX9-NEXT:    v_xor_b32_e32 v8, -1, v5
785; GFX9-NEXT:    v_and_b32_e32 v5, 15, v5
786; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 1, v1
787; GFX9-NEXT:    v_and_b32_e32 v8, 15, v8
788; GFX9-NEXT:    v_lshlrev_b16_e32 v1, v8, v1
789; GFX9-NEXT:    v_lshrrev_b16_e32 v3, v5, v3
790; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
791; GFX9-NEXT:    v_xor_b32_e32 v3, -1, v4
792; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 1, v0
793; GFX9-NEXT:    v_and_b32_e32 v3, 15, v3
794; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v3, v0
795; GFX9-NEXT:    v_and_b32_e32 v3, 15, v4
796; GFX9-NEXT:    v_lshrrev_b16_sdwa v9, v9, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
797; GFX9-NEXT:    v_lshrrev_b16_e32 v2, v3, v2
798; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
799; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff
800; GFX9-NEXT:    v_and_b32_e32 v1, v2, v1
801; GFX9-NEXT:    v_or_b32_e32 v7, v7, v9
802; GFX9-NEXT:    v_and_b32_e32 v0, v2, v0
803; GFX9-NEXT:    v_lshl_or_b32 v0, v7, 16, v0
804; GFX9-NEXT:    v_lshl_or_b32 v1, v6, 16, v1
805; GFX9-NEXT:    s_setpc_b64 s[30:31]
806;
807; R600-LABEL: v_fshr_v4i16:
808; R600:       ; %bb.0:
809; R600-NEXT:    CF_END
810; R600-NEXT:    PAD
811  %ret = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2)
812  ret <4 x i16> %ret
813}
814
815define i64 @v_fshr_i64(i64 %src0, i64 %src1, i64 %src2) {
816; SI-LABEL: v_fshr_i64:
817; SI:       ; %bb.0:
818; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
819; SI-NEXT:    v_and_b32_e32 v5, 63, v4
820; SI-NEXT:    v_not_b32_e32 v4, v4
821; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
822; SI-NEXT:    v_and_b32_e32 v4, 63, v4
823; SI-NEXT:    v_lshr_b64 v[2:3], v[2:3], v5
824; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], v4
825; SI-NEXT:    v_or_b32_e32 v1, v1, v3
826; SI-NEXT:    v_or_b32_e32 v0, v0, v2
827; SI-NEXT:    s_setpc_b64 s[30:31]
828;
829; VI-LABEL: v_fshr_i64:
830; VI:       ; %bb.0:
831; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
832; VI-NEXT:    v_and_b32_e32 v5, 63, v4
833; VI-NEXT:    v_not_b32_e32 v4, v4
834; VI-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
835; VI-NEXT:    v_and_b32_e32 v4, 63, v4
836; VI-NEXT:    v_lshrrev_b64 v[2:3], v5, v[2:3]
837; VI-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]
838; VI-NEXT:    v_or_b32_e32 v1, v1, v3
839; VI-NEXT:    v_or_b32_e32 v0, v0, v2
840; VI-NEXT:    s_setpc_b64 s[30:31]
841;
842; GFX9-LABEL: v_fshr_i64:
843; GFX9:       ; %bb.0:
844; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
845; GFX9-NEXT:    v_and_b32_e32 v5, 63, v4
846; GFX9-NEXT:    v_not_b32_e32 v4, v4
847; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
848; GFX9-NEXT:    v_and_b32_e32 v4, 63, v4
849; GFX9-NEXT:    v_lshrrev_b64 v[2:3], v5, v[2:3]
850; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v4, v[0:1]
851; GFX9-NEXT:    v_or_b32_e32 v1, v1, v3
852; GFX9-NEXT:    v_or_b32_e32 v0, v0, v2
853; GFX9-NEXT:    s_setpc_b64 s[30:31]
854;
855; R600-LABEL: v_fshr_i64:
856; R600:       ; %bb.0:
857; R600-NEXT:    CF_END
858; R600-NEXT:    PAD
859  %ret = call i64 @llvm.fshr.i64(i64 %src0, i64 %src1, i64 %src2)
860  ret i64 %ret
861}
862
863define <2 x i64> @v_fshr_v2i64(<2 x i64> %src0, <2 x i64> %src1, <2 x i64> %src2) {
864; SI-LABEL: v_fshr_v2i64:
865; SI:       ; %bb.0:
866; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
867; SI-NEXT:    v_and_b32_e32 v9, 63, v8
868; SI-NEXT:    v_not_b32_e32 v8, v8
869; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
870; SI-NEXT:    v_and_b32_e32 v8, 63, v8
871; SI-NEXT:    v_lshr_b64 v[4:5], v[4:5], v9
872; SI-NEXT:    v_lshl_b64 v[0:1], v[0:1], v8
873; SI-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
874; SI-NEXT:    v_or_b32_e32 v1, v1, v5
875; SI-NEXT:    v_and_b32_e32 v5, 63, v10
876; SI-NEXT:    v_lshr_b64 v[5:6], v[6:7], v5
877; SI-NEXT:    v_not_b32_e32 v7, v10
878; SI-NEXT:    v_and_b32_e32 v7, 63, v7
879; SI-NEXT:    v_lshl_b64 v[2:3], v[2:3], v7
880; SI-NEXT:    v_or_b32_e32 v0, v0, v4
881; SI-NEXT:    v_or_b32_e32 v3, v3, v6
882; SI-NEXT:    v_or_b32_e32 v2, v2, v5
883; SI-NEXT:    s_setpc_b64 s[30:31]
884;
885; VI-LABEL: v_fshr_v2i64:
886; VI:       ; %bb.0:
887; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
888; VI-NEXT:    v_and_b32_e32 v9, 63, v8
889; VI-NEXT:    v_not_b32_e32 v8, v8
890; VI-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
891; VI-NEXT:    v_and_b32_e32 v8, 63, v8
892; VI-NEXT:    v_lshrrev_b64 v[4:5], v9, v[4:5]
893; VI-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]
894; VI-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
895; VI-NEXT:    v_or_b32_e32 v1, v1, v5
896; VI-NEXT:    v_and_b32_e32 v5, 63, v10
897; VI-NEXT:    v_lshrrev_b64 v[5:6], v5, v[6:7]
898; VI-NEXT:    v_not_b32_e32 v7, v10
899; VI-NEXT:    v_and_b32_e32 v7, 63, v7
900; VI-NEXT:    v_lshlrev_b64 v[2:3], v7, v[2:3]
901; VI-NEXT:    v_or_b32_e32 v0, v0, v4
902; VI-NEXT:    v_or_b32_e32 v3, v3, v6
903; VI-NEXT:    v_or_b32_e32 v2, v2, v5
904; VI-NEXT:    s_setpc_b64 s[30:31]
905;
906; GFX9-LABEL: v_fshr_v2i64:
907; GFX9:       ; %bb.0:
908; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
909; GFX9-NEXT:    v_and_b32_e32 v9, 63, v8
910; GFX9-NEXT:    v_not_b32_e32 v8, v8
911; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
912; GFX9-NEXT:    v_and_b32_e32 v8, 63, v8
913; GFX9-NEXT:    v_lshrrev_b64 v[4:5], v9, v[4:5]
914; GFX9-NEXT:    v_lshlrev_b64 v[0:1], v8, v[0:1]
915; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
916; GFX9-NEXT:    v_or_b32_e32 v1, v1, v5
917; GFX9-NEXT:    v_and_b32_e32 v5, 63, v10
918; GFX9-NEXT:    v_lshrrev_b64 v[5:6], v5, v[6:7]
919; GFX9-NEXT:    v_not_b32_e32 v7, v10
920; GFX9-NEXT:    v_and_b32_e32 v7, 63, v7
921; GFX9-NEXT:    v_lshlrev_b64 v[2:3], v7, v[2:3]
922; GFX9-NEXT:    v_or_b32_e32 v0, v0, v4
923; GFX9-NEXT:    v_or_b32_e32 v3, v3, v6
924; GFX9-NEXT:    v_or_b32_e32 v2, v2, v5
925; GFX9-NEXT:    s_setpc_b64 s[30:31]
926;
927; R600-LABEL: v_fshr_v2i64:
928; R600:       ; %bb.0:
929; R600-NEXT:    CF_END
930; R600-NEXT:    PAD
931  %ret = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %src0, <2 x i64> %src1, <2 x i64> %src2)
932  ret <2 x i64> %ret
933}
934
935define i24 @v_fshr_i24(i24 %src0, i24 %src1, i24 %src2) {
936; SI-LABEL: v_fshr_i24:
937; SI:       ; %bb.0:
938; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
939; SI-NEXT:    s_mov_b32 s4, 0xaaaaaaab
940; SI-NEXT:    v_mul_hi_u32 v3, v2, s4
941; SI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
942; SI-NEXT:    v_lshrrev_b32_e32 v3, 4, v3
943; SI-NEXT:    v_mul_lo_u32 v3, v3, 24
944; SI-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
945; SI-NEXT:    v_add_i32_e32 v2, vcc, 8, v2
946; SI-NEXT:    v_alignbit_b32 v0, v0, v1, v2
947; SI-NEXT:    s_setpc_b64 s[30:31]
948;
949; VI-LABEL: v_fshr_i24:
950; VI:       ; %bb.0:
951; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
952; VI-NEXT:    s_mov_b32 s4, 0xaaaaaaab
953; VI-NEXT:    v_mul_hi_u32 v3, v2, s4
954; VI-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
955; VI-NEXT:    v_lshrrev_b32_e32 v3, 4, v3
956; VI-NEXT:    v_mul_lo_u32 v3, v3, 24
957; VI-NEXT:    v_sub_u32_e32 v2, vcc, v2, v3
958; VI-NEXT:    v_add_u32_e32 v2, vcc, 8, v2
959; VI-NEXT:    v_alignbit_b32 v0, v0, v1, v2
960; VI-NEXT:    s_setpc_b64 s[30:31]
961;
962; GFX9-LABEL: v_fshr_i24:
963; GFX9:       ; %bb.0:
964; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
965; GFX9-NEXT:    s_mov_b32 s4, 0xaaaaaaab
966; GFX9-NEXT:    v_mul_hi_u32 v3, v2, s4
967; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
968; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 4, v3
969; GFX9-NEXT:    v_mul_lo_u32 v3, v3, 24
970; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v3
971; GFX9-NEXT:    v_add_u32_e32 v2, 8, v2
972; GFX9-NEXT:    v_alignbit_b32 v0, v0, v1, v2
973; GFX9-NEXT:    s_setpc_b64 s[30:31]
974;
975; R600-LABEL: v_fshr_i24:
976; R600:       ; %bb.0:
977; R600-NEXT:    CF_END
978; R600-NEXT:    PAD
979  %ret = call i24 @llvm.fshr.i24(i24 %src0, i24 %src1, i24 %src2)
980  ret i24 %ret
981}
982
983define <2 x i24> @v_fshr_v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2) {
984; SI-LABEL: v_fshr_v2i24:
985; SI:       ; %bb.0:
986; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
987; SI-NEXT:    s_mov_b32 s4, 0xaaaaaaab
988; SI-NEXT:    v_mul_hi_u32 v6, v4, s4
989; SI-NEXT:    v_mul_hi_u32 v7, v5, s4
990; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
991; SI-NEXT:    v_lshrrev_b32_e32 v6, 4, v6
992; SI-NEXT:    v_mul_lo_u32 v6, v6, 24
993; SI-NEXT:    v_sub_i32_e32 v4, vcc, v4, v6
994; SI-NEXT:    v_lshrrev_b32_e32 v6, 4, v7
995; SI-NEXT:    v_mul_lo_u32 v6, v6, 24
996; SI-NEXT:    v_add_i32_e32 v4, vcc, 8, v4
997; SI-NEXT:    v_alignbit_b32 v0, v0, v2, v4
998; SI-NEXT:    v_lshlrev_b32_e32 v2, 8, v3
999; SI-NEXT:    v_sub_i32_e32 v3, vcc, v5, v6
1000; SI-NEXT:    v_add_i32_e32 v3, vcc, 8, v3
1001; SI-NEXT:    v_alignbit_b32 v1, v1, v2, v3
1002; SI-NEXT:    s_setpc_b64 s[30:31]
1003;
1004; VI-LABEL: v_fshr_v2i24:
1005; VI:       ; %bb.0:
1006; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1007; VI-NEXT:    s_mov_b32 s4, 0xaaaaaaab
1008; VI-NEXT:    v_mul_hi_u32 v6, v4, s4
1009; VI-NEXT:    v_mul_hi_u32 v7, v5, s4
1010; VI-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
1011; VI-NEXT:    v_lshrrev_b32_e32 v6, 4, v6
1012; VI-NEXT:    v_mul_lo_u32 v6, v6, 24
1013; VI-NEXT:    v_sub_u32_e32 v4, vcc, v4, v6
1014; VI-NEXT:    v_lshrrev_b32_e32 v6, 4, v7
1015; VI-NEXT:    v_mul_lo_u32 v6, v6, 24
1016; VI-NEXT:    v_add_u32_e32 v4, vcc, 8, v4
1017; VI-NEXT:    v_alignbit_b32 v0, v0, v2, v4
1018; VI-NEXT:    v_lshlrev_b32_e32 v2, 8, v3
1019; VI-NEXT:    v_sub_u32_e32 v3, vcc, v5, v6
1020; VI-NEXT:    v_add_u32_e32 v3, vcc, 8, v3
1021; VI-NEXT:    v_alignbit_b32 v1, v1, v2, v3
1022; VI-NEXT:    s_setpc_b64 s[30:31]
1023;
1024; GFX9-LABEL: v_fshr_v2i24:
1025; GFX9:       ; %bb.0:
1026; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1027; GFX9-NEXT:    s_mov_b32 s4, 0xaaaaaaab
1028; GFX9-NEXT:    v_mul_hi_u32 v6, v4, s4
1029; GFX9-NEXT:    v_mul_hi_u32 v7, v5, s4
1030; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
1031; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 4, v6
1032; GFX9-NEXT:    v_mul_lo_u32 v6, v6, 24
1033; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v6
1034; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 4, v7
1035; GFX9-NEXT:    v_mul_lo_u32 v6, v6, 24
1036; GFX9-NEXT:    v_add_u32_e32 v4, 8, v4
1037; GFX9-NEXT:    v_alignbit_b32 v0, v0, v2, v4
1038; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 8, v3
1039; GFX9-NEXT:    v_sub_u32_e32 v3, v5, v6
1040; GFX9-NEXT:    v_add_u32_e32 v3, 8, v3
1041; GFX9-NEXT:    v_alignbit_b32 v1, v1, v2, v3
1042; GFX9-NEXT:    s_setpc_b64 s[30:31]
1043;
1044; R600-LABEL: v_fshr_v2i24:
1045; R600:       ; %bb.0:
1046; R600-NEXT:    CF_END
1047; R600-NEXT:    PAD
1048  %ret = call <2 x i24> @llvm.fshr.v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2)
1049  ret <2 x i24> %ret
1050}
1051