1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,SI
3; RUN: llc < %s -march=amdgcn -mcpu=tonga  -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,VI
4; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,GFX9
5; RUN: llc < %s -march=r600 -mcpu=redwood  -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,R600
6
7declare i32 @llvm.fshl.i32(i32, i32, i32) nounwind readnone
8declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
9declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
10
11define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %z) {
12; SI-LABEL: fshl_i32:
13; SI:       ; %bb.0: ; %entry
14; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
15; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xb
16; SI-NEXT:    s_mov_b32 s7, 0xf000
17; SI-NEXT:    s_mov_b32 s6, -1
18; SI-NEXT:    s_waitcnt lgkmcnt(0)
19; SI-NEXT:    s_andn2_b32 s3, 31, s2
20; SI-NEXT:    s_lshr_b32 s1, s1, 1
21; SI-NEXT:    s_and_b32 s2, s2, 31
22; SI-NEXT:    s_lshr_b32 s1, s1, s3
23; SI-NEXT:    s_lshl_b32 s0, s0, s2
24; SI-NEXT:    s_or_b32 s0, s0, s1
25; SI-NEXT:    v_mov_b32_e32 v0, s0
26; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
27; SI-NEXT:    s_endpgm
28;
29; VI-LABEL: fshl_i32:
30; VI:       ; %bb.0: ; %entry
31; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
32; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x2c
33; VI-NEXT:    s_waitcnt lgkmcnt(0)
34; VI-NEXT:    v_mov_b32_e32 v0, s4
35; VI-NEXT:    s_andn2_b32 s3, 31, s2
36; VI-NEXT:    s_lshr_b32 s1, s1, 1
37; VI-NEXT:    s_and_b32 s2, s2, 31
38; VI-NEXT:    s_lshr_b32 s1, s1, s3
39; VI-NEXT:    s_lshl_b32 s0, s0, s2
40; VI-NEXT:    s_or_b32 s0, s0, s1
41; VI-NEXT:    v_mov_b32_e32 v1, s5
42; VI-NEXT:    v_mov_b32_e32 v2, s0
43; VI-NEXT:    flat_store_dword v[0:1], v2
44; VI-NEXT:    s_endpgm
45;
46; GFX9-LABEL: fshl_i32:
47; GFX9:       ; %bb.0: ; %entry
48; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
49; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x2c
50; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
51; GFX9-NEXT:    v_mov_b32_e32 v0, s4
52; GFX9-NEXT:    s_andn2_b32 s3, 31, s2
53; GFX9-NEXT:    s_lshr_b32 s1, s1, 1
54; GFX9-NEXT:    s_and_b32 s2, s2, 31
55; GFX9-NEXT:    s_lshr_b32 s1, s1, s3
56; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
57; GFX9-NEXT:    s_or_b32 s0, s0, s1
58; GFX9-NEXT:    v_mov_b32_e32 v1, s5
59; GFX9-NEXT:    v_mov_b32_e32 v2, s0
60; GFX9-NEXT:    global_store_dword v[0:1], v2, off
61; GFX9-NEXT:    s_endpgm
62;
63; R600-LABEL: fshl_i32:
64; R600:       ; %bb.0: ; %entry
65; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
66; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
67; R600-NEXT:    CF_END
68; R600-NEXT:    PAD
69; R600-NEXT:    ALU clause starting at 4:
70; R600-NEXT:     NOT_INT * T0.W, KC0[3].X,
71; R600-NEXT:     AND_INT T0.Z, KC0[3].X, literal.x,
72; R600-NEXT:     AND_INT T0.W, PV.W, literal.x,
73; R600-NEXT:     LSHR * T1.W, KC0[2].W, 1,
74; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
75; R600-NEXT:     LSHR T0.W, PS, PV.W,
76; R600-NEXT:     LSHL * T1.W, KC0[2].Z, PV.Z,
77; R600-NEXT:     OR_INT T0.X, PS, PV.W,
78; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
79; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
80entry:
81  %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
82  store i32 %0, i32 addrspace(1)* %in
83  ret void
84}
85
86define amdgpu_kernel void @fshl_i32_imm(i32 addrspace(1)* %in, i32 %x, i32 %y) {
87; SI-LABEL: fshl_i32_imm:
88; SI:       ; %bb.0: ; %entry
89; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
90; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
91; SI-NEXT:    s_mov_b32 s7, 0xf000
92; SI-NEXT:    s_mov_b32 s6, -1
93; SI-NEXT:    s_waitcnt lgkmcnt(0)
94; SI-NEXT:    v_mov_b32_e32 v0, s1
95; SI-NEXT:    v_alignbit_b32 v0, s0, v0, 25
96; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
97; SI-NEXT:    s_endpgm
98;
99; VI-LABEL: fshl_i32_imm:
100; VI:       ; %bb.0: ; %entry
101; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
102; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
103; VI-NEXT:    s_waitcnt lgkmcnt(0)
104; VI-NEXT:    v_mov_b32_e32 v0, s1
105; VI-NEXT:    v_alignbit_b32 v2, s0, v0, 25
106; VI-NEXT:    v_mov_b32_e32 v0, s2
107; VI-NEXT:    v_mov_b32_e32 v1, s3
108; VI-NEXT:    flat_store_dword v[0:1], v2
109; VI-NEXT:    s_endpgm
110;
111; GFX9-LABEL: fshl_i32_imm:
112; GFX9:       ; %bb.0: ; %entry
113; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
114; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
115; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
116; GFX9-NEXT:    v_mov_b32_e32 v0, s1
117; GFX9-NEXT:    v_alignbit_b32 v2, s0, v0, 25
118; GFX9-NEXT:    v_mov_b32_e32 v0, s2
119; GFX9-NEXT:    v_mov_b32_e32 v1, s3
120; GFX9-NEXT:    global_store_dword v[0:1], v2, off
121; GFX9-NEXT:    s_endpgm
122;
123; R600-LABEL: fshl_i32_imm:
124; R600:       ; %bb.0: ; %entry
125; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
126; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
127; R600-NEXT:    CF_END
128; R600-NEXT:    PAD
129; R600-NEXT:    ALU clause starting at 4:
130; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
131; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
132; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,
133; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
134entry:
135  %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 7)
136  store i32 %0, i32 addrspace(1)* %in
137  ret void
138}
139
140define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
141; SI-LABEL: fshl_v2i32:
142; SI:       ; %bb.0: ; %entry
143; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
144; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
145; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
146; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xf
147; SI-NEXT:    s_mov_b32 s7, 0xf000
148; SI-NEXT:    s_mov_b32 s6, -1
149; SI-NEXT:    s_waitcnt lgkmcnt(0)
150; SI-NEXT:    s_lshr_b32 s9, s9, 1
151; SI-NEXT:    s_andn2_b32 s10, 31, s1
152; SI-NEXT:    s_and_b32 s1, s1, 31
153; SI-NEXT:    s_lshl_b32 s1, s3, s1
154; SI-NEXT:    s_andn2_b32 s3, 31, s0
155; SI-NEXT:    s_and_b32 s0, s0, 31
156; SI-NEXT:    s_lshr_b32 s8, s8, 1
157; SI-NEXT:    s_lshr_b32 s9, s9, s10
158; SI-NEXT:    s_lshr_b32 s3, s8, s3
159; SI-NEXT:    s_lshl_b32 s0, s2, s0
160; SI-NEXT:    s_or_b32 s1, s1, s9
161; SI-NEXT:    s_or_b32 s0, s0, s3
162; SI-NEXT:    v_mov_b32_e32 v0, s0
163; SI-NEXT:    v_mov_b32_e32 v1, s1
164; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
165; SI-NEXT:    s_endpgm
166;
167; VI-LABEL: fshl_v2i32:
168; VI:       ; %bb.0: ; %entry
169; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
170; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
171; VI-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
172; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
173; VI-NEXT:    s_waitcnt lgkmcnt(0)
174; VI-NEXT:    v_mov_b32_e32 v2, s2
175; VI-NEXT:    v_mov_b32_e32 v3, s3
176; VI-NEXT:    s_lshr_b32 s7, s7, 1
177; VI-NEXT:    s_andn2_b32 s8, 31, s1
178; VI-NEXT:    s_and_b32 s1, s1, 31
179; VI-NEXT:    s_lshl_b32 s1, s5, s1
180; VI-NEXT:    s_andn2_b32 s5, 31, s0
181; VI-NEXT:    s_and_b32 s0, s0, 31
182; VI-NEXT:    s_lshr_b32 s6, s6, 1
183; VI-NEXT:    s_lshr_b32 s7, s7, s8
184; VI-NEXT:    s_lshr_b32 s5, s6, s5
185; VI-NEXT:    s_lshl_b32 s0, s4, s0
186; VI-NEXT:    s_or_b32 s1, s1, s7
187; VI-NEXT:    s_or_b32 s0, s0, s5
188; VI-NEXT:    v_mov_b32_e32 v0, s0
189; VI-NEXT:    v_mov_b32_e32 v1, s1
190; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
191; VI-NEXT:    s_endpgm
192;
193; GFX9-LABEL: fshl_v2i32:
194; GFX9:       ; %bb.0: ; %entry
195; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
196; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
197; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
198; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
199; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
200; GFX9-NEXT:    v_mov_b32_e32 v2, s2
201; GFX9-NEXT:    v_mov_b32_e32 v3, s3
202; GFX9-NEXT:    s_lshr_b32 s7, s7, 1
203; GFX9-NEXT:    s_andn2_b32 s8, 31, s1
204; GFX9-NEXT:    s_and_b32 s1, s1, 31
205; GFX9-NEXT:    s_lshl_b32 s1, s5, s1
206; GFX9-NEXT:    s_andn2_b32 s5, 31, s0
207; GFX9-NEXT:    s_and_b32 s0, s0, 31
208; GFX9-NEXT:    s_lshr_b32 s6, s6, 1
209; GFX9-NEXT:    s_lshr_b32 s7, s7, s8
210; GFX9-NEXT:    s_lshr_b32 s5, s6, s5
211; GFX9-NEXT:    s_lshl_b32 s0, s4, s0
212; GFX9-NEXT:    s_or_b32 s1, s1, s7
213; GFX9-NEXT:    s_or_b32 s0, s0, s5
214; GFX9-NEXT:    v_mov_b32_e32 v0, s0
215; GFX9-NEXT:    v_mov_b32_e32 v1, s1
216; GFX9-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
217; GFX9-NEXT:    s_endpgm
218;
219; R600-LABEL: fshl_v2i32:
220; R600:       ; %bb.0: ; %entry
221; R600-NEXT:    ALU 17, @4, KC0[CB0:0-32], KC1[]
222; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
223; R600-NEXT:    CF_END
224; R600-NEXT:    PAD
225; R600-NEXT:    ALU clause starting at 4:
226; R600-NEXT:     NOT_INT * T0.W, KC0[4].X,
227; R600-NEXT:     AND_INT T0.Y, KC0[4].X, literal.x,
228; R600-NEXT:     AND_INT T0.Z, PV.W, literal.x,
229; R600-NEXT:     LSHR T0.W, KC0[3].Z, 1,
230; R600-NEXT:     NOT_INT * T1.W, KC0[3].W,
231; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
232; R600-NEXT:     AND_INT T0.X, KC0[3].W, literal.x,
233; R600-NEXT:     AND_INT T1.Y, PS, literal.x,
234; R600-NEXT:     LSHR T1.Z, KC0[3].Y, 1,
235; R600-NEXT:     LSHR T0.W, PV.W, PV.Z,
236; R600-NEXT:     LSHL * T1.W, KC0[3].X, PV.Y,
237; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
238; R600-NEXT:     OR_INT T0.Y, PS, PV.W,
239; R600-NEXT:     LSHR T0.W, PV.Z, PV.Y,
240; R600-NEXT:     LSHL * T1.W, KC0[2].W, PV.X,
241; R600-NEXT:     OR_INT T0.X, PS, PV.W,
242; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
243; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
244entry:
245  %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
246  store <2 x i32> %0, <2 x i32> addrspace(1)* %in
247  ret void
248}
249
250define amdgpu_kernel void @fshl_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
251; SI-LABEL: fshl_v2i32_imm:
252; SI:       ; %bb.0: ; %entry
253; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
254; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
255; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
256; SI-NEXT:    s_mov_b32 s7, 0xf000
257; SI-NEXT:    s_mov_b32 s6, -1
258; SI-NEXT:    s_waitcnt lgkmcnt(0)
259; SI-NEXT:    v_mov_b32_e32 v0, s1
260; SI-NEXT:    v_alignbit_b32 v1, s3, v0, 23
261; SI-NEXT:    v_mov_b32_e32 v0, s0
262; SI-NEXT:    v_alignbit_b32 v0, s2, v0, 25
263; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
264; SI-NEXT:    s_endpgm
265;
266; VI-LABEL: fshl_v2i32_imm:
267; VI:       ; %bb.0: ; %entry
268; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
269; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
270; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
271; VI-NEXT:    s_waitcnt lgkmcnt(0)
272; VI-NEXT:    v_mov_b32_e32 v0, s1
273; VI-NEXT:    v_mov_b32_e32 v2, s0
274; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 23
275; VI-NEXT:    v_alignbit_b32 v0, s4, v2, 25
276; VI-NEXT:    v_mov_b32_e32 v2, s2
277; VI-NEXT:    v_mov_b32_e32 v3, s3
278; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
279; VI-NEXT:    s_endpgm
280;
281; GFX9-LABEL: fshl_v2i32_imm:
282; GFX9:       ; %bb.0: ; %entry
283; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
284; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
285; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
286; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
287; GFX9-NEXT:    v_mov_b32_e32 v0, s1
288; GFX9-NEXT:    v_mov_b32_e32 v2, s0
289; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 23
290; GFX9-NEXT:    v_alignbit_b32 v0, s4, v2, 25
291; GFX9-NEXT:    v_mov_b32_e32 v2, s2
292; GFX9-NEXT:    v_mov_b32_e32 v3, s3
293; GFX9-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
294; GFX9-NEXT:    s_endpgm
295;
296; R600-LABEL: fshl_v2i32_imm:
297; R600:       ; %bb.0: ; %entry
298; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
299; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
300; R600-NEXT:    CF_END
301; R600-NEXT:    PAD
302; R600-NEXT:    ALU clause starting at 4:
303; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
304; R600-NEXT:    23(3.222986e-44), 0(0.000000e+00)
305; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
306; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
307; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
308; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
309entry:
310  %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
311  store <2 x i32> %0, <2 x i32> addrspace(1)* %in
312  ret void
313}
314
315define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
316; SI-LABEL: fshl_v4i32:
317; SI:       ; %bb.0: ; %entry
318; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
319; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
320; SI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x11
321; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x15
322; SI-NEXT:    s_mov_b32 s7, 0xf000
323; SI-NEXT:    s_mov_b32 s6, -1
324; SI-NEXT:    s_waitcnt lgkmcnt(0)
325; SI-NEXT:    s_lshr_b32 s14, s14, 1
326; SI-NEXT:    s_andn2_b32 s16, 31, s3
327; SI-NEXT:    s_and_b32 s3, s3, 31
328; SI-NEXT:    s_lshl_b32 s3, s11, s3
329; SI-NEXT:    s_andn2_b32 s11, 31, s2
330; SI-NEXT:    s_and_b32 s2, s2, 31
331; SI-NEXT:    s_lshl_b32 s2, s10, s2
332; SI-NEXT:    s_lshr_b32 s11, s14, s11
333; SI-NEXT:    s_or_b32 s2, s2, s11
334; SI-NEXT:    s_andn2_b32 s10, 31, s1
335; SI-NEXT:    s_and_b32 s1, s1, 31
336; SI-NEXT:    s_lshr_b32 s11, s13, 1
337; SI-NEXT:    s_lshl_b32 s1, s9, s1
338; SI-NEXT:    s_lshr_b32 s10, s11, s10
339; SI-NEXT:    s_lshr_b32 s15, s15, 1
340; SI-NEXT:    s_or_b32 s1, s1, s10
341; SI-NEXT:    s_andn2_b32 s9, 31, s0
342; SI-NEXT:    s_and_b32 s0, s0, 31
343; SI-NEXT:    s_lshr_b32 s10, s12, 1
344; SI-NEXT:    s_lshr_b32 s15, s15, s16
345; SI-NEXT:    s_lshr_b32 s9, s10, s9
346; SI-NEXT:    s_lshl_b32 s0, s8, s0
347; SI-NEXT:    s_or_b32 s3, s3, s15
348; SI-NEXT:    s_or_b32 s0, s0, s9
349; SI-NEXT:    v_mov_b32_e32 v0, s0
350; SI-NEXT:    v_mov_b32_e32 v1, s1
351; SI-NEXT:    v_mov_b32_e32 v2, s2
352; SI-NEXT:    v_mov_b32_e32 v3, s3
353; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
354; SI-NEXT:    s_endpgm
355;
356; VI-LABEL: fshl_v4i32:
357; VI:       ; %bb.0: ; %entry
358; VI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
359; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
360; VI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
361; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
362; VI-NEXT:    s_waitcnt lgkmcnt(0)
363; VI-NEXT:    v_mov_b32_e32 v4, s12
364; VI-NEXT:    v_mov_b32_e32 v5, s13
365; VI-NEXT:    s_lshr_b32 s10, s10, 1
366; VI-NEXT:    s_andn2_b32 s14, 31, s3
367; VI-NEXT:    s_and_b32 s3, s3, 31
368; VI-NEXT:    s_lshl_b32 s3, s7, s3
369; VI-NEXT:    s_andn2_b32 s7, 31, s2
370; VI-NEXT:    s_and_b32 s2, s2, 31
371; VI-NEXT:    s_lshl_b32 s2, s6, s2
372; VI-NEXT:    s_lshr_b32 s7, s10, s7
373; VI-NEXT:    s_or_b32 s2, s2, s7
374; VI-NEXT:    s_andn2_b32 s6, 31, s1
375; VI-NEXT:    s_and_b32 s1, s1, 31
376; VI-NEXT:    s_lshr_b32 s7, s9, 1
377; VI-NEXT:    s_lshl_b32 s1, s5, s1
378; VI-NEXT:    s_lshr_b32 s6, s7, s6
379; VI-NEXT:    s_lshr_b32 s11, s11, 1
380; VI-NEXT:    s_or_b32 s1, s1, s6
381; VI-NEXT:    s_andn2_b32 s5, 31, s0
382; VI-NEXT:    s_and_b32 s0, s0, 31
383; VI-NEXT:    s_lshr_b32 s6, s8, 1
384; VI-NEXT:    s_lshr_b32 s11, s11, s14
385; VI-NEXT:    s_lshr_b32 s5, s6, s5
386; VI-NEXT:    s_lshl_b32 s0, s4, s0
387; VI-NEXT:    s_or_b32 s3, s3, s11
388; VI-NEXT:    s_or_b32 s0, s0, s5
389; VI-NEXT:    v_mov_b32_e32 v0, s0
390; VI-NEXT:    v_mov_b32_e32 v1, s1
391; VI-NEXT:    v_mov_b32_e32 v2, s2
392; VI-NEXT:    v_mov_b32_e32 v3, s3
393; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
394; VI-NEXT:    s_endpgm
395;
396; GFX9-LABEL: fshl_v4i32:
397; GFX9:       ; %bb.0: ; %entry
398; GFX9-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
399; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
400; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
401; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
402; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
403; GFX9-NEXT:    v_mov_b32_e32 v4, s12
404; GFX9-NEXT:    v_mov_b32_e32 v5, s13
405; GFX9-NEXT:    s_lshr_b32 s10, s10, 1
406; GFX9-NEXT:    s_andn2_b32 s14, 31, s3
407; GFX9-NEXT:    s_and_b32 s3, s3, 31
408; GFX9-NEXT:    s_lshl_b32 s3, s7, s3
409; GFX9-NEXT:    s_andn2_b32 s7, 31, s2
410; GFX9-NEXT:    s_and_b32 s2, s2, 31
411; GFX9-NEXT:    s_lshl_b32 s2, s6, s2
412; GFX9-NEXT:    s_lshr_b32 s7, s10, s7
413; GFX9-NEXT:    s_or_b32 s2, s2, s7
414; GFX9-NEXT:    s_andn2_b32 s6, 31, s1
415; GFX9-NEXT:    s_and_b32 s1, s1, 31
416; GFX9-NEXT:    s_lshr_b32 s7, s9, 1
417; GFX9-NEXT:    s_lshl_b32 s1, s5, s1
418; GFX9-NEXT:    s_lshr_b32 s6, s7, s6
419; GFX9-NEXT:    s_lshr_b32 s11, s11, 1
420; GFX9-NEXT:    s_or_b32 s1, s1, s6
421; GFX9-NEXT:    s_andn2_b32 s5, 31, s0
422; GFX9-NEXT:    s_and_b32 s0, s0, 31
423; GFX9-NEXT:    s_lshr_b32 s6, s8, 1
424; GFX9-NEXT:    s_lshr_b32 s11, s11, s14
425; GFX9-NEXT:    s_lshr_b32 s5, s6, s5
426; GFX9-NEXT:    s_lshl_b32 s0, s4, s0
427; GFX9-NEXT:    s_or_b32 s3, s3, s11
428; GFX9-NEXT:    s_or_b32 s0, s0, s5
429; GFX9-NEXT:    v_mov_b32_e32 v0, s0
430; GFX9-NEXT:    v_mov_b32_e32 v1, s1
431; GFX9-NEXT:    v_mov_b32_e32 v2, s2
432; GFX9-NEXT:    v_mov_b32_e32 v3, s3
433; GFX9-NEXT:    global_store_dwordx4 v[4:5], v[0:3], off
434; GFX9-NEXT:    s_endpgm
435;
436; R600-LABEL: fshl_v4i32:
437; R600:       ; %bb.0: ; %entry
438; R600-NEXT:    ALU 35, @4, KC0[CB0:0-32], KC1[]
439; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
440; R600-NEXT:    CF_END
441; R600-NEXT:    PAD
442; R600-NEXT:    ALU clause starting at 4:
443; R600-NEXT:     AND_INT * T0.W, KC0[5].Y, literal.x,
444; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
445; R600-NEXT:     LSHR T0.Z, KC0[4].Z, 1,
446; R600-NEXT:     NOT_INT T1.W, KC0[6].X,
447; R600-NEXT:     AND_INT * T2.W, KC0[6].X, literal.x,
448; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
449; R600-NEXT:     AND_INT T0.X, KC0[5].Z, literal.x,
450; R600-NEXT:     LSHL T0.Y, KC0[4].X, PS,
451; R600-NEXT:     NOT_INT T1.Z, KC0[5].W,
452; R600-NEXT:     AND_INT * T1.W, PV.W, literal.x,
453; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
454; R600-NEXT:     LSHR * T2.W, KC0[5].X, 1,
455; R600-NEXT:     LSHR T1.X, PV.W, T1.W,
456; R600-NEXT:     AND_INT T1.Y, KC0[5].W, literal.x,
457; R600-NEXT:     AND_INT T1.Z, T1.Z, literal.x,
458; R600-NEXT:     LSHR T1.W, KC0[4].W, 1,
459; R600-NEXT:     NOT_INT * T2.W, KC0[5].Z,
460; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
461; R600-NEXT:     AND_INT T2.X, PS, literal.x,
462; R600-NEXT:     LSHR T2.Y, PV.W, PV.Z,
463; R600-NEXT:     LSHL T1.Z, KC0[3].W, PV.Y,
464; R600-NEXT:     NOT_INT T1.W, KC0[5].Y,
465; R600-NEXT:     OR_INT * T2.W, T0.Y, PV.X,
466; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
467; R600-NEXT:     AND_INT T1.X, PV.W, literal.x,
468; R600-NEXT:     LSHR T0.Y, KC0[4].Y, 1,
469; R600-NEXT:     OR_INT T2.Z, PV.Z, PV.Y,
470; R600-NEXT:     LSHR T1.W, T0.Z, PV.X,
471; R600-NEXT:     LSHL * T3.W, KC0[3].Z, T0.X,
472; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
473; R600-NEXT:     OR_INT T2.Y, PS, PV.W,
474; R600-NEXT:     LSHR T1.W, PV.Y, PV.X,
475; R600-NEXT:     LSHL * T0.W, KC0[3].Y, T0.W,
476; R600-NEXT:     OR_INT T2.X, PS, PV.W,
477; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
478; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
479entry:
480  %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
481  store <4 x i32> %0, <4 x i32> addrspace(1)* %in
482  ret void
483}
484
485define amdgpu_kernel void @fshl_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
486; SI-LABEL: fshl_v4i32_imm:
487; SI:       ; %bb.0: ; %entry
488; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
489; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
490; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
491; SI-NEXT:    s_mov_b32 s7, 0xf000
492; SI-NEXT:    s_mov_b32 s6, -1
493; SI-NEXT:    s_waitcnt lgkmcnt(0)
494; SI-NEXT:    v_mov_b32_e32 v0, s3
495; SI-NEXT:    v_alignbit_b32 v3, s11, v0, 31
496; SI-NEXT:    v_mov_b32_e32 v0, s2
497; SI-NEXT:    v_alignbit_b32 v2, s10, v0, 23
498; SI-NEXT:    v_mov_b32_e32 v0, s1
499; SI-NEXT:    v_alignbit_b32 v1, s9, v0, 25
500; SI-NEXT:    v_mov_b32_e32 v0, s0
501; SI-NEXT:    v_alignbit_b32 v0, s8, v0, 31
502; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
503; SI-NEXT:    s_endpgm
504;
505; VI-LABEL: fshl_v4i32_imm:
506; VI:       ; %bb.0: ; %entry
507; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
508; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
509; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x44
510; VI-NEXT:    s_waitcnt lgkmcnt(0)
511; VI-NEXT:    v_mov_b32_e32 v4, s8
512; VI-NEXT:    v_mov_b32_e32 v5, s9
513; VI-NEXT:    v_mov_b32_e32 v0, s3
514; VI-NEXT:    v_mov_b32_e32 v1, s2
515; VI-NEXT:    v_alignbit_b32 v3, s7, v0, 31
516; VI-NEXT:    v_mov_b32_e32 v0, s1
517; VI-NEXT:    v_alignbit_b32 v2, s6, v1, 23
518; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 25
519; VI-NEXT:    v_mov_b32_e32 v0, s0
520; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 31
521; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
522; VI-NEXT:    s_endpgm
523;
524; GFX9-LABEL: fshl_v4i32_imm:
525; GFX9:       ; %bb.0: ; %entry
526; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
527; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
528; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x44
529; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
530; GFX9-NEXT:    v_mov_b32_e32 v4, s8
531; GFX9-NEXT:    v_mov_b32_e32 v5, s9
532; GFX9-NEXT:    v_mov_b32_e32 v0, s3
533; GFX9-NEXT:    v_mov_b32_e32 v1, s2
534; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, 31
535; GFX9-NEXT:    v_mov_b32_e32 v0, s1
536; GFX9-NEXT:    v_alignbit_b32 v2, s6, v1, 23
537; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 25
538; GFX9-NEXT:    v_mov_b32_e32 v0, s0
539; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 31
540; GFX9-NEXT:    global_store_dwordx4 v[4:5], v[0:3], off
541; GFX9-NEXT:    s_endpgm
542;
543; R600-LABEL: fshl_v4i32_imm:
544; R600:       ; %bb.0: ; %entry
545; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
546; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
547; R600-NEXT:    CF_END
548; R600-NEXT:    PAD
549; R600-NEXT:    ALU clause starting at 4:
550; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, literal.x,
551; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
552; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,
553; R600-NEXT:    23(3.222986e-44), 0(0.000000e+00)
554; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,
555; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
556; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, literal.x,
557; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
558; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
559; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
560entry:
561  %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
562  store <4 x i32> %0, <4 x i32> addrspace(1)* %in
563  ret void
564}
565