1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,SI
3; RUN: llc < %s -march=amdgcn -mcpu=tonga  -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,VI
4; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX89,GFX9
5; RUN: llc < %s -march=r600 -mcpu=redwood  -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,R600
6
7declare i32 @llvm.fshl.i32(i32, i32, i32) nounwind readnone
8declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
9declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
10
11define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %z) {
12; SI-LABEL: fshl_i32:
13; SI:       ; %bb.0: ; %entry
14; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
15; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xb
16; SI-NEXT:    s_mov_b32 s7, 0xf000
17; SI-NEXT:    s_mov_b32 s6, -1
18; SI-NEXT:    s_waitcnt lgkmcnt(0)
19; SI-NEXT:    s_sub_i32 s3, 32, s2
20; SI-NEXT:    v_mov_b32_e32 v0, s1
21; SI-NEXT:    s_and_b32 s1, s2, 31
22; SI-NEXT:    v_mov_b32_e32 v1, s3
23; SI-NEXT:    s_cmp_eq_u32 s1, 0
24; SI-NEXT:    v_alignbit_b32 v0, s0, v0, v1
25; SI-NEXT:    v_mov_b32_e32 v1, s0
26; SI-NEXT:    s_cselect_b64 vcc, -1, 0
27; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
28; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
29; SI-NEXT:    s_endpgm
30;
31; VI-LABEL: fshl_i32:
32; VI:       ; %bb.0: ; %entry
33; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
34; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x2c
35; VI-NEXT:    s_waitcnt lgkmcnt(0)
36; VI-NEXT:    s_sub_i32 s3, 32, s2
37; VI-NEXT:    v_mov_b32_e32 v0, s1
38; VI-NEXT:    s_and_b32 s1, s2, 31
39; VI-NEXT:    v_mov_b32_e32 v1, s3
40; VI-NEXT:    s_cmp_eq_u32 s1, 0
41; VI-NEXT:    v_alignbit_b32 v0, s0, v0, v1
42; VI-NEXT:    v_mov_b32_e32 v1, s0
43; VI-NEXT:    s_cselect_b64 vcc, -1, 0
44; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
45; VI-NEXT:    v_mov_b32_e32 v0, s4
46; VI-NEXT:    v_mov_b32_e32 v1, s5
47; VI-NEXT:    flat_store_dword v[0:1], v2
48; VI-NEXT:    s_endpgm
49;
50; GFX9-LABEL: fshl_i32:
51; GFX9:       ; %bb.0: ; %entry
52; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
53; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x2c
54; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
55; GFX9-NEXT:    s_sub_i32 s3, 32, s2
56; GFX9-NEXT:    v_mov_b32_e32 v0, s1
57; GFX9-NEXT:    s_and_b32 s1, s2, 31
58; GFX9-NEXT:    v_mov_b32_e32 v1, s3
59; GFX9-NEXT:    s_cmp_eq_u32 s1, 0
60; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v1
61; GFX9-NEXT:    v_mov_b32_e32 v1, s0
62; GFX9-NEXT:    s_cselect_b64 vcc, -1, 0
63; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
64; GFX9-NEXT:    v_mov_b32_e32 v0, s4
65; GFX9-NEXT:    v_mov_b32_e32 v1, s5
66; GFX9-NEXT:    global_store_dword v[0:1], v2, off
67; GFX9-NEXT:    s_endpgm
68;
69; R600-LABEL: fshl_i32:
70; R600:       ; %bb.0: ; %entry
71; R600-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
72; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
73; R600-NEXT:    CF_END
74; R600-NEXT:    PAD
75; R600-NEXT:    ALU clause starting at 4:
76; R600-NEXT:     SUB_INT * T0.W, literal.x, KC0[3].X,
77; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
78; R600-NEXT:     BIT_ALIGN_INT T0.W, KC0[2].Z, KC0[2].W, PV.W,
79; R600-NEXT:     AND_INT * T1.W, KC0[3].X, literal.x,
80; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
81; R600-NEXT:     CNDE_INT T0.X, PS, KC0[2].Z, PV.W,
82; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
83; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
84entry:
85  %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
86  store i32 %0, i32 addrspace(1)* %in
87  ret void
88}
89
90define amdgpu_kernel void @fshl_i32_imm(i32 addrspace(1)* %in, i32 %x, i32 %y) {
91; SI-LABEL: fshl_i32_imm:
92; SI:       ; %bb.0: ; %entry
93; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
94; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
95; SI-NEXT:    s_mov_b32 s7, 0xf000
96; SI-NEXT:    s_mov_b32 s6, -1
97; SI-NEXT:    s_waitcnt lgkmcnt(0)
98; SI-NEXT:    v_mov_b32_e32 v0, s1
99; SI-NEXT:    v_alignbit_b32 v0, s0, v0, 25
100; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
101; SI-NEXT:    s_endpgm
102;
103; VI-LABEL: fshl_i32_imm:
104; VI:       ; %bb.0: ; %entry
105; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
106; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
107; VI-NEXT:    s_waitcnt lgkmcnt(0)
108; VI-NEXT:    v_mov_b32_e32 v0, s1
109; VI-NEXT:    v_alignbit_b32 v2, s0, v0, 25
110; VI-NEXT:    v_mov_b32_e32 v0, s2
111; VI-NEXT:    v_mov_b32_e32 v1, s3
112; VI-NEXT:    flat_store_dword v[0:1], v2
113; VI-NEXT:    s_endpgm
114;
115; GFX9-LABEL: fshl_i32_imm:
116; GFX9:       ; %bb.0: ; %entry
117; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
118; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x2c
119; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
120; GFX9-NEXT:    v_mov_b32_e32 v0, s1
121; GFX9-NEXT:    v_alignbit_b32 v2, s0, v0, 25
122; GFX9-NEXT:    v_mov_b32_e32 v0, s2
123; GFX9-NEXT:    v_mov_b32_e32 v1, s3
124; GFX9-NEXT:    global_store_dword v[0:1], v2, off
125; GFX9-NEXT:    s_endpgm
126;
127; R600-LABEL: fshl_i32_imm:
128; R600:       ; %bb.0: ; %entry
129; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
130; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
131; R600-NEXT:    CF_END
132; R600-NEXT:    PAD
133; R600-NEXT:    ALU clause starting at 4:
134; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
135; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
136; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,
137; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
138entry:
139  %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 7)
140  store i32 %0, i32 addrspace(1)* %in
141  ret void
142}
143
144define amdgpu_kernel void @fshl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
145; SI-LABEL: fshl_v2i32:
146; SI:       ; %bb.0: ; %entry
147; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
148; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
149; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
150; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xf
151; SI-NEXT:    s_mov_b32 s7, 0xf000
152; SI-NEXT:    s_mov_b32 s6, -1
153; SI-NEXT:    s_waitcnt lgkmcnt(0)
154; SI-NEXT:    v_mov_b32_e32 v0, s9
155; SI-NEXT:    s_sub_i32 s10, 32, s1
156; SI-NEXT:    s_and_b32 s1, s1, 31
157; SI-NEXT:    v_mov_b32_e32 v1, s10
158; SI-NEXT:    s_cmp_eq_u32 s1, 0
159; SI-NEXT:    v_alignbit_b32 v0, s3, v0, v1
160; SI-NEXT:    s_cselect_b64 vcc, -1, 0
161; SI-NEXT:    v_mov_b32_e32 v1, s3
162; SI-NEXT:    s_sub_i32 s1, 32, s0
163; SI-NEXT:    s_and_b32 s0, s0, 31
164; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
165; SI-NEXT:    s_cmp_eq_u32 s0, 0
166; SI-NEXT:    v_mov_b32_e32 v0, s8
167; SI-NEXT:    v_mov_b32_e32 v2, s1
168; SI-NEXT:    v_alignbit_b32 v0, s2, v0, v2
169; SI-NEXT:    v_mov_b32_e32 v2, s2
170; SI-NEXT:    s_cselect_b64 vcc, -1, 0
171; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
172; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
173; SI-NEXT:    s_endpgm
174;
175; VI-LABEL: fshl_v2i32:
176; VI:       ; %bb.0: ; %entry
177; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
178; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
179; VI-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
180; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
181; VI-NEXT:    s_waitcnt lgkmcnt(0)
182; VI-NEXT:    v_mov_b32_e32 v0, s7
183; VI-NEXT:    s_sub_i32 s8, 32, s1
184; VI-NEXT:    s_and_b32 s1, s1, 31
185; VI-NEXT:    v_mov_b32_e32 v1, s8
186; VI-NEXT:    s_cmp_eq_u32 s1, 0
187; VI-NEXT:    v_alignbit_b32 v0, s5, v0, v1
188; VI-NEXT:    s_cselect_b64 vcc, -1, 0
189; VI-NEXT:    v_mov_b32_e32 v1, s5
190; VI-NEXT:    s_sub_i32 s1, 32, s0
191; VI-NEXT:    s_and_b32 s0, s0, 31
192; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
193; VI-NEXT:    s_cmp_eq_u32 s0, 0
194; VI-NEXT:    v_mov_b32_e32 v0, s6
195; VI-NEXT:    v_mov_b32_e32 v2, s1
196; VI-NEXT:    v_alignbit_b32 v0, s4, v0, v2
197; VI-NEXT:    v_mov_b32_e32 v2, s4
198; VI-NEXT:    s_cselect_b64 vcc, -1, 0
199; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
200; VI-NEXT:    v_mov_b32_e32 v2, s2
201; VI-NEXT:    v_mov_b32_e32 v3, s3
202; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
203; VI-NEXT:    s_endpgm
204;
205; GFX9-LABEL: fshl_v2i32:
206; GFX9:       ; %bb.0: ; %entry
207; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
208; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
209; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
210; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
211; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
212; GFX9-NEXT:    v_mov_b32_e32 v0, s7
213; GFX9-NEXT:    s_sub_i32 s8, 32, s1
214; GFX9-NEXT:    s_and_b32 s1, s1, 31
215; GFX9-NEXT:    v_mov_b32_e32 v1, s8
216; GFX9-NEXT:    s_cmp_eq_u32 s1, 0
217; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, v1
218; GFX9-NEXT:    s_cselect_b64 vcc, -1, 0
219; GFX9-NEXT:    v_mov_b32_e32 v1, s5
220; GFX9-NEXT:    s_sub_i32 s1, 32, s0
221; GFX9-NEXT:    s_and_b32 s0, s0, 31
222; GFX9-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
223; GFX9-NEXT:    s_cmp_eq_u32 s0, 0
224; GFX9-NEXT:    v_mov_b32_e32 v0, s6
225; GFX9-NEXT:    v_mov_b32_e32 v2, s1
226; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v2
227; GFX9-NEXT:    v_mov_b32_e32 v2, s4
228; GFX9-NEXT:    s_cselect_b64 vcc, -1, 0
229; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
230; GFX9-NEXT:    v_mov_b32_e32 v2, s2
231; GFX9-NEXT:    v_mov_b32_e32 v3, s3
232; GFX9-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
233; GFX9-NEXT:    s_endpgm
234;
235; R600-LABEL: fshl_v2i32:
236; R600:       ; %bb.0: ; %entry
237; R600-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
238; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
239; R600-NEXT:    CF_END
240; R600-NEXT:    PAD
241; R600-NEXT:    ALU clause starting at 4:
242; R600-NEXT:     AND_INT T0.W, KC0[4].X, literal.x,
243; R600-NEXT:     SUB_INT * T1.W, literal.y, KC0[4].X,
244; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
245; R600-NEXT:     AND_INT T0.Y, KC0[3].W, literal.x,
246; R600-NEXT:     SUB_INT T0.Z, literal.y, KC0[3].W,
247; R600-NEXT:     BIT_ALIGN_INT T1.W, KC0[3].X, KC0[3].Z, PS,
248; R600-NEXT:     SETE_INT * T0.W, PV.W, 0.0,
249; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
250; R600-NEXT:     CNDE_INT T1.Y, PS, PV.W, KC0[3].X,
251; R600-NEXT:     BIT_ALIGN_INT T0.W, KC0[2].W, KC0[3].Y, PV.Z,
252; R600-NEXT:     SETE_INT * T1.W, PV.Y, 0.0,
253; R600-NEXT:     CNDE_INT T1.X, PS, PV.W, KC0[2].W,
254; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
255; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
256entry:
257  %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
258  store <2 x i32> %0, <2 x i32> addrspace(1)* %in
259  ret void
260}
261
262define amdgpu_kernel void @fshl_v2i32_imm(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) {
263; SI-LABEL: fshl_v2i32_imm:
264; SI:       ; %bb.0: ; %entry
265; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
266; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
267; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
268; SI-NEXT:    s_mov_b32 s7, 0xf000
269; SI-NEXT:    s_mov_b32 s6, -1
270; SI-NEXT:    s_waitcnt lgkmcnt(0)
271; SI-NEXT:    v_mov_b32_e32 v0, s1
272; SI-NEXT:    v_alignbit_b32 v1, s3, v0, 23
273; SI-NEXT:    v_mov_b32_e32 v0, s0
274; SI-NEXT:    v_alignbit_b32 v0, s2, v0, 25
275; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
276; SI-NEXT:    s_endpgm
277;
278; VI-LABEL: fshl_v2i32_imm:
279; VI:       ; %bb.0: ; %entry
280; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
281; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
282; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
283; VI-NEXT:    s_waitcnt lgkmcnt(0)
284; VI-NEXT:    v_mov_b32_e32 v0, s1
285; VI-NEXT:    v_mov_b32_e32 v2, s0
286; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 23
287; VI-NEXT:    v_alignbit_b32 v0, s4, v2, 25
288; VI-NEXT:    v_mov_b32_e32 v2, s2
289; VI-NEXT:    v_mov_b32_e32 v3, s3
290; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
291; VI-NEXT:    s_endpgm
292;
293; GFX9-LABEL: fshl_v2i32_imm:
294; GFX9:       ; %bb.0: ; %entry
295; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
296; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
297; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
298; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
299; GFX9-NEXT:    v_mov_b32_e32 v0, s1
300; GFX9-NEXT:    v_mov_b32_e32 v2, s0
301; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 23
302; GFX9-NEXT:    v_alignbit_b32 v0, s4, v2, 25
303; GFX9-NEXT:    v_mov_b32_e32 v2, s2
304; GFX9-NEXT:    v_mov_b32_e32 v3, s3
305; GFX9-NEXT:    global_store_dwordx2 v[2:3], v[0:1], off
306; GFX9-NEXT:    s_endpgm
307;
308; R600-LABEL: fshl_v2i32_imm:
309; R600:       ; %bb.0: ; %entry
310; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
311; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
312; R600-NEXT:    CF_END
313; R600-NEXT:    PAD
314; R600-NEXT:    ALU clause starting at 4:
315; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
316; R600-NEXT:    23(3.222986e-44), 0(0.000000e+00)
317; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
318; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
319; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
320; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
321entry:
322  %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
323  store <2 x i32> %0, <2 x i32> addrspace(1)* %in
324  ret void
325}
326
327define amdgpu_kernel void @fshl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
328; SI-LABEL: fshl_v4i32:
329; SI:       ; %bb.0: ; %entry
330; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
331; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
332; SI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x11
333; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x15
334; SI-NEXT:    s_mov_b32 s7, 0xf000
335; SI-NEXT:    s_mov_b32 s6, -1
336; SI-NEXT:    s_waitcnt lgkmcnt(0)
337; SI-NEXT:    v_mov_b32_e32 v0, s15
338; SI-NEXT:    s_sub_i32 s16, 32, s3
339; SI-NEXT:    s_and_b32 s3, s3, 31
340; SI-NEXT:    v_mov_b32_e32 v1, s16
341; SI-NEXT:    s_cmp_eq_u32 s3, 0
342; SI-NEXT:    v_alignbit_b32 v0, s11, v0, v1
343; SI-NEXT:    s_cselect_b64 vcc, -1, 0
344; SI-NEXT:    v_mov_b32_e32 v1, s11
345; SI-NEXT:    s_sub_i32 s3, 32, s2
346; SI-NEXT:    s_and_b32 s2, s2, 31
347; SI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
348; SI-NEXT:    s_cmp_eq_u32 s2, 0
349; SI-NEXT:    v_mov_b32_e32 v0, s14
350; SI-NEXT:    v_mov_b32_e32 v1, s3
351; SI-NEXT:    v_alignbit_b32 v0, s10, v0, v1
352; SI-NEXT:    s_cselect_b64 vcc, -1, 0
353; SI-NEXT:    v_mov_b32_e32 v1, s10
354; SI-NEXT:    s_sub_i32 s2, 32, s1
355; SI-NEXT:    s_and_b32 s1, s1, 31
356; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
357; SI-NEXT:    s_cmp_eq_u32 s1, 0
358; SI-NEXT:    v_mov_b32_e32 v0, s13
359; SI-NEXT:    v_mov_b32_e32 v1, s2
360; SI-NEXT:    v_alignbit_b32 v0, s9, v0, v1
361; SI-NEXT:    s_cselect_b64 vcc, -1, 0
362; SI-NEXT:    v_mov_b32_e32 v1, s9
363; SI-NEXT:    s_sub_i32 s1, 32, s0
364; SI-NEXT:    s_and_b32 s0, s0, 31
365; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
366; SI-NEXT:    s_cmp_eq_u32 s0, 0
367; SI-NEXT:    v_mov_b32_e32 v0, s12
368; SI-NEXT:    v_mov_b32_e32 v4, s1
369; SI-NEXT:    v_alignbit_b32 v0, s8, v0, v4
370; SI-NEXT:    v_mov_b32_e32 v4, s8
371; SI-NEXT:    s_cselect_b64 vcc, -1, 0
372; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
373; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
374; SI-NEXT:    s_endpgm
375;
376; VI-LABEL: fshl_v4i32:
377; VI:       ; %bb.0: ; %entry
378; VI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
379; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
380; VI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
381; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
382; VI-NEXT:    s_waitcnt lgkmcnt(0)
383; VI-NEXT:    v_mov_b32_e32 v0, s11
384; VI-NEXT:    s_sub_i32 s14, 32, s3
385; VI-NEXT:    s_and_b32 s3, s3, 31
386; VI-NEXT:    v_mov_b32_e32 v1, s14
387; VI-NEXT:    s_cmp_eq_u32 s3, 0
388; VI-NEXT:    v_alignbit_b32 v0, s7, v0, v1
389; VI-NEXT:    s_cselect_b64 vcc, -1, 0
390; VI-NEXT:    v_mov_b32_e32 v1, s7
391; VI-NEXT:    s_sub_i32 s3, 32, s2
392; VI-NEXT:    s_and_b32 s2, s2, 31
393; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
394; VI-NEXT:    s_cmp_eq_u32 s2, 0
395; VI-NEXT:    v_mov_b32_e32 v0, s10
396; VI-NEXT:    v_mov_b32_e32 v1, s3
397; VI-NEXT:    v_alignbit_b32 v0, s6, v0, v1
398; VI-NEXT:    s_cselect_b64 vcc, -1, 0
399; VI-NEXT:    v_mov_b32_e32 v1, s6
400; VI-NEXT:    s_sub_i32 s2, 32, s1
401; VI-NEXT:    s_and_b32 s1, s1, 31
402; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
403; VI-NEXT:    s_cmp_eq_u32 s1, 0
404; VI-NEXT:    v_mov_b32_e32 v0, s9
405; VI-NEXT:    v_mov_b32_e32 v1, s2
406; VI-NEXT:    v_alignbit_b32 v0, s5, v0, v1
407; VI-NEXT:    s_cselect_b64 vcc, -1, 0
408; VI-NEXT:    v_mov_b32_e32 v1, s5
409; VI-NEXT:    s_sub_i32 s1, 32, s0
410; VI-NEXT:    s_and_b32 s0, s0, 31
411; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
412; VI-NEXT:    s_cmp_eq_u32 s0, 0
413; VI-NEXT:    v_mov_b32_e32 v0, s8
414; VI-NEXT:    v_mov_b32_e32 v4, s1
415; VI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
416; VI-NEXT:    v_mov_b32_e32 v4, s4
417; VI-NEXT:    s_cselect_b64 vcc, -1, 0
418; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
419; VI-NEXT:    v_mov_b32_e32 v4, s12
420; VI-NEXT:    v_mov_b32_e32 v5, s13
421; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
422; VI-NEXT:    s_endpgm
423;
424; GFX9-LABEL: fshl_v4i32:
425; GFX9:       ; %bb.0: ; %entry
426; GFX9-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x24
427; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
428; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x44
429; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x54
430; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
431; GFX9-NEXT:    v_mov_b32_e32 v0, s11
432; GFX9-NEXT:    s_sub_i32 s14, 32, s3
433; GFX9-NEXT:    s_and_b32 s3, s3, 31
434; GFX9-NEXT:    v_mov_b32_e32 v1, s14
435; GFX9-NEXT:    s_cmp_eq_u32 s3, 0
436; GFX9-NEXT:    v_alignbit_b32 v0, s7, v0, v1
437; GFX9-NEXT:    s_cselect_b64 vcc, -1, 0
438; GFX9-NEXT:    v_mov_b32_e32 v1, s7
439; GFX9-NEXT:    s_sub_i32 s3, 32, s2
440; GFX9-NEXT:    s_and_b32 s2, s2, 31
441; GFX9-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
442; GFX9-NEXT:    s_cmp_eq_u32 s2, 0
443; GFX9-NEXT:    v_mov_b32_e32 v0, s10
444; GFX9-NEXT:    v_mov_b32_e32 v1, s3
445; GFX9-NEXT:    v_alignbit_b32 v0, s6, v0, v1
446; GFX9-NEXT:    s_cselect_b64 vcc, -1, 0
447; GFX9-NEXT:    v_mov_b32_e32 v1, s6
448; GFX9-NEXT:    s_sub_i32 s2, 32, s1
449; GFX9-NEXT:    s_and_b32 s1, s1, 31
450; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
451; GFX9-NEXT:    s_cmp_eq_u32 s1, 0
452; GFX9-NEXT:    v_mov_b32_e32 v0, s9
453; GFX9-NEXT:    v_mov_b32_e32 v1, s2
454; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, v1
455; GFX9-NEXT:    s_cselect_b64 vcc, -1, 0
456; GFX9-NEXT:    v_mov_b32_e32 v1, s5
457; GFX9-NEXT:    s_sub_i32 s1, 32, s0
458; GFX9-NEXT:    s_and_b32 s0, s0, 31
459; GFX9-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc
460; GFX9-NEXT:    s_cmp_eq_u32 s0, 0
461; GFX9-NEXT:    v_mov_b32_e32 v0, s8
462; GFX9-NEXT:    v_mov_b32_e32 v4, s1
463; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v4
464; GFX9-NEXT:    v_mov_b32_e32 v4, s4
465; GFX9-NEXT:    s_cselect_b64 vcc, -1, 0
466; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
467; GFX9-NEXT:    v_mov_b32_e32 v4, s12
468; GFX9-NEXT:    v_mov_b32_e32 v5, s13
469; GFX9-NEXT:    global_store_dwordx4 v[4:5], v[0:3], off
470; GFX9-NEXT:    s_endpgm
471;
472; R600-LABEL: fshl_v4i32:
473; R600:       ; %bb.0: ; %entry
474; R600-NEXT:    ALU 25, @4, KC0[CB0:0-32], KC1[]
475; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
476; R600-NEXT:    CF_END
477; R600-NEXT:    PAD
478; R600-NEXT:    ALU clause starting at 4:
479; R600-NEXT:     SUB_INT * T0.W, literal.x, KC0[6].X,
480; R600-NEXT:    32(4.484155e-44), 0(0.000000e+00)
481; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, PV.W,
482; R600-NEXT:     AND_INT * T1.W, KC0[6].X, literal.x,
483; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
484; R600-NEXT:     AND_INT T0.X, KC0[5].Z, literal.x,
485; R600-NEXT:     SUB_INT T0.Y, literal.y, KC0[5].Z,
486; R600-NEXT:     SETE_INT T0.Z, PV.W, 0.0,
487; R600-NEXT:     SUB_INT T1.W, literal.y, KC0[5].W,
488; R600-NEXT:     AND_INT * T2.W, KC0[5].W, literal.x,
489; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
490; R600-NEXT:     SETE_INT T1.Z, PS, 0.0,
491; R600-NEXT:     BIT_ALIGN_INT * T1.W, KC0[3].W, KC0[4].W, PV.W,
492; R600-NEXT:     CNDE_INT * T0.W, T0.Z, T0.W, KC0[4].X,
493; R600-NEXT:     CNDE_INT T0.Z, T1.Z, T1.W, KC0[3].W,
494; R600-NEXT:     BIT_ALIGN_INT T1.W, KC0[3].Z, KC0[4].Z, T0.Y,
495; R600-NEXT:     SETE_INT * T2.W, T0.X, 0.0,
496; R600-NEXT:     CNDE_INT T0.Y, PS, PV.W, KC0[3].Z,
497; R600-NEXT:     AND_INT T1.W, KC0[5].Y, literal.x,
498; R600-NEXT:     SUB_INT * T2.W, literal.y, KC0[5].Y,
499; R600-NEXT:    31(4.344025e-44), 32(4.484155e-44)
500; R600-NEXT:     BIT_ALIGN_INT T2.W, KC0[3].Y, KC0[4].Y, PS,
501; R600-NEXT:     SETE_INT * T1.W, PV.W, 0.0,
502; R600-NEXT:     CNDE_INT T0.X, PS, PV.W, KC0[3].Y,
503; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
504; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
505entry:
506  %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
507  store <4 x i32> %0, <4 x i32> addrspace(1)* %in
508  ret void
509}
510
511define amdgpu_kernel void @fshl_v4i32_imm(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) {
512; SI-LABEL: fshl_v4i32_imm:
513; SI:       ; %bb.0: ; %entry
514; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
515; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
516; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
517; SI-NEXT:    s_mov_b32 s7, 0xf000
518; SI-NEXT:    s_mov_b32 s6, -1
519; SI-NEXT:    s_waitcnt lgkmcnt(0)
520; SI-NEXT:    v_mov_b32_e32 v0, s3
521; SI-NEXT:    v_alignbit_b32 v3, s11, v0, 31
522; SI-NEXT:    v_mov_b32_e32 v0, s2
523; SI-NEXT:    v_alignbit_b32 v2, s10, v0, 23
524; SI-NEXT:    v_mov_b32_e32 v0, s1
525; SI-NEXT:    v_alignbit_b32 v1, s9, v0, 25
526; SI-NEXT:    v_mov_b32_e32 v0, s0
527; SI-NEXT:    v_alignbit_b32 v0, s8, v0, 31
528; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
529; SI-NEXT:    s_endpgm
530;
531; VI-LABEL: fshl_v4i32_imm:
532; VI:       ; %bb.0: ; %entry
533; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
534; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
535; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x44
536; VI-NEXT:    s_waitcnt lgkmcnt(0)
537; VI-NEXT:    v_mov_b32_e32 v4, s8
538; VI-NEXT:    v_mov_b32_e32 v5, s9
539; VI-NEXT:    v_mov_b32_e32 v0, s3
540; VI-NEXT:    v_mov_b32_e32 v1, s2
541; VI-NEXT:    v_alignbit_b32 v3, s7, v0, 31
542; VI-NEXT:    v_mov_b32_e32 v0, s1
543; VI-NEXT:    v_alignbit_b32 v2, s6, v1, 23
544; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 25
545; VI-NEXT:    v_mov_b32_e32 v0, s0
546; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 31
547; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
548; VI-NEXT:    s_endpgm
549;
550; GFX9-LABEL: fshl_v4i32_imm:
551; GFX9:       ; %bb.0: ; %entry
552; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
553; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
554; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x44
555; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
556; GFX9-NEXT:    v_mov_b32_e32 v4, s8
557; GFX9-NEXT:    v_mov_b32_e32 v5, s9
558; GFX9-NEXT:    v_mov_b32_e32 v0, s3
559; GFX9-NEXT:    v_mov_b32_e32 v1, s2
560; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, 31
561; GFX9-NEXT:    v_mov_b32_e32 v0, s1
562; GFX9-NEXT:    v_alignbit_b32 v2, s6, v1, 23
563; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 25
564; GFX9-NEXT:    v_mov_b32_e32 v0, s0
565; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 31
566; GFX9-NEXT:    global_store_dwordx4 v[4:5], v[0:3], off
567; GFX9-NEXT:    s_endpgm
568;
569; R600-LABEL: fshl_v4i32_imm:
570; R600:       ; %bb.0: ; %entry
571; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
572; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
573; R600-NEXT:    CF_END
574; R600-NEXT:    PAD
575; R600-NEXT:    ALU clause starting at 4:
576; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, literal.x,
577; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
578; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,
579; R600-NEXT:    23(3.222986e-44), 0(0.000000e+00)
580; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,
581; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
582; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, literal.x,
583; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
584; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
585; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
586entry:
587  %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
588  store <4 x i32> %0, <4 x i32> addrspace(1)* %in
589  ret void
590}
591