1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mattr=+mad-mac-f32-insts -verify-machineinstrs  < %s | FileCheck -check-prefixes=GCN,SI %s
3; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
4; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
5
6define amdgpu_kernel void @frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
7; SI-LABEL: frem_f16:
8; SI:       ; %bb.0:
9; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
10; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
11; SI-NEXT:    s_mov_b32 s3, 0xf000
12; SI-NEXT:    s_mov_b32 s2, -1
13; SI-NEXT:    s_waitcnt lgkmcnt(0)
14; SI-NEXT:    s_mov_b32 s0, s4
15; SI-NEXT:    s_mov_b32 s1, s5
16; SI-NEXT:    s_mov_b32 s4, s6
17; SI-NEXT:    s_mov_b32 s5, s7
18; SI-NEXT:    s_mov_b32 s6, s2
19; SI-NEXT:    s_mov_b32 s7, s3
20; SI-NEXT:    s_mov_b32 s10, s2
21; SI-NEXT:    s_mov_b32 s11, s3
22; SI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
23; SI-NEXT:    s_waitcnt vmcnt(0)
24; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
25; SI-NEXT:    buffer_load_ushort v1, off, s[8:11], 0 offset:8
26; SI-NEXT:    s_waitcnt vmcnt(0)
27; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
28; SI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
29; SI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
30; SI-NEXT:    v_rcp_f32_e32 v4, v3
31; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
32; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
33; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
34; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
35; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
36; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
37; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
38; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
39; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
40; SI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
41; SI-NEXT:    v_trunc_f32_e32 v2, v2
42; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
43; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
44; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
45; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
46; SI-NEXT:    s_endpgm
47;
48; CI-LABEL: frem_f16:
49; CI:       ; %bb.0:
50; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
51; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
52; CI-NEXT:    s_mov_b32 s11, 0xf000
53; CI-NEXT:    s_mov_b32 s10, -1
54; CI-NEXT:    s_mov_b32 s2, s10
55; CI-NEXT:    s_waitcnt lgkmcnt(0)
56; CI-NEXT:    s_mov_b32 s8, s4
57; CI-NEXT:    s_mov_b32 s9, s5
58; CI-NEXT:    s_mov_b32 s4, s6
59; CI-NEXT:    s_mov_b32 s5, s7
60; CI-NEXT:    s_mov_b32 s3, s11
61; CI-NEXT:    s_mov_b32 s6, s10
62; CI-NEXT:    s_mov_b32 s7, s11
63; CI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
64; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
65; CI-NEXT:    s_waitcnt vmcnt(1)
66; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
67; CI-NEXT:    s_waitcnt vmcnt(0)
68; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
69; CI-NEXT:    v_div_scale_f32 v3, s[0:1], v1, v1, v0
70; CI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
71; CI-NEXT:    v_rcp_f32_e32 v4, v3
72; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
73; CI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
74; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
75; CI-NEXT:    v_mul_f32_e32 v5, v2, v4
76; CI-NEXT:    v_fma_f32 v6, -v3, v5, v2
77; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
78; CI-NEXT:    v_fma_f32 v2, -v3, v5, v2
79; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
80; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
81; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
82; CI-NEXT:    v_trunc_f32_e32 v2, v2
83; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
84; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
85; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
86; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
87; CI-NEXT:    s_endpgm
88;
89; VI-LABEL: frem_f16:
90; VI:       ; %bb.0:
91; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
92; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
93; VI-NEXT:    s_waitcnt lgkmcnt(0)
94; VI-NEXT:    v_mov_b32_e32 v2, s6
95; VI-NEXT:    s_add_u32 s0, s0, 8
96; VI-NEXT:    v_mov_b32_e32 v3, s7
97; VI-NEXT:    s_addc_u32 s1, s1, 0
98; VI-NEXT:    flat_load_ushort v4, v[2:3]
99; VI-NEXT:    v_mov_b32_e32 v3, s1
100; VI-NEXT:    v_mov_b32_e32 v2, s0
101; VI-NEXT:    flat_load_ushort v2, v[2:3]
102; VI-NEXT:    v_mov_b32_e32 v0, s4
103; VI-NEXT:    v_mov_b32_e32 v1, s5
104; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
105; VI-NEXT:    v_cvt_f32_f16_e32 v3, v4
106; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
107; VI-NEXT:    v_cvt_f32_f16_e32 v5, v2
108; VI-NEXT:    v_rcp_f32_e32 v5, v5
109; VI-NEXT:    v_mul_f32_e32 v3, v3, v5
110; VI-NEXT:    v_cvt_f16_f32_e32 v3, v3
111; VI-NEXT:    v_div_fixup_f16 v3, v3, v2, v4
112; VI-NEXT:    v_trunc_f16_e32 v3, v3
113; VI-NEXT:    v_fma_f16 v2, -v3, v2, v4
114; VI-NEXT:    flat_store_short v[0:1], v2
115; VI-NEXT:    s_endpgm
116                      half addrspace(1)* %in2) #0 {
117   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
118   %r0 = load half, half addrspace(1)* %in1, align 4
119   %r1 = load half, half addrspace(1)* %gep2, align 4
120   %r2 = frem half %r0, %r1
121   store half %r2, half addrspace(1)* %out, align 4
122   ret void
123}
124
125define amdgpu_kernel void @fast_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
126; SI-LABEL: fast_frem_f16:
127; SI:       ; %bb.0:
128; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
129; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
130; SI-NEXT:    s_mov_b32 s3, 0xf000
131; SI-NEXT:    s_mov_b32 s2, -1
132; SI-NEXT:    s_waitcnt lgkmcnt(0)
133; SI-NEXT:    s_mov_b32 s0, s4
134; SI-NEXT:    s_mov_b32 s1, s5
135; SI-NEXT:    s_mov_b32 s4, s6
136; SI-NEXT:    s_mov_b32 s5, s7
137; SI-NEXT:    s_mov_b32 s6, s2
138; SI-NEXT:    s_mov_b32 s7, s3
139; SI-NEXT:    s_mov_b32 s10, s2
140; SI-NEXT:    s_mov_b32 s11, s3
141; SI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
142; SI-NEXT:    s_waitcnt vmcnt(0)
143; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
144; SI-NEXT:    buffer_load_ushort v1, off, s[8:11], 0 offset:8
145; SI-NEXT:    s_waitcnt vmcnt(0)
146; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
147; SI-NEXT:    v_rcp_f32_e32 v2, v1
148; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
149; SI-NEXT:    v_trunc_f32_e32 v2, v2
150; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
151; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
152; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
153; SI-NEXT:    s_endpgm
154;
155; CI-LABEL: fast_frem_f16:
156; CI:       ; %bb.0:
157; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
158; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
159; CI-NEXT:    s_mov_b32 s11, 0xf000
160; CI-NEXT:    s_mov_b32 s10, -1
161; CI-NEXT:    s_mov_b32 s2, s10
162; CI-NEXT:    s_mov_b32 s3, s11
163; CI-NEXT:    s_waitcnt lgkmcnt(0)
164; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
165; CI-NEXT:    s_mov_b32 s8, s4
166; CI-NEXT:    s_mov_b32 s9, s5
167; CI-NEXT:    s_mov_b32 s4, s6
168; CI-NEXT:    s_mov_b32 s5, s7
169; CI-NEXT:    s_mov_b32 s6, s10
170; CI-NEXT:    s_mov_b32 s7, s11
171; CI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
172; CI-NEXT:    s_waitcnt vmcnt(1)
173; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
174; CI-NEXT:    v_rcp_f32_e32 v2, v1
175; CI-NEXT:    s_waitcnt vmcnt(0)
176; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
177; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
178; CI-NEXT:    v_trunc_f32_e32 v2, v2
179; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
180; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
181; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
182; CI-NEXT:    s_endpgm
183;
184; VI-LABEL: fast_frem_f16:
185; VI:       ; %bb.0:
186; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
187; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
188; VI-NEXT:    s_waitcnt lgkmcnt(0)
189; VI-NEXT:    v_mov_b32_e32 v2, s6
190; VI-NEXT:    s_add_u32 s0, s0, 8
191; VI-NEXT:    v_mov_b32_e32 v3, s7
192; VI-NEXT:    s_addc_u32 s1, s1, 0
193; VI-NEXT:    flat_load_ushort v4, v[2:3]
194; VI-NEXT:    v_mov_b32_e32 v3, s1
195; VI-NEXT:    v_mov_b32_e32 v2, s0
196; VI-NEXT:    flat_load_ushort v2, v[2:3]
197; VI-NEXT:    v_mov_b32_e32 v0, s4
198; VI-NEXT:    v_mov_b32_e32 v1, s5
199; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
200; VI-NEXT:    v_rcp_f16_e32 v3, v2
201; VI-NEXT:    v_mul_f16_e32 v3, v4, v3
202; VI-NEXT:    v_trunc_f16_e32 v3, v3
203; VI-NEXT:    v_fma_f16 v2, -v3, v2, v4
204; VI-NEXT:    flat_store_short v[0:1], v2
205; VI-NEXT:    s_endpgm
206                      half addrspace(1)* %in2) #0 {
207   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
208   %r0 = load half, half addrspace(1)* %in1, align 4
209   %r1 = load half, half addrspace(1)* %gep2, align 4
210   %r2 = frem fast half %r0, %r1
211   store half %r2, half addrspace(1)* %out, align 4
212   ret void
213}
214
215define amdgpu_kernel void @unsafe_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
216; SI-LABEL: unsafe_frem_f16:
217; SI:       ; %bb.0:
218; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
219; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
220; SI-NEXT:    s_mov_b32 s3, 0xf000
221; SI-NEXT:    s_mov_b32 s2, -1
222; SI-NEXT:    s_waitcnt lgkmcnt(0)
223; SI-NEXT:    s_mov_b32 s0, s4
224; SI-NEXT:    s_mov_b32 s1, s5
225; SI-NEXT:    s_mov_b32 s4, s6
226; SI-NEXT:    s_mov_b32 s5, s7
227; SI-NEXT:    s_mov_b32 s6, s2
228; SI-NEXT:    s_mov_b32 s7, s3
229; SI-NEXT:    s_mov_b32 s10, s2
230; SI-NEXT:    s_mov_b32 s11, s3
231; SI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
232; SI-NEXT:    s_waitcnt vmcnt(0)
233; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
234; SI-NEXT:    buffer_load_ushort v1, off, s[8:11], 0 offset:8
235; SI-NEXT:    s_waitcnt vmcnt(0)
236; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
237; SI-NEXT:    v_rcp_f32_e32 v2, v1
238; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
239; SI-NEXT:    v_trunc_f32_e32 v2, v2
240; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
241; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
242; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
243; SI-NEXT:    s_endpgm
244;
245; CI-LABEL: unsafe_frem_f16:
246; CI:       ; %bb.0:
247; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
248; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
249; CI-NEXT:    s_mov_b32 s11, 0xf000
250; CI-NEXT:    s_mov_b32 s10, -1
251; CI-NEXT:    s_mov_b32 s2, s10
252; CI-NEXT:    s_mov_b32 s3, s11
253; CI-NEXT:    s_waitcnt lgkmcnt(0)
254; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
255; CI-NEXT:    s_mov_b32 s8, s4
256; CI-NEXT:    s_mov_b32 s9, s5
257; CI-NEXT:    s_mov_b32 s4, s6
258; CI-NEXT:    s_mov_b32 s5, s7
259; CI-NEXT:    s_mov_b32 s6, s10
260; CI-NEXT:    s_mov_b32 s7, s11
261; CI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
262; CI-NEXT:    s_waitcnt vmcnt(1)
263; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
264; CI-NEXT:    v_rcp_f32_e32 v2, v1
265; CI-NEXT:    s_waitcnt vmcnt(0)
266; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
267; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
268; CI-NEXT:    v_trunc_f32_e32 v2, v2
269; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
270; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
271; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
272; CI-NEXT:    s_endpgm
273;
274; VI-LABEL: unsafe_frem_f16:
275; VI:       ; %bb.0:
276; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
277; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
278; VI-NEXT:    s_waitcnt lgkmcnt(0)
279; VI-NEXT:    v_mov_b32_e32 v2, s6
280; VI-NEXT:    s_add_u32 s0, s0, 8
281; VI-NEXT:    v_mov_b32_e32 v3, s7
282; VI-NEXT:    s_addc_u32 s1, s1, 0
283; VI-NEXT:    flat_load_ushort v4, v[2:3]
284; VI-NEXT:    v_mov_b32_e32 v3, s1
285; VI-NEXT:    v_mov_b32_e32 v2, s0
286; VI-NEXT:    flat_load_ushort v2, v[2:3]
287; VI-NEXT:    v_mov_b32_e32 v0, s4
288; VI-NEXT:    v_mov_b32_e32 v1, s5
289; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
290; VI-NEXT:    v_rcp_f16_e32 v3, v2
291; VI-NEXT:    v_mul_f16_e32 v3, v4, v3
292; VI-NEXT:    v_trunc_f16_e32 v3, v3
293; VI-NEXT:    v_fma_f16 v2, -v3, v2, v4
294; VI-NEXT:    flat_store_short v[0:1], v2
295; VI-NEXT:    s_endpgm
296                             half addrspace(1)* %in2) #1 {
297   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
298   %r0 = load half, half addrspace(1)* %in1, align 4
299   %r1 = load half, half addrspace(1)* %gep2, align 4
300   %r2 = frem half %r0, %r1
301   store half %r2, half addrspace(1)* %out, align 4
302   ret void
303}
304
305define amdgpu_kernel void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
306; SI-LABEL: frem_f32:
307; SI:       ; %bb.0:
308; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
309; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
310; SI-NEXT:    s_mov_b32 s3, 0xf000
311; SI-NEXT:    s_mov_b32 s2, -1
312; SI-NEXT:    s_waitcnt lgkmcnt(0)
313; SI-NEXT:    s_mov_b32 s0, s4
314; SI-NEXT:    s_mov_b32 s1, s5
315; SI-NEXT:    s_mov_b32 s4, s6
316; SI-NEXT:    s_mov_b32 s5, s7
317; SI-NEXT:    s_mov_b32 s6, s2
318; SI-NEXT:    s_mov_b32 s7, s3
319; SI-NEXT:    s_mov_b32 s10, s2
320; SI-NEXT:    s_mov_b32 s11, s3
321; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
322; SI-NEXT:    buffer_load_dword v1, off, s[8:11], 0 offset:16
323; SI-NEXT:    s_waitcnt vmcnt(0)
324; SI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
325; SI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
326; SI-NEXT:    v_rcp_f32_e32 v4, v3
327; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
328; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
329; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
330; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
331; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
332; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
333; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
334; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
335; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
336; SI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
337; SI-NEXT:    v_trunc_f32_e32 v2, v2
338; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
339; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
340; SI-NEXT:    s_endpgm
341;
342; CI-LABEL: frem_f32:
343; CI:       ; %bb.0:
344; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
345; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
346; CI-NEXT:    s_mov_b32 s11, 0xf000
347; CI-NEXT:    s_mov_b32 s10, -1
348; CI-NEXT:    s_mov_b32 s2, s10
349; CI-NEXT:    s_waitcnt lgkmcnt(0)
350; CI-NEXT:    s_mov_b32 s8, s4
351; CI-NEXT:    s_mov_b32 s9, s5
352; CI-NEXT:    s_mov_b32 s4, s6
353; CI-NEXT:    s_mov_b32 s5, s7
354; CI-NEXT:    s_mov_b32 s6, s10
355; CI-NEXT:    s_mov_b32 s7, s11
356; CI-NEXT:    s_mov_b32 s3, s11
357; CI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
358; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:16
359; CI-NEXT:    s_waitcnt vmcnt(0)
360; CI-NEXT:    v_div_scale_f32 v3, s[0:1], v1, v1, v0
361; CI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
362; CI-NEXT:    v_rcp_f32_e32 v4, v3
363; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
364; CI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
365; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
366; CI-NEXT:    v_mul_f32_e32 v5, v2, v4
367; CI-NEXT:    v_fma_f32 v6, -v3, v5, v2
368; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
369; CI-NEXT:    v_fma_f32 v2, -v3, v5, v2
370; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
371; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
372; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
373; CI-NEXT:    v_trunc_f32_e32 v2, v2
374; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
375; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
376; CI-NEXT:    s_endpgm
377;
378; VI-LABEL: frem_f32:
379; VI:       ; %bb.0:
380; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
381; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
382; VI-NEXT:    s_waitcnt lgkmcnt(0)
383; VI-NEXT:    v_mov_b32_e32 v2, s6
384; VI-NEXT:    s_add_u32 s0, s0, 16
385; VI-NEXT:    v_mov_b32_e32 v3, s7
386; VI-NEXT:    s_addc_u32 s1, s1, 0
387; VI-NEXT:    flat_load_dword v4, v[2:3]
388; VI-NEXT:    v_mov_b32_e32 v3, s1
389; VI-NEXT:    v_mov_b32_e32 v2, s0
390; VI-NEXT:    flat_load_dword v2, v[2:3]
391; VI-NEXT:    v_mov_b32_e32 v0, s4
392; VI-NEXT:    v_mov_b32_e32 v1, s5
393; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
394; VI-NEXT:    v_div_scale_f32 v5, s[0:1], v2, v2, v4
395; VI-NEXT:    v_div_scale_f32 v3, vcc, v4, v2, v4
396; VI-NEXT:    v_rcp_f32_e32 v6, v5
397; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
398; VI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
399; VI-NEXT:    v_fma_f32 v6, v7, v6, v6
400; VI-NEXT:    v_mul_f32_e32 v7, v3, v6
401; VI-NEXT:    v_fma_f32 v8, -v5, v7, v3
402; VI-NEXT:    v_fma_f32 v7, v8, v6, v7
403; VI-NEXT:    v_fma_f32 v3, -v5, v7, v3
404; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
405; VI-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
406; VI-NEXT:    v_div_fixup_f32 v3, v3, v2, v4
407; VI-NEXT:    v_trunc_f32_e32 v3, v3
408; VI-NEXT:    v_fma_f32 v2, -v3, v2, v4
409; VI-NEXT:    flat_store_dword v[0:1], v2
410; VI-NEXT:    s_endpgm
411                      float addrspace(1)* %in2) #0 {
412   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
413   %r0 = load float, float addrspace(1)* %in1, align 4
414   %r1 = load float, float addrspace(1)* %gep2, align 4
415   %r2 = frem float %r0, %r1
416   store float %r2, float addrspace(1)* %out, align 4
417   ret void
418}
419
420define amdgpu_kernel void @fast_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
421; SI-LABEL: fast_frem_f32:
422; SI:       ; %bb.0:
423; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
424; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
425; SI-NEXT:    s_mov_b32 s3, 0xf000
426; SI-NEXT:    s_mov_b32 s2, -1
427; SI-NEXT:    s_waitcnt lgkmcnt(0)
428; SI-NEXT:    s_mov_b32 s0, s4
429; SI-NEXT:    s_mov_b32 s1, s5
430; SI-NEXT:    s_mov_b32 s4, s6
431; SI-NEXT:    s_mov_b32 s5, s7
432; SI-NEXT:    s_mov_b32 s6, s2
433; SI-NEXT:    s_mov_b32 s7, s3
434; SI-NEXT:    s_mov_b32 s10, s2
435; SI-NEXT:    s_mov_b32 s11, s3
436; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
437; SI-NEXT:    buffer_load_dword v1, off, s[8:11], 0 offset:16
438; SI-NEXT:    s_waitcnt vmcnt(0)
439; SI-NEXT:    v_rcp_f32_e32 v2, v1
440; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
441; SI-NEXT:    v_trunc_f32_e32 v2, v2
442; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
443; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
444; SI-NEXT:    s_endpgm
445;
446; CI-LABEL: fast_frem_f32:
447; CI:       ; %bb.0:
448; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
449; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
450; CI-NEXT:    s_mov_b32 s11, 0xf000
451; CI-NEXT:    s_mov_b32 s10, -1
452; CI-NEXT:    s_mov_b32 s2, s10
453; CI-NEXT:    s_waitcnt lgkmcnt(0)
454; CI-NEXT:    s_mov_b32 s8, s4
455; CI-NEXT:    s_mov_b32 s9, s5
456; CI-NEXT:    s_mov_b32 s4, s6
457; CI-NEXT:    s_mov_b32 s5, s7
458; CI-NEXT:    s_mov_b32 s6, s10
459; CI-NEXT:    s_mov_b32 s7, s11
460; CI-NEXT:    s_mov_b32 s3, s11
461; CI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
462; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:16
463; CI-NEXT:    s_waitcnt vmcnt(0)
464; CI-NEXT:    v_rcp_f32_e32 v2, v1
465; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
466; CI-NEXT:    v_trunc_f32_e32 v2, v2
467; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
468; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
469; CI-NEXT:    s_endpgm
470;
471; VI-LABEL: fast_frem_f32:
472; VI:       ; %bb.0:
473; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
474; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
475; VI-NEXT:    s_waitcnt lgkmcnt(0)
476; VI-NEXT:    v_mov_b32_e32 v2, s6
477; VI-NEXT:    s_add_u32 s0, s0, 16
478; VI-NEXT:    v_mov_b32_e32 v3, s7
479; VI-NEXT:    s_addc_u32 s1, s1, 0
480; VI-NEXT:    flat_load_dword v4, v[2:3]
481; VI-NEXT:    v_mov_b32_e32 v3, s1
482; VI-NEXT:    v_mov_b32_e32 v2, s0
483; VI-NEXT:    flat_load_dword v2, v[2:3]
484; VI-NEXT:    v_mov_b32_e32 v0, s4
485; VI-NEXT:    v_mov_b32_e32 v1, s5
486; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
487; VI-NEXT:    v_rcp_f32_e32 v3, v2
488; VI-NEXT:    v_mul_f32_e32 v3, v4, v3
489; VI-NEXT:    v_trunc_f32_e32 v3, v3
490; VI-NEXT:    v_fma_f32 v2, -v3, v2, v4
491; VI-NEXT:    flat_store_dword v[0:1], v2
492; VI-NEXT:    s_endpgm
493                      float addrspace(1)* %in2) #0 {
494   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
495   %r0 = load float, float addrspace(1)* %in1, align 4
496   %r1 = load float, float addrspace(1)* %gep2, align 4
497   %r2 = frem fast float %r0, %r1
498   store float %r2, float addrspace(1)* %out, align 4
499   ret void
500}
501
502define amdgpu_kernel void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
503; SI-LABEL: unsafe_frem_f32:
504; SI:       ; %bb.0:
505; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
506; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
507; SI-NEXT:    s_mov_b32 s3, 0xf000
508; SI-NEXT:    s_mov_b32 s2, -1
509; SI-NEXT:    s_waitcnt lgkmcnt(0)
510; SI-NEXT:    s_mov_b32 s0, s4
511; SI-NEXT:    s_mov_b32 s1, s5
512; SI-NEXT:    s_mov_b32 s4, s6
513; SI-NEXT:    s_mov_b32 s5, s7
514; SI-NEXT:    s_mov_b32 s6, s2
515; SI-NEXT:    s_mov_b32 s7, s3
516; SI-NEXT:    s_mov_b32 s10, s2
517; SI-NEXT:    s_mov_b32 s11, s3
518; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
519; SI-NEXT:    buffer_load_dword v1, off, s[8:11], 0 offset:16
520; SI-NEXT:    s_waitcnt vmcnt(0)
521; SI-NEXT:    v_rcp_f32_e32 v2, v1
522; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
523; SI-NEXT:    v_trunc_f32_e32 v2, v2
524; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
525; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
526; SI-NEXT:    s_endpgm
527;
528; CI-LABEL: unsafe_frem_f32:
529; CI:       ; %bb.0:
530; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
531; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
532; CI-NEXT:    s_mov_b32 s11, 0xf000
533; CI-NEXT:    s_mov_b32 s10, -1
534; CI-NEXT:    s_mov_b32 s2, s10
535; CI-NEXT:    s_waitcnt lgkmcnt(0)
536; CI-NEXT:    s_mov_b32 s8, s4
537; CI-NEXT:    s_mov_b32 s9, s5
538; CI-NEXT:    s_mov_b32 s4, s6
539; CI-NEXT:    s_mov_b32 s5, s7
540; CI-NEXT:    s_mov_b32 s6, s10
541; CI-NEXT:    s_mov_b32 s7, s11
542; CI-NEXT:    s_mov_b32 s3, s11
543; CI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
544; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:16
545; CI-NEXT:    s_waitcnt vmcnt(0)
546; CI-NEXT:    v_rcp_f32_e32 v2, v1
547; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
548; CI-NEXT:    v_trunc_f32_e32 v2, v2
549; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
550; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
551; CI-NEXT:    s_endpgm
552;
553; VI-LABEL: unsafe_frem_f32:
554; VI:       ; %bb.0:
555; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
556; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
557; VI-NEXT:    s_waitcnt lgkmcnt(0)
558; VI-NEXT:    v_mov_b32_e32 v2, s6
559; VI-NEXT:    s_add_u32 s0, s0, 16
560; VI-NEXT:    v_mov_b32_e32 v3, s7
561; VI-NEXT:    s_addc_u32 s1, s1, 0
562; VI-NEXT:    flat_load_dword v4, v[2:3]
563; VI-NEXT:    v_mov_b32_e32 v3, s1
564; VI-NEXT:    v_mov_b32_e32 v2, s0
565; VI-NEXT:    flat_load_dword v2, v[2:3]
566; VI-NEXT:    v_mov_b32_e32 v0, s4
567; VI-NEXT:    v_mov_b32_e32 v1, s5
568; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
569; VI-NEXT:    v_rcp_f32_e32 v3, v2
570; VI-NEXT:    v_mul_f32_e32 v3, v4, v3
571; VI-NEXT:    v_trunc_f32_e32 v3, v3
572; VI-NEXT:    v_fma_f32 v2, -v3, v2, v4
573; VI-NEXT:    flat_store_dword v[0:1], v2
574; VI-NEXT:    s_endpgm
575                             float addrspace(1)* %in2) #1 {
576   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
577   %r0 = load float, float addrspace(1)* %in1, align 4
578   %r1 = load float, float addrspace(1)* %gep2, align 4
579   %r2 = frem float %r0, %r1
580   store float %r2, float addrspace(1)* %out, align 4
581   ret void
582}
583
584define amdgpu_kernel void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
585; SI-LABEL: frem_f64:
586; SI:       ; %bb.0:
587; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
588; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
589; SI-NEXT:    s_mov_b32 s7, 0xf000
590; SI-NEXT:    s_mov_b32 s6, -1
591; SI-NEXT:    s_waitcnt lgkmcnt(0)
592; SI-NEXT:    s_mov_b32 s4, s8
593; SI-NEXT:    s_mov_b32 s5, s9
594; SI-NEXT:    s_mov_b32 s0, s10
595; SI-NEXT:    s_mov_b32 s1, s11
596; SI-NEXT:    s_mov_b32 s2, s6
597; SI-NEXT:    s_mov_b32 s3, s7
598; SI-NEXT:    s_mov_b32 s14, s6
599; SI-NEXT:    s_mov_b32 s15, s7
600; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
601; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[12:15], 0
602; SI-NEXT:    s_waitcnt vmcnt(0)
603; SI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
604; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
605; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
606; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
607; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
608; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
609; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[0:1], v[2:3], v[0:1]
610; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
611; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
612; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
613; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v9
614; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
615; SI-NEXT:    s_nop 0
616; SI-NEXT:    s_nop 0
617; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
618; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
619; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
620; SI-NEXT:    v_add_i32_e32 v8, vcc, 0xfffffc01, v6
621; SI-NEXT:    s_mov_b32 s1, 0xfffff
622; SI-NEXT:    s_mov_b32 s0, s6
623; SI-NEXT:    v_lshr_b64 v[6:7], s[0:1], v8
624; SI-NEXT:    v_not_b32_e32 v6, v6
625; SI-NEXT:    v_and_b32_e32 v6, v4, v6
626; SI-NEXT:    v_not_b32_e32 v7, v7
627; SI-NEXT:    v_and_b32_e32 v7, v5, v7
628; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v5
629; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
630; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
631; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v8
632; SI-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[0:1]
633; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
634; SI-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[0:1]
635; SI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
636; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
637; SI-NEXT:    s_endpgm
638;
639; CI-LABEL: frem_f64:
640; CI:       ; %bb.0:
641; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
642; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
643; CI-NEXT:    s_mov_b32 s11, 0xf000
644; CI-NEXT:    s_mov_b32 s10, -1
645; CI-NEXT:    s_mov_b32 s2, s10
646; CI-NEXT:    s_waitcnt lgkmcnt(0)
647; CI-NEXT:    s_mov_b32 s8, s4
648; CI-NEXT:    s_mov_b32 s9, s5
649; CI-NEXT:    s_mov_b32 s4, s6
650; CI-NEXT:    s_mov_b32 s5, s7
651; CI-NEXT:    s_mov_b32 s6, s10
652; CI-NEXT:    s_mov_b32 s7, s11
653; CI-NEXT:    s_mov_b32 s3, s11
654; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
655; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
656; CI-NEXT:    s_waitcnt vmcnt(0)
657; CI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
658; CI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
659; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
660; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
661; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
662; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
663; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
664; CI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
665; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
666; CI-NEXT:    s_nop 1
667; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
668; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
669; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
670; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
671; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
672; CI-NEXT:    s_endpgm
673;
674; VI-LABEL: frem_f64:
675; VI:       ; %bb.0:
676; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
677; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
678; VI-NEXT:    s_waitcnt lgkmcnt(0)
679; VI-NEXT:    v_mov_b32_e32 v2, s6
680; VI-NEXT:    v_mov_b32_e32 v3, s7
681; VI-NEXT:    v_mov_b32_e32 v4, s0
682; VI-NEXT:    v_mov_b32_e32 v5, s1
683; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
684; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
685; VI-NEXT:    v_mov_b32_e32 v0, s4
686; VI-NEXT:    v_mov_b32_e32 v1, s5
687; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
688; VI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[2:3]
689; VI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
690; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
691; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
692; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
693; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
694; VI-NEXT:    v_div_scale_f64 v[10:11], vcc, v[2:3], v[4:5], v[2:3]
695; VI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
696; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
697; VI-NEXT:    s_nop 1
698; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
699; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[2:3]
700; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
701; VI-NEXT:    v_fma_f64 v[2:3], -v[6:7], v[4:5], v[2:3]
702; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
703; VI-NEXT:    s_endpgm
704                      double addrspace(1)* %in2) #0 {
705   %r0 = load double, double addrspace(1)* %in1, align 8
706   %r1 = load double, double addrspace(1)* %in2, align 8
707   %r2 = frem double %r0, %r1
708   store double %r2, double addrspace(1)* %out, align 8
709   ret void
710}
711
712define amdgpu_kernel void @fast_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
713; SI-LABEL: fast_frem_f64:
714; SI:       ; %bb.0:
715; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
716; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
717; SI-NEXT:    s_mov_b32 s7, 0xf000
718; SI-NEXT:    s_mov_b32 s6, -1
719; SI-NEXT:    s_waitcnt lgkmcnt(0)
720; SI-NEXT:    s_mov_b32 s4, s8
721; SI-NEXT:    s_mov_b32 s5, s9
722; SI-NEXT:    s_mov_b32 s0, s10
723; SI-NEXT:    s_mov_b32 s1, s11
724; SI-NEXT:    s_mov_b32 s2, s6
725; SI-NEXT:    s_mov_b32 s3, s7
726; SI-NEXT:    s_mov_b32 s14, s6
727; SI-NEXT:    s_mov_b32 s15, s7
728; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
729; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[12:15], 0
730; SI-NEXT:    s_waitcnt vmcnt(0)
731; SI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
732; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
733; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
734; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
735; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
736; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
737; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[0:1], v[2:3], v[0:1]
738; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
739; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
740; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
741; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v9
742; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
743; SI-NEXT:    s_nop 0
744; SI-NEXT:    s_nop 0
745; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
746; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
747; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
748; SI-NEXT:    v_add_i32_e32 v8, vcc, 0xfffffc01, v6
749; SI-NEXT:    s_mov_b32 s1, 0xfffff
750; SI-NEXT:    s_mov_b32 s0, s6
751; SI-NEXT:    v_lshr_b64 v[6:7], s[0:1], v8
752; SI-NEXT:    v_not_b32_e32 v6, v6
753; SI-NEXT:    v_and_b32_e32 v6, v4, v6
754; SI-NEXT:    v_not_b32_e32 v7, v7
755; SI-NEXT:    v_and_b32_e32 v7, v5, v7
756; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v5
757; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
758; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
759; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v8
760; SI-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[0:1]
761; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
762; SI-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[0:1]
763; SI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
764; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
765; SI-NEXT:    s_endpgm
766;
767; CI-LABEL: fast_frem_f64:
768; CI:       ; %bb.0:
769; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
770; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
771; CI-NEXT:    s_mov_b32 s11, 0xf000
772; CI-NEXT:    s_mov_b32 s10, -1
773; CI-NEXT:    s_mov_b32 s2, s10
774; CI-NEXT:    s_waitcnt lgkmcnt(0)
775; CI-NEXT:    s_mov_b32 s8, s4
776; CI-NEXT:    s_mov_b32 s9, s5
777; CI-NEXT:    s_mov_b32 s4, s6
778; CI-NEXT:    s_mov_b32 s5, s7
779; CI-NEXT:    s_mov_b32 s6, s10
780; CI-NEXT:    s_mov_b32 s7, s11
781; CI-NEXT:    s_mov_b32 s3, s11
782; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
783; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
784; CI-NEXT:    s_waitcnt vmcnt(0)
785; CI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
786; CI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
787; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
788; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
789; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
790; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
791; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
792; CI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
793; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
794; CI-NEXT:    s_nop 1
795; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
796; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
797; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
798; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
799; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
800; CI-NEXT:    s_endpgm
801;
802; VI-LABEL: fast_frem_f64:
803; VI:       ; %bb.0:
804; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
805; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
806; VI-NEXT:    s_waitcnt lgkmcnt(0)
807; VI-NEXT:    v_mov_b32_e32 v2, s6
808; VI-NEXT:    v_mov_b32_e32 v3, s7
809; VI-NEXT:    v_mov_b32_e32 v4, s0
810; VI-NEXT:    v_mov_b32_e32 v5, s1
811; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
812; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
813; VI-NEXT:    v_mov_b32_e32 v0, s4
814; VI-NEXT:    v_mov_b32_e32 v1, s5
815; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
816; VI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[2:3]
817; VI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
818; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
819; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
820; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
821; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
822; VI-NEXT:    v_div_scale_f64 v[10:11], vcc, v[2:3], v[4:5], v[2:3]
823; VI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
824; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
825; VI-NEXT:    s_nop 1
826; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
827; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[2:3]
828; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
829; VI-NEXT:    v_fma_f64 v[2:3], -v[6:7], v[4:5], v[2:3]
830; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
831; VI-NEXT:    s_endpgm
832                      double addrspace(1)* %in2) #0 {
833   %r0 = load double, double addrspace(1)* %in1, align 8
834   %r1 = load double, double addrspace(1)* %in2, align 8
835   %r2 = frem fast double %r0, %r1
836   store double %r2, double addrspace(1)* %out, align 8
837   ret void
838}
839
840define amdgpu_kernel void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
841; SI-LABEL: unsafe_frem_f64:
842; SI:       ; %bb.0:
843; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
844; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
845; SI-NEXT:    s_mov_b32 s15, 0xf000
846; SI-NEXT:    s_mov_b32 s14, -1
847; SI-NEXT:    s_waitcnt lgkmcnt(0)
848; SI-NEXT:    s_mov_b32 s12, s4
849; SI-NEXT:    s_mov_b32 s13, s5
850; SI-NEXT:    s_mov_b32 s0, s6
851; SI-NEXT:    s_mov_b32 s1, s7
852; SI-NEXT:    s_mov_b32 s2, s14
853; SI-NEXT:    s_mov_b32 s3, s15
854; SI-NEXT:    s_mov_b32 s10, s14
855; SI-NEXT:    s_mov_b32 s11, s15
856; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
857; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[8:11], 0
858; SI-NEXT:    s_waitcnt vmcnt(0)
859; SI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
860; SI-NEXT:    v_mul_f64 v[4:5], v[0:1], v[4:5]
861; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
862; SI-NEXT:    v_add_i32_e32 v8, vcc, 0xfffffc01, v6
863; SI-NEXT:    s_mov_b32 s1, 0xfffff
864; SI-NEXT:    s_mov_b32 s0, s14
865; SI-NEXT:    v_lshr_b64 v[6:7], s[0:1], v8
866; SI-NEXT:    v_not_b32_e32 v6, v6
867; SI-NEXT:    v_and_b32_e32 v6, v4, v6
868; SI-NEXT:    v_not_b32_e32 v7, v7
869; SI-NEXT:    v_and_b32_e32 v7, v5, v7
870; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v5
871; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
872; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
873; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v8
874; SI-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[0:1]
875; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
876; SI-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[0:1]
877; SI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
878; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[12:15], 0
879; SI-NEXT:    s_endpgm
880;
881; CI-LABEL: unsafe_frem_f64:
882; CI:       ; %bb.0:
883; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
884; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
885; CI-NEXT:    s_mov_b32 s11, 0xf000
886; CI-NEXT:    s_mov_b32 s10, -1
887; CI-NEXT:    s_mov_b32 s2, s10
888; CI-NEXT:    s_waitcnt lgkmcnt(0)
889; CI-NEXT:    s_mov_b32 s8, s4
890; CI-NEXT:    s_mov_b32 s9, s5
891; CI-NEXT:    s_mov_b32 s4, s6
892; CI-NEXT:    s_mov_b32 s5, s7
893; CI-NEXT:    s_mov_b32 s6, s10
894; CI-NEXT:    s_mov_b32 s7, s11
895; CI-NEXT:    s_mov_b32 s3, s11
896; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
897; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
898; CI-NEXT:    s_waitcnt vmcnt(0)
899; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
900; CI-NEXT:    v_mul_f64 v[4:5], v[0:1], v[4:5]
901; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
902; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
903; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
904; CI-NEXT:    s_endpgm
905;
906; VI-LABEL: unsafe_frem_f64:
907; VI:       ; %bb.0:
908; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
909; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
910; VI-NEXT:    s_waitcnt lgkmcnt(0)
911; VI-NEXT:    v_mov_b32_e32 v2, s6
912; VI-NEXT:    v_mov_b32_e32 v3, s7
913; VI-NEXT:    v_mov_b32_e32 v4, s0
914; VI-NEXT:    v_mov_b32_e32 v5, s1
915; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
916; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
917; VI-NEXT:    v_mov_b32_e32 v0, s4
918; VI-NEXT:    v_mov_b32_e32 v1, s5
919; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
920; VI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
921; VI-NEXT:    v_mul_f64 v[6:7], v[2:3], v[6:7]
922; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
923; VI-NEXT:    v_fma_f64 v[2:3], -v[6:7], v[4:5], v[2:3]
924; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
925; VI-NEXT:    s_endpgm
926                             double addrspace(1)* %in2) #1 {
927   %r0 = load double, double addrspace(1)* %in1, align 8
928   %r1 = load double, double addrspace(1)* %in2, align 8
929   %r2 = frem double %r0, %r1
930   store double %r2, double addrspace(1)* %out, align 8
931   ret void
932}
933
934define amdgpu_kernel void @frem_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in1,
935; SI-LABEL: frem_v2f16:
936; SI:       ; %bb.0:
937; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
938; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
939; SI-NEXT:    s_mov_b32 s3, 0xf000
940; SI-NEXT:    s_mov_b32 s2, -1
941; SI-NEXT:    s_waitcnt lgkmcnt(0)
942; SI-NEXT:    s_mov_b32 s0, s4
943; SI-NEXT:    s_mov_b32 s1, s5
944; SI-NEXT:    s_mov_b32 s4, s6
945; SI-NEXT:    s_mov_b32 s5, s7
946; SI-NEXT:    s_mov_b32 s6, s2
947; SI-NEXT:    s_mov_b32 s7, s3
948; SI-NEXT:    s_mov_b32 s10, s2
949; SI-NEXT:    s_mov_b32 s11, s3
950; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
951; SI-NEXT:    s_waitcnt vmcnt(0)
952; SI-NEXT:    v_cvt_f32_f16_e32 v1, v0
953; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
954; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
955; SI-NEXT:    buffer_load_dword v2, off, s[8:11], 0 offset:16
956; SI-NEXT:    s_waitcnt vmcnt(0)
957; SI-NEXT:    v_cvt_f32_f16_e32 v3, v2
958; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
959; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
960; SI-NEXT:    v_div_scale_f32 v4, vcc, v0, v2, v0
961; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v2, v2, v0
962; SI-NEXT:    v_rcp_f32_e32 v6, v5
963; SI-NEXT:    s_mov_b32 s6, 3
964; SI-NEXT:    s_mov_b32 s7, 0
965; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
966; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
967; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
968; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
969; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
970; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
971; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
972; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
973; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
974; SI-NEXT:    v_div_fixup_f32 v4, v4, v2, v0
975; SI-NEXT:    v_trunc_f32_e32 v4, v4
976; SI-NEXT:    v_fma_f32 v0, -v4, v2, v0
977; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
978; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
979; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
980; SI-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
981; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v1
982; SI-NEXT:    v_rcp_f32_e32 v5, v4
983; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
984; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
985; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
986; SI-NEXT:    v_mul_f32_e32 v6, v2, v5
987; SI-NEXT:    v_fma_f32 v7, -v4, v6, v2
988; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
989; SI-NEXT:    v_fma_f32 v2, -v4, v6, v2
990; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
991; SI-NEXT:    v_div_fmas_f32 v2, v2, v5, v6
992; SI-NEXT:    v_div_fixup_f32 v2, v2, v3, v1
993; SI-NEXT:    v_trunc_f32_e32 v2, v2
994; SI-NEXT:    v_fma_f32 v1, -v2, v3, v1
995; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
996; SI-NEXT:    v_or_b32_e32 v0, v1, v0
997; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
998; SI-NEXT:    s_endpgm
999;
1000; CI-LABEL: frem_v2f16:
1001; CI:       ; %bb.0:
1002; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1003; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1004; CI-NEXT:    s_mov_b32 s3, 0xf000
1005; CI-NEXT:    s_mov_b32 s2, -1
1006; CI-NEXT:    s_mov_b32 s10, s2
1007; CI-NEXT:    s_waitcnt lgkmcnt(0)
1008; CI-NEXT:    s_mov_b32 s0, s4
1009; CI-NEXT:    s_mov_b32 s1, s5
1010; CI-NEXT:    s_mov_b32 s4, s6
1011; CI-NEXT:    s_mov_b32 s5, s7
1012; CI-NEXT:    s_mov_b32 s11, s3
1013; CI-NEXT:    s_mov_b32 s6, s2
1014; CI-NEXT:    s_mov_b32 s7, s3
1015; CI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
1016; CI-NEXT:    buffer_load_dword v2, off, s[8:11], 0 offset:16
1017; CI-NEXT:    s_mov_b32 s6, 3
1018; CI-NEXT:    s_mov_b32 s7, 0
1019; CI-NEXT:    s_waitcnt vmcnt(1)
1020; CI-NEXT:    v_cvt_f32_f16_e32 v1, v0
1021; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1022; CI-NEXT:    s_waitcnt vmcnt(0)
1023; CI-NEXT:    v_cvt_f32_f16_e32 v3, v2
1024; CI-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
1025; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
1026; CI-NEXT:    v_cvt_f32_f16_e32 v2, v2
1027; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v2, v2, v0
1028; CI-NEXT:    v_div_scale_f32 v4, vcc, v0, v2, v0
1029; CI-NEXT:    v_rcp_f32_e32 v6, v5
1030; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1031; CI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
1032; CI-NEXT:    v_fma_f32 v6, v7, v6, v6
1033; CI-NEXT:    v_mul_f32_e32 v7, v4, v6
1034; CI-NEXT:    v_fma_f32 v8, -v5, v7, v4
1035; CI-NEXT:    v_fma_f32 v7, v8, v6, v7
1036; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1037; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1038; CI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
1039; CI-NEXT:    v_div_fixup_f32 v4, v4, v2, v0
1040; CI-NEXT:    v_trunc_f32_e32 v4, v4
1041; CI-NEXT:    v_fma_f32 v0, -v4, v2, v0
1042; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v1
1043; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
1044; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
1045; CI-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
1046; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1047; CI-NEXT:    v_rcp_f32_e32 v5, v4
1048; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1049; CI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
1050; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
1051; CI-NEXT:    v_mul_f32_e32 v6, v2, v5
1052; CI-NEXT:    v_fma_f32 v7, -v4, v6, v2
1053; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
1054; CI-NEXT:    v_fma_f32 v2, -v4, v6, v2
1055; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1056; CI-NEXT:    v_div_fmas_f32 v2, v2, v5, v6
1057; CI-NEXT:    v_div_fixup_f32 v2, v2, v3, v1
1058; CI-NEXT:    v_trunc_f32_e32 v2, v2
1059; CI-NEXT:    v_fma_f32 v1, -v2, v3, v1
1060; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
1061; CI-NEXT:    v_or_b32_e32 v0, v1, v0
1062; CI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1063; CI-NEXT:    s_endpgm
1064;
1065; VI-LABEL: frem_v2f16:
1066; VI:       ; %bb.0:
1067; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1068; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1069; VI-NEXT:    s_waitcnt lgkmcnt(0)
1070; VI-NEXT:    v_mov_b32_e32 v2, s6
1071; VI-NEXT:    s_add_u32 s0, s0, 16
1072; VI-NEXT:    v_mov_b32_e32 v3, s7
1073; VI-NEXT:    s_addc_u32 s1, s1, 0
1074; VI-NEXT:    flat_load_dword v4, v[2:3]
1075; VI-NEXT:    v_mov_b32_e32 v3, s1
1076; VI-NEXT:    v_mov_b32_e32 v2, s0
1077; VI-NEXT:    flat_load_dword v2, v[2:3]
1078; VI-NEXT:    v_mov_b32_e32 v0, s4
1079; VI-NEXT:    v_mov_b32_e32 v1, s5
1080; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
1081; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v4
1082; VI-NEXT:    v_cvt_f32_f16_e32 v5, v3
1083; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1084; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
1085; VI-NEXT:    v_cvt_f32_f16_e32 v7, v6
1086; VI-NEXT:    v_rcp_f32_e32 v7, v7
1087; VI-NEXT:    v_mul_f32_e32 v5, v5, v7
1088; VI-NEXT:    v_cvt_f16_f32_e32 v5, v5
1089; VI-NEXT:    v_div_fixup_f16 v5, v5, v6, v3
1090; VI-NEXT:    v_trunc_f16_e32 v5, v5
1091; VI-NEXT:    v_fma_f16 v3, -v5, v6, v3
1092; VI-NEXT:    v_cvt_f32_f16_e32 v6, v2
1093; VI-NEXT:    v_cvt_f32_f16_e32 v5, v4
1094; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
1095; VI-NEXT:    v_rcp_f32_e32 v6, v6
1096; VI-NEXT:    v_mul_f32_e32 v5, v5, v6
1097; VI-NEXT:    v_cvt_f16_f32_e32 v5, v5
1098; VI-NEXT:    v_div_fixup_f16 v5, v5, v2, v4
1099; VI-NEXT:    v_trunc_f16_e32 v5, v5
1100; VI-NEXT:    v_fma_f16 v2, -v5, v2, v4
1101; VI-NEXT:    v_or_b32_e32 v2, v2, v3
1102; VI-NEXT:    flat_store_dword v[0:1], v2
1103; VI-NEXT:    s_endpgm
1104                        <2 x half> addrspace(1)* %in2) #0 {
1105   %gep2 = getelementptr <2 x half>, <2 x half> addrspace(1)* %in2, i32 4
1106   %r0 = load <2 x half>, <2 x half> addrspace(1)* %in1, align 8
1107   %r1 = load <2 x half>, <2 x half> addrspace(1)* %gep2, align 8
1108   %r2 = frem <2 x half> %r0, %r1
1109   store <2 x half> %r2, <2 x half> addrspace(1)* %out, align 8
1110   ret void
1111}
1112
1113define amdgpu_kernel void @frem_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in1,
1114; SI-LABEL: frem_v4f16:
1115; SI:       ; %bb.0:
1116; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1117; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1118; SI-NEXT:    s_mov_b32 s3, 0xf000
1119; SI-NEXT:    s_mov_b32 s2, -1
1120; SI-NEXT:    s_waitcnt lgkmcnt(0)
1121; SI-NEXT:    s_mov_b32 s0, s4
1122; SI-NEXT:    s_mov_b32 s1, s5
1123; SI-NEXT:    s_mov_b32 s4, s6
1124; SI-NEXT:    s_mov_b32 s5, s7
1125; SI-NEXT:    s_mov_b32 s6, s2
1126; SI-NEXT:    s_mov_b32 s7, s3
1127; SI-NEXT:    s_mov_b32 s10, s2
1128; SI-NEXT:    s_mov_b32 s11, s3
1129; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
1130; SI-NEXT:    s_waitcnt vmcnt(0)
1131; SI-NEXT:    v_cvt_f32_f16_e32 v2, v0
1132; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1133; SI-NEXT:    v_cvt_f32_f16_e32 v3, v0
1134; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
1135; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
1136; SI-NEXT:    v_cvt_f32_f16_e32 v5, v0
1137; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0 offset:32
1138; SI-NEXT:    s_waitcnt vmcnt(0)
1139; SI-NEXT:    v_cvt_f32_f16_e32 v6, v0
1140; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1141; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
1142; SI-NEXT:    v_cvt_f32_f16_e32 v7, v1
1143; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
1144; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
1145; SI-NEXT:    v_div_scale_f32 v8, vcc, v5, v1, v5
1146; SI-NEXT:    v_div_scale_f32 v9, s[4:5], v1, v1, v5
1147; SI-NEXT:    v_rcp_f32_e32 v10, v9
1148; SI-NEXT:    s_mov_b32 s6, 3
1149; SI-NEXT:    s_mov_b32 s7, 0
1150; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1151; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
1152; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
1153; SI-NEXT:    v_mul_f32_e32 v11, v8, v10
1154; SI-NEXT:    v_fma_f32 v12, -v9, v11, v8
1155; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
1156; SI-NEXT:    v_fma_f32 v8, -v9, v11, v8
1157; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1158; SI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
1159; SI-NEXT:    v_div_fixup_f32 v8, v8, v1, v5
1160; SI-NEXT:    v_trunc_f32_e32 v8, v8
1161; SI-NEXT:    v_fma_f32 v1, -v8, v1, v5
1162; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
1163; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
1164; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1165; SI-NEXT:    v_div_scale_f32 v5, vcc, v4, v7, v4
1166; SI-NEXT:    v_div_scale_f32 v8, s[4:5], v7, v7, v4
1167; SI-NEXT:    v_rcp_f32_e32 v9, v8
1168; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1169; SI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
1170; SI-NEXT:    v_fma_f32 v9, v10, v9, v9
1171; SI-NEXT:    v_mul_f32_e32 v10, v5, v9
1172; SI-NEXT:    v_fma_f32 v11, -v8, v10, v5
1173; SI-NEXT:    v_fma_f32 v10, v11, v9, v10
1174; SI-NEXT:    v_fma_f32 v5, -v8, v10, v5
1175; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1176; SI-NEXT:    v_div_fmas_f32 v5, v5, v9, v10
1177; SI-NEXT:    v_div_fixup_f32 v5, v5, v7, v4
1178; SI-NEXT:    v_trunc_f32_e32 v5, v5
1179; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1180; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
1181; SI-NEXT:    v_or_b32_e32 v1, v4, v1
1182; SI-NEXT:    v_div_scale_f32 v4, vcc, v3, v0, v3
1183; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v0, v0, v3
1184; SI-NEXT:    v_rcp_f32_e32 v7, v5
1185; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1186; SI-NEXT:    v_fma_f32 v8, -v5, v7, 1.0
1187; SI-NEXT:    v_fma_f32 v7, v8, v7, v7
1188; SI-NEXT:    v_mul_f32_e32 v8, v4, v7
1189; SI-NEXT:    v_fma_f32 v9, -v5, v8, v4
1190; SI-NEXT:    v_fma_f32 v8, v9, v7, v8
1191; SI-NEXT:    v_fma_f32 v4, -v5, v8, v4
1192; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1193; SI-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
1194; SI-NEXT:    v_div_fixup_f32 v4, v4, v0, v3
1195; SI-NEXT:    v_trunc_f32_e32 v4, v4
1196; SI-NEXT:    v_fma_f32 v0, -v4, v0, v3
1197; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
1198; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1199; SI-NEXT:    v_div_scale_f32 v3, vcc, v2, v6, v2
1200; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v6, v6, v2
1201; SI-NEXT:    v_rcp_f32_e32 v5, v4
1202; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1203; SI-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1204; SI-NEXT:    v_fma_f32 v5, v7, v5, v5
1205; SI-NEXT:    v_mul_f32_e32 v7, v3, v5
1206; SI-NEXT:    v_fma_f32 v8, -v4, v7, v3
1207; SI-NEXT:    v_fma_f32 v7, v8, v5, v7
1208; SI-NEXT:    v_fma_f32 v3, -v4, v7, v3
1209; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1210; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v7
1211; SI-NEXT:    v_div_fixup_f32 v3, v3, v6, v2
1212; SI-NEXT:    v_trunc_f32_e32 v3, v3
1213; SI-NEXT:    v_fma_f32 v2, -v3, v6, v2
1214; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
1215; SI-NEXT:    v_or_b32_e32 v0, v2, v0
1216; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1217; SI-NEXT:    s_endpgm
1218;
1219; CI-LABEL: frem_v4f16:
1220; CI:       ; %bb.0:
1221; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1222; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1223; CI-NEXT:    s_mov_b32 s3, 0xf000
1224; CI-NEXT:    s_mov_b32 s2, -1
1225; CI-NEXT:    s_mov_b32 s10, s2
1226; CI-NEXT:    s_waitcnt lgkmcnt(0)
1227; CI-NEXT:    s_mov_b32 s0, s4
1228; CI-NEXT:    s_mov_b32 s1, s5
1229; CI-NEXT:    s_mov_b32 s4, s6
1230; CI-NEXT:    s_mov_b32 s5, s7
1231; CI-NEXT:    s_mov_b32 s6, s2
1232; CI-NEXT:    s_mov_b32 s7, s3
1233; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
1234; CI-NEXT:    s_mov_b32 s11, s3
1235; CI-NEXT:    s_mov_b32 s6, 3
1236; CI-NEXT:    s_mov_b32 s7, 0
1237; CI-NEXT:    s_waitcnt vmcnt(0)
1238; CI-NEXT:    v_cvt_f32_f16_e32 v2, v0
1239; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1240; CI-NEXT:    v_cvt_f32_f16_e32 v3, v0
1241; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
1242; CI-NEXT:    v_cvt_f32_f16_e32 v4, v1
1243; CI-NEXT:    v_cvt_f32_f16_e32 v5, v0
1244; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0 offset:32
1245; CI-NEXT:    s_waitcnt vmcnt(0)
1246; CI-NEXT:    v_cvt_f32_f16_e32 v7, v1
1247; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
1248; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
1249; CI-NEXT:    v_cvt_f32_f16_e32 v6, v0
1250; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1251; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
1252; CI-NEXT:    v_div_scale_f32 v9, s[4:5], v1, v1, v5
1253; CI-NEXT:    v_div_scale_f32 v8, vcc, v5, v1, v5
1254; CI-NEXT:    v_rcp_f32_e32 v10, v9
1255; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1256; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
1257; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
1258; CI-NEXT:    v_mul_f32_e32 v11, v8, v10
1259; CI-NEXT:    v_fma_f32 v12, -v9, v11, v8
1260; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
1261; CI-NEXT:    v_fma_f32 v8, -v9, v11, v8
1262; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1263; CI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
1264; CI-NEXT:    v_div_fixup_f32 v8, v8, v1, v5
1265; CI-NEXT:    v_trunc_f32_e32 v8, v8
1266; CI-NEXT:    v_fma_f32 v1, -v8, v1, v5
1267; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v7, v7, v4
1268; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
1269; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
1270; CI-NEXT:    v_div_scale_f32 v5, vcc, v4, v7, v4
1271; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1272; CI-NEXT:    v_rcp_f32_e32 v9, v8
1273; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1274; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
1275; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
1276; CI-NEXT:    v_mul_f32_e32 v10, v5, v9
1277; CI-NEXT:    v_fma_f32 v11, -v8, v10, v5
1278; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
1279; CI-NEXT:    v_fma_f32 v5, -v8, v10, v5
1280; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1281; CI-NEXT:    v_div_fmas_f32 v5, v5, v9, v10
1282; CI-NEXT:    v_div_fixup_f32 v5, v5, v7, v4
1283; CI-NEXT:    v_trunc_f32_e32 v5, v5
1284; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1285; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v0, v0, v3
1286; CI-NEXT:    v_cvt_f16_f32_e32 v4, v4
1287; CI-NEXT:    v_or_b32_e32 v1, v4, v1
1288; CI-NEXT:    v_div_scale_f32 v4, vcc, v3, v0, v3
1289; CI-NEXT:    v_rcp_f32_e32 v7, v5
1290; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1291; CI-NEXT:    v_fma_f32 v8, -v5, v7, 1.0
1292; CI-NEXT:    v_fma_f32 v7, v8, v7, v7
1293; CI-NEXT:    v_mul_f32_e32 v8, v4, v7
1294; CI-NEXT:    v_fma_f32 v9, -v5, v8, v4
1295; CI-NEXT:    v_fma_f32 v8, v9, v7, v8
1296; CI-NEXT:    v_fma_f32 v4, -v5, v8, v4
1297; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1298; CI-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
1299; CI-NEXT:    v_div_fixup_f32 v4, v4, v0, v3
1300; CI-NEXT:    v_trunc_f32_e32 v4, v4
1301; CI-NEXT:    v_fma_f32 v0, -v4, v0, v3
1302; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v6, v6, v2
1303; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
1304; CI-NEXT:    v_div_scale_f32 v3, vcc, v2, v6, v2
1305; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1306; CI-NEXT:    v_rcp_f32_e32 v5, v4
1307; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1308; CI-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1309; CI-NEXT:    v_fma_f32 v5, v7, v5, v5
1310; CI-NEXT:    v_mul_f32_e32 v7, v3, v5
1311; CI-NEXT:    v_fma_f32 v8, -v4, v7, v3
1312; CI-NEXT:    v_fma_f32 v7, v8, v5, v7
1313; CI-NEXT:    v_fma_f32 v3, -v4, v7, v3
1314; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1315; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v7
1316; CI-NEXT:    v_div_fixup_f32 v3, v3, v6, v2
1317; CI-NEXT:    v_trunc_f32_e32 v3, v3
1318; CI-NEXT:    v_fma_f32 v2, -v3, v6, v2
1319; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
1320; CI-NEXT:    v_or_b32_e32 v0, v2, v0
1321; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1322; CI-NEXT:    s_endpgm
1323;
1324; VI-LABEL: frem_v4f16:
1325; VI:       ; %bb.0:
1326; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1327; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1328; VI-NEXT:    s_waitcnt lgkmcnt(0)
1329; VI-NEXT:    v_mov_b32_e32 v2, s6
1330; VI-NEXT:    s_add_u32 s0, s0, 32
1331; VI-NEXT:    s_addc_u32 s1, s1, 0
1332; VI-NEXT:    v_mov_b32_e32 v5, s1
1333; VI-NEXT:    v_mov_b32_e32 v4, s0
1334; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
1335; VI-NEXT:    v_mov_b32_e32 v3, s7
1336; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
1337; VI-NEXT:    v_mov_b32_e32 v0, s4
1338; VI-NEXT:    v_mov_b32_e32 v1, s5
1339; VI-NEXT:    s_waitcnt vmcnt(1) lgkmcnt(1)
1340; VI-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
1341; VI-NEXT:    v_cvt_f32_f16_e32 v9, v8
1342; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1343; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
1344; VI-NEXT:    v_cvt_f32_f16_e32 v7, v6
1345; VI-NEXT:    v_rcp_f32_e32 v9, v9
1346; VI-NEXT:    v_mul_f32_e32 v7, v7, v9
1347; VI-NEXT:    v_cvt_f16_f32_e32 v7, v7
1348; VI-NEXT:    v_div_fixup_f16 v7, v7, v8, v6
1349; VI-NEXT:    v_trunc_f16_e32 v7, v7
1350; VI-NEXT:    v_fma_f16 v6, -v7, v8, v6
1351; VI-NEXT:    v_cvt_f32_f16_e32 v8, v5
1352; VI-NEXT:    v_cvt_f32_f16_e32 v7, v3
1353; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
1354; VI-NEXT:    v_rcp_f32_e32 v8, v8
1355; VI-NEXT:    v_mul_f32_e32 v7, v7, v8
1356; VI-NEXT:    v_cvt_f16_f32_e32 v7, v7
1357; VI-NEXT:    v_div_fixup_f16 v7, v7, v5, v3
1358; VI-NEXT:    v_trunc_f16_e32 v7, v7
1359; VI-NEXT:    v_fma_f16 v3, -v7, v5, v3
1360; VI-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
1361; VI-NEXT:    v_cvt_f32_f16_e32 v8, v7
1362; VI-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
1363; VI-NEXT:    v_or_b32_e32 v3, v3, v6
1364; VI-NEXT:    v_cvt_f32_f16_e32 v6, v5
1365; VI-NEXT:    v_rcp_f32_e32 v8, v8
1366; VI-NEXT:    v_mul_f32_e32 v6, v6, v8
1367; VI-NEXT:    v_cvt_f16_f32_e32 v6, v6
1368; VI-NEXT:    v_div_fixup_f16 v6, v6, v7, v5
1369; VI-NEXT:    v_trunc_f16_e32 v6, v6
1370; VI-NEXT:    v_fma_f16 v5, -v6, v7, v5
1371; VI-NEXT:    v_cvt_f32_f16_e32 v7, v4
1372; VI-NEXT:    v_cvt_f32_f16_e32 v6, v2
1373; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
1374; VI-NEXT:    v_rcp_f32_e32 v7, v7
1375; VI-NEXT:    v_mul_f32_e32 v6, v6, v7
1376; VI-NEXT:    v_cvt_f16_f32_e32 v6, v6
1377; VI-NEXT:    v_div_fixup_f16 v6, v6, v4, v2
1378; VI-NEXT:    v_trunc_f16_e32 v6, v6
1379; VI-NEXT:    v_fma_f16 v2, -v6, v4, v2
1380; VI-NEXT:    v_or_b32_e32 v2, v2, v5
1381; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
1382; VI-NEXT:    s_endpgm
1383                        <4 x half> addrspace(1)* %in2) #0 {
1384   %gep2 = getelementptr <4 x half>, <4 x half> addrspace(1)* %in2, i32 4
1385   %r0 = load <4 x half>, <4 x half> addrspace(1)* %in1, align 16
1386   %r1 = load <4 x half>, <4 x half> addrspace(1)* %gep2, align 16
1387   %r2 = frem <4 x half> %r0, %r1
1388   store <4 x half> %r2, <4 x half> addrspace(1)* %out, align 16
1389   ret void
1390}
1391
1392define amdgpu_kernel void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
1393; SI-LABEL: frem_v2f32:
1394; SI:       ; %bb.0:
1395; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1396; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1397; SI-NEXT:    s_mov_b32 s3, 0xf000
1398; SI-NEXT:    s_mov_b32 s2, -1
1399; SI-NEXT:    s_waitcnt lgkmcnt(0)
1400; SI-NEXT:    s_mov_b32 s0, s4
1401; SI-NEXT:    s_mov_b32 s1, s5
1402; SI-NEXT:    s_mov_b32 s4, s6
1403; SI-NEXT:    s_mov_b32 s5, s7
1404; SI-NEXT:    s_mov_b32 s6, s2
1405; SI-NEXT:    s_mov_b32 s7, s3
1406; SI-NEXT:    s_mov_b32 s10, s2
1407; SI-NEXT:    s_mov_b32 s11, s3
1408; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
1409; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[8:11], 0 offset:32
1410; SI-NEXT:    s_waitcnt vmcnt(0)
1411; SI-NEXT:    v_div_scale_f32 v4, vcc, v1, v3, v1
1412; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1413; SI-NEXT:    v_rcp_f32_e32 v6, v5
1414; SI-NEXT:    s_mov_b32 s6, 3
1415; SI-NEXT:    s_mov_b32 s7, 0
1416; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1417; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
1418; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
1419; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
1420; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
1421; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
1422; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1423; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1424; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
1425; SI-NEXT:    v_div_fixup_f32 v4, v4, v3, v1
1426; SI-NEXT:    v_trunc_f32_e32 v4, v4
1427; SI-NEXT:    v_fma_f32 v1, -v4, v3, v1
1428; SI-NEXT:    v_div_scale_f32 v3, vcc, v0, v2, v0
1429; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1430; SI-NEXT:    v_rcp_f32_e32 v5, v4
1431; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1432; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
1433; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
1434; SI-NEXT:    v_mul_f32_e32 v6, v3, v5
1435; SI-NEXT:    v_fma_f32 v7, -v4, v6, v3
1436; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
1437; SI-NEXT:    v_fma_f32 v3, -v4, v6, v3
1438; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1439; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
1440; SI-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
1441; SI-NEXT:    v_trunc_f32_e32 v3, v3
1442; SI-NEXT:    v_fma_f32 v0, -v3, v2, v0
1443; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1444; SI-NEXT:    s_endpgm
1445;
1446; CI-LABEL: frem_v2f32:
1447; CI:       ; %bb.0:
1448; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1449; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1450; CI-NEXT:    s_mov_b32 s3, 0xf000
1451; CI-NEXT:    s_mov_b32 s2, -1
1452; CI-NEXT:    s_mov_b32 s10, s2
1453; CI-NEXT:    s_waitcnt lgkmcnt(0)
1454; CI-NEXT:    s_mov_b32 s0, s4
1455; CI-NEXT:    s_mov_b32 s1, s5
1456; CI-NEXT:    s_mov_b32 s4, s6
1457; CI-NEXT:    s_mov_b32 s5, s7
1458; CI-NEXT:    s_mov_b32 s6, s2
1459; CI-NEXT:    s_mov_b32 s7, s3
1460; CI-NEXT:    s_mov_b32 s11, s3
1461; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
1462; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[8:11], 0 offset:32
1463; CI-NEXT:    s_mov_b32 s6, 3
1464; CI-NEXT:    s_mov_b32 s7, 0
1465; CI-NEXT:    s_waitcnt vmcnt(0)
1466; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1467; CI-NEXT:    v_div_scale_f32 v4, vcc, v1, v3, v1
1468; CI-NEXT:    v_rcp_f32_e32 v6, v5
1469; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1470; CI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
1471; CI-NEXT:    v_fma_f32 v6, v7, v6, v6
1472; CI-NEXT:    v_mul_f32_e32 v7, v4, v6
1473; CI-NEXT:    v_fma_f32 v8, -v5, v7, v4
1474; CI-NEXT:    v_fma_f32 v7, v8, v6, v7
1475; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1476; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1477; CI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
1478; CI-NEXT:    v_div_fixup_f32 v4, v4, v3, v1
1479; CI-NEXT:    v_trunc_f32_e32 v4, v4
1480; CI-NEXT:    v_fma_f32 v1, -v4, v3, v1
1481; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1482; CI-NEXT:    v_div_scale_f32 v3, vcc, v0, v2, v0
1483; CI-NEXT:    v_rcp_f32_e32 v5, v4
1484; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1485; CI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
1486; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
1487; CI-NEXT:    v_mul_f32_e32 v6, v3, v5
1488; CI-NEXT:    v_fma_f32 v7, -v4, v6, v3
1489; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
1490; CI-NEXT:    v_fma_f32 v3, -v4, v6, v3
1491; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1492; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
1493; CI-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
1494; CI-NEXT:    v_trunc_f32_e32 v3, v3
1495; CI-NEXT:    v_fma_f32 v0, -v3, v2, v0
1496; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1497; CI-NEXT:    s_endpgm
1498;
1499; VI-LABEL: frem_v2f32:
1500; VI:       ; %bb.0:
1501; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1502; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1503; VI-NEXT:    s_mov_b32 s2, 3
1504; VI-NEXT:    s_mov_b32 s3, 0
1505; VI-NEXT:    s_waitcnt lgkmcnt(0)
1506; VI-NEXT:    v_mov_b32_e32 v2, s6
1507; VI-NEXT:    s_add_u32 s0, s0, 32
1508; VI-NEXT:    s_addc_u32 s1, s1, 0
1509; VI-NEXT:    v_mov_b32_e32 v5, s1
1510; VI-NEXT:    v_mov_b32_e32 v3, s7
1511; VI-NEXT:    v_mov_b32_e32 v4, s0
1512; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
1513; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
1514; VI-NEXT:    v_mov_b32_e32 v0, s4
1515; VI-NEXT:    v_mov_b32_e32 v1, s5
1516; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1517; VI-NEXT:    v_div_scale_f32 v7, s[0:1], v5, v5, v3
1518; VI-NEXT:    v_div_scale_f32 v6, vcc, v3, v5, v3
1519; VI-NEXT:    v_rcp_f32_e32 v8, v7
1520; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1521; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
1522; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
1523; VI-NEXT:    v_mul_f32_e32 v9, v6, v8
1524; VI-NEXT:    v_fma_f32 v10, -v7, v9, v6
1525; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
1526; VI-NEXT:    v_fma_f32 v6, -v7, v9, v6
1527; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1528; VI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
1529; VI-NEXT:    v_div_fixup_f32 v6, v6, v5, v3
1530; VI-NEXT:    v_trunc_f32_e32 v6, v6
1531; VI-NEXT:    v_fma_f32 v3, -v6, v5, v3
1532; VI-NEXT:    v_div_scale_f32 v6, s[0:1], v4, v4, v2
1533; VI-NEXT:    v_div_scale_f32 v5, vcc, v2, v4, v2
1534; VI-NEXT:    v_rcp_f32_e32 v7, v6
1535; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1536; VI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
1537; VI-NEXT:    v_fma_f32 v7, v8, v7, v7
1538; VI-NEXT:    v_mul_f32_e32 v8, v5, v7
1539; VI-NEXT:    v_fma_f32 v9, -v6, v8, v5
1540; VI-NEXT:    v_fma_f32 v8, v9, v7, v8
1541; VI-NEXT:    v_fma_f32 v5, -v6, v8, v5
1542; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1543; VI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
1544; VI-NEXT:    v_div_fixup_f32 v5, v5, v4, v2
1545; VI-NEXT:    v_trunc_f32_e32 v5, v5
1546; VI-NEXT:    v_fma_f32 v2, -v5, v4, v2
1547; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
1548; VI-NEXT:    s_endpgm
1549                        <2 x float> addrspace(1)* %in2) #0 {
1550   %gep2 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in2, i32 4
1551   %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1, align 8
1552   %r1 = load <2 x float>, <2 x float> addrspace(1)* %gep2, align 8
1553   %r2 = frem <2 x float> %r0, %r1
1554   store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8
1555   ret void
1556}
1557
1558define amdgpu_kernel void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
1559; SI-LABEL: frem_v4f32:
1560; SI:       ; %bb.0:
1561; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1562; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1563; SI-NEXT:    s_mov_b32 s3, 0xf000
1564; SI-NEXT:    s_mov_b32 s2, -1
1565; SI-NEXT:    s_waitcnt lgkmcnt(0)
1566; SI-NEXT:    s_mov_b32 s0, s4
1567; SI-NEXT:    s_mov_b32 s1, s5
1568; SI-NEXT:    s_mov_b32 s4, s6
1569; SI-NEXT:    s_mov_b32 s5, s7
1570; SI-NEXT:    s_mov_b32 s6, s2
1571; SI-NEXT:    s_mov_b32 s7, s3
1572; SI-NEXT:    s_mov_b32 s10, s2
1573; SI-NEXT:    s_mov_b32 s11, s3
1574; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
1575; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:64
1576; SI-NEXT:    s_waitcnt vmcnt(0)
1577; SI-NEXT:    v_div_scale_f32 v8, vcc, v3, v7, v3
1578; SI-NEXT:    v_div_scale_f32 v9, s[4:5], v7, v7, v3
1579; SI-NEXT:    v_rcp_f32_e32 v10, v9
1580; SI-NEXT:    s_mov_b32 s6, 3
1581; SI-NEXT:    s_mov_b32 s7, 0
1582; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1583; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
1584; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
1585; SI-NEXT:    v_mul_f32_e32 v11, v8, v10
1586; SI-NEXT:    v_fma_f32 v12, -v9, v11, v8
1587; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
1588; SI-NEXT:    v_fma_f32 v8, -v9, v11, v8
1589; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1590; SI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
1591; SI-NEXT:    v_div_fixup_f32 v8, v8, v7, v3
1592; SI-NEXT:    v_trunc_f32_e32 v8, v8
1593; SI-NEXT:    v_fma_f32 v3, -v8, v7, v3
1594; SI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
1595; SI-NEXT:    v_div_scale_f32 v8, s[4:5], v6, v6, v2
1596; SI-NEXT:    v_rcp_f32_e32 v9, v8
1597; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1598; SI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
1599; SI-NEXT:    v_fma_f32 v9, v10, v9, v9
1600; SI-NEXT:    v_mul_f32_e32 v10, v7, v9
1601; SI-NEXT:    v_fma_f32 v11, -v8, v10, v7
1602; SI-NEXT:    v_fma_f32 v10, v11, v9, v10
1603; SI-NEXT:    v_fma_f32 v7, -v8, v10, v7
1604; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1605; SI-NEXT:    v_div_fmas_f32 v7, v7, v9, v10
1606; SI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
1607; SI-NEXT:    v_trunc_f32_e32 v7, v7
1608; SI-NEXT:    v_fma_f32 v2, -v7, v6, v2
1609; SI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
1610; SI-NEXT:    v_div_scale_f32 v7, s[4:5], v5, v5, v1
1611; SI-NEXT:    v_rcp_f32_e32 v8, v7
1612; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1613; SI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
1614; SI-NEXT:    v_fma_f32 v8, v9, v8, v8
1615; SI-NEXT:    v_mul_f32_e32 v9, v6, v8
1616; SI-NEXT:    v_fma_f32 v10, -v7, v9, v6
1617; SI-NEXT:    v_fma_f32 v9, v10, v8, v9
1618; SI-NEXT:    v_fma_f32 v6, -v7, v9, v6
1619; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1620; SI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
1621; SI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
1622; SI-NEXT:    v_trunc_f32_e32 v6, v6
1623; SI-NEXT:    v_fma_f32 v1, -v6, v5, v1
1624; SI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
1625; SI-NEXT:    v_div_scale_f32 v6, s[4:5], v4, v4, v0
1626; SI-NEXT:    v_rcp_f32_e32 v7, v6
1627; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1628; SI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
1629; SI-NEXT:    v_fma_f32 v7, v8, v7, v7
1630; SI-NEXT:    v_mul_f32_e32 v8, v5, v7
1631; SI-NEXT:    v_fma_f32 v9, -v6, v8, v5
1632; SI-NEXT:    v_fma_f32 v8, v9, v7, v8
1633; SI-NEXT:    v_fma_f32 v5, -v6, v8, v5
1634; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1635; SI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
1636; SI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
1637; SI-NEXT:    v_trunc_f32_e32 v5, v5
1638; SI-NEXT:    v_fma_f32 v0, -v5, v4, v0
1639; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1640; SI-NEXT:    s_endpgm
1641;
1642; CI-LABEL: frem_v4f32:
1643; CI:       ; %bb.0:
1644; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1645; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1646; CI-NEXT:    s_mov_b32 s3, 0xf000
1647; CI-NEXT:    s_mov_b32 s2, -1
1648; CI-NEXT:    s_mov_b32 s10, s2
1649; CI-NEXT:    s_waitcnt lgkmcnt(0)
1650; CI-NEXT:    s_mov_b32 s0, s4
1651; CI-NEXT:    s_mov_b32 s1, s5
1652; CI-NEXT:    s_mov_b32 s4, s6
1653; CI-NEXT:    s_mov_b32 s5, s7
1654; CI-NEXT:    s_mov_b32 s6, s2
1655; CI-NEXT:    s_mov_b32 s7, s3
1656; CI-NEXT:    s_mov_b32 s11, s3
1657; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
1658; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:64
1659; CI-NEXT:    s_mov_b32 s6, 3
1660; CI-NEXT:    s_mov_b32 s7, 0
1661; CI-NEXT:    s_waitcnt vmcnt(0)
1662; CI-NEXT:    v_div_scale_f32 v9, s[4:5], v7, v7, v3
1663; CI-NEXT:    v_div_scale_f32 v8, vcc, v3, v7, v3
1664; CI-NEXT:    v_rcp_f32_e32 v10, v9
1665; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1666; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
1667; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
1668; CI-NEXT:    v_mul_f32_e32 v11, v8, v10
1669; CI-NEXT:    v_fma_f32 v12, -v9, v11, v8
1670; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
1671; CI-NEXT:    v_fma_f32 v8, -v9, v11, v8
1672; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1673; CI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
1674; CI-NEXT:    v_div_fixup_f32 v8, v8, v7, v3
1675; CI-NEXT:    v_trunc_f32_e32 v8, v8
1676; CI-NEXT:    v_fma_f32 v3, -v8, v7, v3
1677; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v6, v6, v2
1678; CI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
1679; CI-NEXT:    v_rcp_f32_e32 v9, v8
1680; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1681; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
1682; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
1683; CI-NEXT:    v_mul_f32_e32 v10, v7, v9
1684; CI-NEXT:    v_fma_f32 v11, -v8, v10, v7
1685; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
1686; CI-NEXT:    v_fma_f32 v7, -v8, v10, v7
1687; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1688; CI-NEXT:    v_div_fmas_f32 v7, v7, v9, v10
1689; CI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
1690; CI-NEXT:    v_trunc_f32_e32 v7, v7
1691; CI-NEXT:    v_fma_f32 v2, -v7, v6, v2
1692; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v5, v5, v1
1693; CI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
1694; CI-NEXT:    v_rcp_f32_e32 v8, v7
1695; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1696; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
1697; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
1698; CI-NEXT:    v_mul_f32_e32 v9, v6, v8
1699; CI-NEXT:    v_fma_f32 v10, -v7, v9, v6
1700; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
1701; CI-NEXT:    v_fma_f32 v6, -v7, v9, v6
1702; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1703; CI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
1704; CI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
1705; CI-NEXT:    v_trunc_f32_e32 v6, v6
1706; CI-NEXT:    v_fma_f32 v1, -v6, v5, v1
1707; CI-NEXT:    v_div_scale_f32 v6, s[4:5], v4, v4, v0
1708; CI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
1709; CI-NEXT:    v_rcp_f32_e32 v7, v6
1710; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1711; CI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
1712; CI-NEXT:    v_fma_f32 v7, v8, v7, v7
1713; CI-NEXT:    v_mul_f32_e32 v8, v5, v7
1714; CI-NEXT:    v_fma_f32 v9, -v6, v8, v5
1715; CI-NEXT:    v_fma_f32 v8, v9, v7, v8
1716; CI-NEXT:    v_fma_f32 v5, -v6, v8, v5
1717; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1718; CI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
1719; CI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
1720; CI-NEXT:    v_trunc_f32_e32 v5, v5
1721; CI-NEXT:    v_fma_f32 v0, -v5, v4, v0
1722; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1723; CI-NEXT:    s_endpgm
1724;
1725; VI-LABEL: frem_v4f32:
1726; VI:       ; %bb.0:
1727; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1728; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1729; VI-NEXT:    s_mov_b32 s2, 3
1730; VI-NEXT:    s_mov_b32 s3, 0
1731; VI-NEXT:    s_waitcnt lgkmcnt(0)
1732; VI-NEXT:    v_mov_b32_e32 v0, s6
1733; VI-NEXT:    s_add_u32 s0, s0, 64
1734; VI-NEXT:    s_addc_u32 s1, s1, 0
1735; VI-NEXT:    v_mov_b32_e32 v5, s1
1736; VI-NEXT:    v_mov_b32_e32 v1, s7
1737; VI-NEXT:    v_mov_b32_e32 v4, s0
1738; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
1739; VI-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]
1740; VI-NEXT:    v_mov_b32_e32 v8, s4
1741; VI-NEXT:    v_mov_b32_e32 v9, s5
1742; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1743; VI-NEXT:    v_div_scale_f32 v11, s[0:1], v7, v7, v3
1744; VI-NEXT:    v_div_scale_f32 v10, vcc, v3, v7, v3
1745; VI-NEXT:    v_rcp_f32_e32 v12, v11
1746; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1747; VI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
1748; VI-NEXT:    v_fma_f32 v12, v13, v12, v12
1749; VI-NEXT:    v_mul_f32_e32 v13, v10, v12
1750; VI-NEXT:    v_fma_f32 v14, -v11, v13, v10
1751; VI-NEXT:    v_fma_f32 v13, v14, v12, v13
1752; VI-NEXT:    v_fma_f32 v10, -v11, v13, v10
1753; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1754; VI-NEXT:    v_div_fmas_f32 v10, v10, v12, v13
1755; VI-NEXT:    v_div_fixup_f32 v10, v10, v7, v3
1756; VI-NEXT:    v_trunc_f32_e32 v10, v10
1757; VI-NEXT:    v_fma_f32 v3, -v10, v7, v3
1758; VI-NEXT:    v_div_scale_f32 v10, s[0:1], v6, v6, v2
1759; VI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
1760; VI-NEXT:    v_rcp_f32_e32 v11, v10
1761; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1762; VI-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
1763; VI-NEXT:    v_fma_f32 v11, v12, v11, v11
1764; VI-NEXT:    v_mul_f32_e32 v12, v7, v11
1765; VI-NEXT:    v_fma_f32 v13, -v10, v12, v7
1766; VI-NEXT:    v_fma_f32 v12, v13, v11, v12
1767; VI-NEXT:    v_fma_f32 v7, -v10, v12, v7
1768; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1769; VI-NEXT:    v_div_fmas_f32 v7, v7, v11, v12
1770; VI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
1771; VI-NEXT:    v_trunc_f32_e32 v7, v7
1772; VI-NEXT:    v_fma_f32 v2, -v7, v6, v2
1773; VI-NEXT:    v_div_scale_f32 v7, s[0:1], v5, v5, v1
1774; VI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
1775; VI-NEXT:    v_rcp_f32_e32 v10, v7
1776; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1777; VI-NEXT:    v_fma_f32 v11, -v7, v10, 1.0
1778; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
1779; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
1780; VI-NEXT:    v_fma_f32 v12, -v7, v11, v6
1781; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
1782; VI-NEXT:    v_fma_f32 v6, -v7, v11, v6
1783; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1784; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
1785; VI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
1786; VI-NEXT:    v_trunc_f32_e32 v6, v6
1787; VI-NEXT:    v_fma_f32 v1, -v6, v5, v1
1788; VI-NEXT:    v_div_scale_f32 v6, s[0:1], v4, v4, v0
1789; VI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
1790; VI-NEXT:    v_rcp_f32_e32 v7, v6
1791; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1792; VI-NEXT:    v_fma_f32 v10, -v6, v7, 1.0
1793; VI-NEXT:    v_fma_f32 v7, v10, v7, v7
1794; VI-NEXT:    v_mul_f32_e32 v10, v5, v7
1795; VI-NEXT:    v_fma_f32 v11, -v6, v10, v5
1796; VI-NEXT:    v_fma_f32 v10, v11, v7, v10
1797; VI-NEXT:    v_fma_f32 v5, -v6, v10, v5
1798; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1799; VI-NEXT:    v_div_fmas_f32 v5, v5, v7, v10
1800; VI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
1801; VI-NEXT:    v_trunc_f32_e32 v5, v5
1802; VI-NEXT:    v_fma_f32 v0, -v5, v4, v0
1803; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
1804; VI-NEXT:    s_endpgm
1805                        <4 x float> addrspace(1)* %in2) #0 {
1806   %gep2 = getelementptr <4 x float>, <4 x float> addrspace(1)* %in2, i32 4
1807   %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1, align 16
1808   %r1 = load <4 x float>, <4 x float> addrspace(1)* %gep2, align 16
1809   %r2 = frem <4 x float> %r0, %r1
1810   store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16
1811   ret void
1812}
1813
1814define amdgpu_kernel void @frem_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
1815; SI-LABEL: frem_v2f64:
1816; SI:       ; %bb.0:
1817; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
1818; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
1819; SI-NEXT:    s_mov_b32 s7, 0xf000
1820; SI-NEXT:    s_mov_b32 s6, -1
1821; SI-NEXT:    s_waitcnt lgkmcnt(0)
1822; SI-NEXT:    s_mov_b32 s4, s8
1823; SI-NEXT:    s_mov_b32 s5, s9
1824; SI-NEXT:    s_mov_b32 s0, s10
1825; SI-NEXT:    s_mov_b32 s1, s11
1826; SI-NEXT:    s_mov_b32 s2, s6
1827; SI-NEXT:    s_mov_b32 s3, s7
1828; SI-NEXT:    s_mov_b32 s14, s6
1829; SI-NEXT:    s_mov_b32 s15, s7
1830; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
1831; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[12:15], 0 offset:64
1832; SI-NEXT:    s_waitcnt vmcnt(0)
1833; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[6:7], v[6:7], v[2:3]
1834; SI-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
1835; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
1836; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1837; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
1838; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1839; SI-NEXT:    v_div_scale_f64 v[12:13], s[0:1], v[2:3], v[6:7], v[2:3]
1840; SI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
1841; SI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], v[12:13]
1842; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v9
1843; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v3, v13
1844; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
1845; SI-NEXT:    s_nop 0
1846; SI-NEXT:    s_nop 0
1847; SI-NEXT:    v_div_fmas_f64 v[8:9], v[16:17], v[10:11], v[14:15]
1848; SI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
1849; SI-NEXT:    v_bfe_u32 v10, v9, 20, 11
1850; SI-NEXT:    s_movk_i32 s8, 0xfc01
1851; SI-NEXT:    v_add_i32_e32 v12, vcc, s8, v10
1852; SI-NEXT:    s_mov_b32 s3, 0xfffff
1853; SI-NEXT:    v_lshr_b64 v[10:11], s[2:3], v12
1854; SI-NEXT:    v_not_b32_e32 v10, v10
1855; SI-NEXT:    v_and_b32_e32 v10, v8, v10
1856; SI-NEXT:    v_not_b32_e32 v11, v11
1857; SI-NEXT:    v_and_b32_e32 v11, v9, v11
1858; SI-NEXT:    s_brev_b32 s9, 1
1859; SI-NEXT:    v_and_b32_e32 v13, s9, v9
1860; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v12
1861; SI-NEXT:    v_cndmask_b32_e32 v11, v11, v13, vcc
1862; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v12
1863; SI-NEXT:    v_cndmask_b32_e64 v9, v11, v9, s[0:1]
1864; SI-NEXT:    v_cndmask_b32_e64 v10, v10, 0, vcc
1865; SI-NEXT:    v_cndmask_b32_e64 v8, v10, v8, s[0:1]
1866; SI-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
1867; SI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[0:1]
1868; SI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
1869; SI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
1870; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
1871; SI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
1872; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
1873; SI-NEXT:    v_div_scale_f64 v[10:11], s[0:1], v[0:1], v[4:5], v[0:1]
1874; SI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
1875; SI-NEXT:    v_fma_f64 v[14:15], -v[6:7], v[12:13], v[10:11]
1876; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v7
1877; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v11
1878; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
1879; SI-NEXT:    s_nop 0
1880; SI-NEXT:    s_nop 0
1881; SI-NEXT:    v_div_fmas_f64 v[6:7], v[14:15], v[8:9], v[12:13]
1882; SI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
1883; SI-NEXT:    v_bfe_u32 v8, v7, 20, 11
1884; SI-NEXT:    v_add_i32_e32 v10, vcc, s8, v8
1885; SI-NEXT:    v_lshr_b64 v[8:9], s[2:3], v10
1886; SI-NEXT:    v_not_b32_e32 v8, v8
1887; SI-NEXT:    v_and_b32_e32 v8, v6, v8
1888; SI-NEXT:    v_not_b32_e32 v9, v9
1889; SI-NEXT:    v_and_b32_e32 v9, v7, v9
1890; SI-NEXT:    v_and_b32_e32 v11, s9, v7
1891; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v10
1892; SI-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
1893; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v10
1894; SI-NEXT:    v_cndmask_b32_e64 v7, v9, v7, s[0:1]
1895; SI-NEXT:    v_cndmask_b32_e64 v8, v8, 0, vcc
1896; SI-NEXT:    v_cndmask_b32_e64 v6, v8, v6, s[0:1]
1897; SI-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
1898; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
1899; SI-NEXT:    s_endpgm
1900;
1901; CI-LABEL: frem_v2f64:
1902; CI:       ; %bb.0:
1903; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1904; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1905; CI-NEXT:    s_mov_b32 s3, 0xf000
1906; CI-NEXT:    s_mov_b32 s2, -1
1907; CI-NEXT:    s_mov_b32 s10, s2
1908; CI-NEXT:    s_waitcnt lgkmcnt(0)
1909; CI-NEXT:    s_mov_b32 s0, s4
1910; CI-NEXT:    s_mov_b32 s1, s5
1911; CI-NEXT:    s_mov_b32 s4, s6
1912; CI-NEXT:    s_mov_b32 s5, s7
1913; CI-NEXT:    s_mov_b32 s6, s2
1914; CI-NEXT:    s_mov_b32 s7, s3
1915; CI-NEXT:    s_mov_b32 s11, s3
1916; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
1917; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:64
1918; CI-NEXT:    s_waitcnt vmcnt(0)
1919; CI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[6:7], v[6:7], v[2:3]
1920; CI-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
1921; CI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
1922; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1923; CI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
1924; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1925; CI-NEXT:    v_div_scale_f64 v[12:13], vcc, v[2:3], v[6:7], v[2:3]
1926; CI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
1927; CI-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
1928; CI-NEXT:    s_nop 1
1929; CI-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
1930; CI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
1931; CI-NEXT:    v_trunc_f64_e32 v[8:9], v[8:9]
1932; CI-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
1933; CI-NEXT:    v_div_scale_f64 v[6:7], s[4:5], v[4:5], v[4:5], v[0:1]
1934; CI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
1935; CI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
1936; CI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
1937; CI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
1938; CI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
1939; CI-NEXT:    v_div_scale_f64 v[10:11], vcc, v[0:1], v[4:5], v[0:1]
1940; CI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
1941; CI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
1942; CI-NEXT:    s_nop 1
1943; CI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
1944; CI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
1945; CI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
1946; CI-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
1947; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1948; CI-NEXT:    s_endpgm
1949;
1950; VI-LABEL: frem_v2f64:
1951; VI:       ; %bb.0:
1952; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1953; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1954; VI-NEXT:    s_waitcnt lgkmcnt(0)
1955; VI-NEXT:    v_mov_b32_e32 v0, s6
1956; VI-NEXT:    s_add_u32 s0, s0, 64
1957; VI-NEXT:    s_addc_u32 s1, s1, 0
1958; VI-NEXT:    v_mov_b32_e32 v5, s1
1959; VI-NEXT:    v_mov_b32_e32 v1, s7
1960; VI-NEXT:    v_mov_b32_e32 v4, s0
1961; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
1962; VI-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]
1963; VI-NEXT:    v_mov_b32_e32 v8, s4
1964; VI-NEXT:    v_mov_b32_e32 v9, s5
1965; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
1966; VI-NEXT:    v_div_scale_f64 v[10:11], s[0:1], v[6:7], v[6:7], v[2:3]
1967; VI-NEXT:    v_rcp_f64_e32 v[12:13], v[10:11]
1968; VI-NEXT:    v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
1969; VI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
1970; VI-NEXT:    v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
1971; VI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
1972; VI-NEXT:    v_div_scale_f64 v[14:15], vcc, v[2:3], v[6:7], v[2:3]
1973; VI-NEXT:    v_mul_f64 v[16:17], v[14:15], v[12:13]
1974; VI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
1975; VI-NEXT:    s_nop 1
1976; VI-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
1977; VI-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[6:7], v[2:3]
1978; VI-NEXT:    v_trunc_f64_e32 v[10:11], v[10:11]
1979; VI-NEXT:    v_fma_f64 v[2:3], -v[10:11], v[6:7], v[2:3]
1980; VI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[0:1]
1981; VI-NEXT:    v_rcp_f64_e32 v[10:11], v[6:7]
1982; VI-NEXT:    v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
1983; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1984; VI-NEXT:    v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
1985; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1986; VI-NEXT:    v_div_scale_f64 v[12:13], vcc, v[0:1], v[4:5], v[0:1]
1987; VI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
1988; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[14:15], v[12:13]
1989; VI-NEXT:    s_nop 1
1990; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[14:15]
1991; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
1992; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
1993; VI-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
1994; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
1995; VI-NEXT:    s_endpgm
1996                        <2 x double> addrspace(1)* %in2) #0 {
1997   %gep2 = getelementptr <2 x double>, <2 x double> addrspace(1)* %in2, i32 4
1998   %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1, align 16
1999   %r1 = load <2 x double>, <2 x double> addrspace(1)* %gep2, align 16
2000   %r2 = frem <2 x double> %r0, %r1
2001   store <2 x double> %r2, <2 x double> addrspace(1)* %out, align 16
2002   ret void
2003}
2004
2005attributes #0 = { nounwind "unsafe-fp-math"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
2006attributes #1 = { nounwind "unsafe-fp-math"="true" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
2007