1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mattr=+mad-mac-f32-insts -verify-machineinstrs  < %s | FileCheck -check-prefixes=GCN,SI %s
3; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
4; RUN:  llc -amdgpu-scalarize-global-loads=false -enable-misched=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
5
6define amdgpu_kernel void @frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
7; SI-LABEL: frem_f16:
8; SI:       ; %bb.0:
9; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
10; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
11; SI-NEXT:    s_mov_b32 s3, 0xf000
12; SI-NEXT:    s_mov_b32 s2, -1
13; SI-NEXT:    s_waitcnt lgkmcnt(0)
14; SI-NEXT:    s_mov_b32 s0, s4
15; SI-NEXT:    s_mov_b32 s1, s5
16; SI-NEXT:    s_mov_b32 s4, s6
17; SI-NEXT:    s_mov_b32 s5, s7
18; SI-NEXT:    s_mov_b32 s6, s2
19; SI-NEXT:    s_mov_b32 s7, s3
20; SI-NEXT:    s_mov_b32 s10, s2
21; SI-NEXT:    s_mov_b32 s11, s3
22; SI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
23; SI-NEXT:    s_waitcnt vmcnt(0)
24; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
25; SI-NEXT:    buffer_load_ushort v1, off, s[8:11], 0 offset:8
26; SI-NEXT:    s_waitcnt vmcnt(0)
27; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
28; SI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
29; SI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
30; SI-NEXT:    v_rcp_f32_e32 v4, v3
31; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
32; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
33; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
34; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
35; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
36; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
37; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
38; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
39; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
40; SI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
41; SI-NEXT:    v_trunc_f32_e32 v2, v2
42; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
43; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
44; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
45; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
46; SI-NEXT:    s_endpgm
47;
48; CI-LABEL: frem_f16:
49; CI:       ; %bb.0:
50; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
51; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
52; CI-NEXT:    s_mov_b32 s11, 0xf000
53; CI-NEXT:    s_mov_b32 s10, -1
54; CI-NEXT:    s_mov_b32 s2, s10
55; CI-NEXT:    s_waitcnt lgkmcnt(0)
56; CI-NEXT:    s_mov_b32 s8, s4
57; CI-NEXT:    s_mov_b32 s9, s5
58; CI-NEXT:    s_mov_b32 s4, s6
59; CI-NEXT:    s_mov_b32 s5, s7
60; CI-NEXT:    s_mov_b32 s3, s11
61; CI-NEXT:    s_mov_b32 s6, s10
62; CI-NEXT:    s_mov_b32 s7, s11
63; CI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
64; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
65; CI-NEXT:    s_waitcnt vmcnt(1)
66; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
67; CI-NEXT:    s_waitcnt vmcnt(0)
68; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
69; CI-NEXT:    v_div_scale_f32 v3, s[0:1], v1, v1, v0
70; CI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
71; CI-NEXT:    v_rcp_f32_e32 v4, v3
72; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
73; CI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
74; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
75; CI-NEXT:    v_mul_f32_e32 v5, v2, v4
76; CI-NEXT:    v_fma_f32 v6, -v3, v5, v2
77; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
78; CI-NEXT:    v_fma_f32 v2, -v3, v5, v2
79; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
80; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
81; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
82; CI-NEXT:    v_trunc_f32_e32 v2, v2
83; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
84; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
85; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
86; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
87; CI-NEXT:    s_endpgm
88;
89; VI-LABEL: frem_f16:
90; VI:       ; %bb.0:
91; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
92; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
93; VI-NEXT:    s_waitcnt lgkmcnt(0)
94; VI-NEXT:    v_mov_b32_e32 v2, s6
95; VI-NEXT:    s_add_u32 s0, s0, 8
96; VI-NEXT:    v_mov_b32_e32 v3, s7
97; VI-NEXT:    s_addc_u32 s1, s1, 0
98; VI-NEXT:    flat_load_ushort v4, v[2:3]
99; VI-NEXT:    v_mov_b32_e32 v3, s1
100; VI-NEXT:    v_mov_b32_e32 v2, s0
101; VI-NEXT:    flat_load_ushort v2, v[2:3]
102; VI-NEXT:    v_mov_b32_e32 v0, s4
103; VI-NEXT:    v_mov_b32_e32 v1, s5
104; VI-NEXT:    s_waitcnt vmcnt(1)
105; VI-NEXT:    v_cvt_f32_f16_e32 v3, v4
106; VI-NEXT:    s_waitcnt vmcnt(0)
107; VI-NEXT:    v_cvt_f32_f16_e32 v5, v2
108; VI-NEXT:    v_rcp_f32_e32 v5, v5
109; VI-NEXT:    v_mul_f32_e32 v3, v3, v5
110; VI-NEXT:    v_cvt_f16_f32_e32 v3, v3
111; VI-NEXT:    v_div_fixup_f16 v3, v3, v2, v4
112; VI-NEXT:    v_trunc_f16_e32 v3, v3
113; VI-NEXT:    v_fma_f16 v2, -v3, v2, v4
114; VI-NEXT:    flat_store_short v[0:1], v2
115; VI-NEXT:    s_endpgm
116                      half addrspace(1)* %in2) #0 {
117   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
118   %r0 = load half, half addrspace(1)* %in1, align 4
119   %r1 = load half, half addrspace(1)* %gep2, align 4
120   %r2 = frem half %r0, %r1
121   store half %r2, half addrspace(1)* %out, align 4
122   ret void
123}
124
125define amdgpu_kernel void @fast_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
126; SI-LABEL: fast_frem_f16:
127; SI:       ; %bb.0:
128; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
129; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
130; SI-NEXT:    s_mov_b32 s3, 0xf000
131; SI-NEXT:    s_mov_b32 s2, -1
132; SI-NEXT:    s_waitcnt lgkmcnt(0)
133; SI-NEXT:    s_mov_b32 s0, s4
134; SI-NEXT:    s_mov_b32 s1, s5
135; SI-NEXT:    s_mov_b32 s4, s6
136; SI-NEXT:    s_mov_b32 s5, s7
137; SI-NEXT:    s_mov_b32 s6, s2
138; SI-NEXT:    s_mov_b32 s7, s3
139; SI-NEXT:    s_mov_b32 s10, s2
140; SI-NEXT:    s_mov_b32 s11, s3
141; SI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
142; SI-NEXT:    s_waitcnt vmcnt(0)
143; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
144; SI-NEXT:    buffer_load_ushort v1, off, s[8:11], 0 offset:8
145; SI-NEXT:    s_waitcnt vmcnt(0)
146; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
147; SI-NEXT:    v_rcp_f32_e32 v2, v1
148; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
149; SI-NEXT:    v_trunc_f32_e32 v2, v2
150; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
151; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
152; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
153; SI-NEXT:    s_endpgm
154;
155; CI-LABEL: fast_frem_f16:
156; CI:       ; %bb.0:
157; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
158; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
159; CI-NEXT:    s_mov_b32 s11, 0xf000
160; CI-NEXT:    s_mov_b32 s10, -1
161; CI-NEXT:    s_mov_b32 s2, s10
162; CI-NEXT:    s_mov_b32 s3, s11
163; CI-NEXT:    s_waitcnt lgkmcnt(0)
164; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
165; CI-NEXT:    s_mov_b32 s8, s4
166; CI-NEXT:    s_mov_b32 s9, s5
167; CI-NEXT:    s_mov_b32 s4, s6
168; CI-NEXT:    s_mov_b32 s5, s7
169; CI-NEXT:    s_mov_b32 s6, s10
170; CI-NEXT:    s_mov_b32 s7, s11
171; CI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
172; CI-NEXT:    s_waitcnt vmcnt(1)
173; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
174; CI-NEXT:    v_rcp_f32_e32 v2, v1
175; CI-NEXT:    s_waitcnt vmcnt(0)
176; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
177; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
178; CI-NEXT:    v_trunc_f32_e32 v2, v2
179; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
180; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
181; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
182; CI-NEXT:    s_endpgm
183;
184; VI-LABEL: fast_frem_f16:
185; VI:       ; %bb.0:
186; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
187; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
188; VI-NEXT:    s_waitcnt lgkmcnt(0)
189; VI-NEXT:    v_mov_b32_e32 v2, s6
190; VI-NEXT:    s_add_u32 s0, s0, 8
191; VI-NEXT:    v_mov_b32_e32 v3, s7
192; VI-NEXT:    s_addc_u32 s1, s1, 0
193; VI-NEXT:    flat_load_ushort v4, v[2:3]
194; VI-NEXT:    v_mov_b32_e32 v3, s1
195; VI-NEXT:    v_mov_b32_e32 v2, s0
196; VI-NEXT:    flat_load_ushort v2, v[2:3]
197; VI-NEXT:    v_mov_b32_e32 v0, s4
198; VI-NEXT:    v_mov_b32_e32 v1, s5
199; VI-NEXT:    s_waitcnt vmcnt(0)
200; VI-NEXT:    v_rcp_f16_e32 v3, v2
201; VI-NEXT:    v_mul_f16_e32 v3, v4, v3
202; VI-NEXT:    v_trunc_f16_e32 v3, v3
203; VI-NEXT:    v_fma_f16 v2, -v3, v2, v4
204; VI-NEXT:    flat_store_short v[0:1], v2
205; VI-NEXT:    s_endpgm
206                      half addrspace(1)* %in2) #0 {
207   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
208   %r0 = load half, half addrspace(1)* %in1, align 4
209   %r1 = load half, half addrspace(1)* %gep2, align 4
210   %r2 = frem fast half %r0, %r1
211   store half %r2, half addrspace(1)* %out, align 4
212   ret void
213}
214
215define amdgpu_kernel void @unsafe_frem_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
216; SI-LABEL: unsafe_frem_f16:
217; SI:       ; %bb.0:
218; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
219; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
220; SI-NEXT:    s_mov_b32 s3, 0xf000
221; SI-NEXT:    s_mov_b32 s2, -1
222; SI-NEXT:    s_waitcnt lgkmcnt(0)
223; SI-NEXT:    s_mov_b32 s0, s4
224; SI-NEXT:    s_mov_b32 s1, s5
225; SI-NEXT:    s_mov_b32 s4, s6
226; SI-NEXT:    s_mov_b32 s5, s7
227; SI-NEXT:    s_mov_b32 s6, s2
228; SI-NEXT:    s_mov_b32 s7, s3
229; SI-NEXT:    s_mov_b32 s10, s2
230; SI-NEXT:    s_mov_b32 s11, s3
231; SI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
232; SI-NEXT:    s_waitcnt vmcnt(0)
233; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
234; SI-NEXT:    buffer_load_ushort v1, off, s[8:11], 0 offset:8
235; SI-NEXT:    s_waitcnt vmcnt(0)
236; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
237; SI-NEXT:    v_rcp_f32_e32 v2, v1
238; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
239; SI-NEXT:    v_trunc_f32_e32 v2, v2
240; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
241; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
242; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
243; SI-NEXT:    s_endpgm
244;
245; CI-LABEL: unsafe_frem_f16:
246; CI:       ; %bb.0:
247; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
248; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
249; CI-NEXT:    s_mov_b32 s11, 0xf000
250; CI-NEXT:    s_mov_b32 s10, -1
251; CI-NEXT:    s_mov_b32 s2, s10
252; CI-NEXT:    s_mov_b32 s3, s11
253; CI-NEXT:    s_waitcnt lgkmcnt(0)
254; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
255; CI-NEXT:    s_mov_b32 s8, s4
256; CI-NEXT:    s_mov_b32 s9, s5
257; CI-NEXT:    s_mov_b32 s4, s6
258; CI-NEXT:    s_mov_b32 s5, s7
259; CI-NEXT:    s_mov_b32 s6, s10
260; CI-NEXT:    s_mov_b32 s7, s11
261; CI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
262; CI-NEXT:    s_waitcnt vmcnt(1)
263; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
264; CI-NEXT:    v_rcp_f32_e32 v2, v1
265; CI-NEXT:    s_waitcnt vmcnt(0)
266; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
267; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
268; CI-NEXT:    v_trunc_f32_e32 v2, v2
269; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
270; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
271; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
272; CI-NEXT:    s_endpgm
273;
274; VI-LABEL: unsafe_frem_f16:
275; VI:       ; %bb.0:
276; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
277; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
278; VI-NEXT:    s_waitcnt lgkmcnt(0)
279; VI-NEXT:    v_mov_b32_e32 v2, s6
280; VI-NEXT:    s_add_u32 s0, s0, 8
281; VI-NEXT:    v_mov_b32_e32 v3, s7
282; VI-NEXT:    s_addc_u32 s1, s1, 0
283; VI-NEXT:    flat_load_ushort v4, v[2:3]
284; VI-NEXT:    v_mov_b32_e32 v3, s1
285; VI-NEXT:    v_mov_b32_e32 v2, s0
286; VI-NEXT:    flat_load_ushort v2, v[2:3]
287; VI-NEXT:    v_mov_b32_e32 v0, s4
288; VI-NEXT:    v_mov_b32_e32 v1, s5
289; VI-NEXT:    s_waitcnt vmcnt(0)
290; VI-NEXT:    v_rcp_f16_e32 v3, v2
291; VI-NEXT:    v_mul_f16_e32 v3, v4, v3
292; VI-NEXT:    v_trunc_f16_e32 v3, v3
293; VI-NEXT:    v_fma_f16 v2, -v3, v2, v4
294; VI-NEXT:    flat_store_short v[0:1], v2
295; VI-NEXT:    s_endpgm
296                             half addrspace(1)* %in2) #1 {
297   %gep2 = getelementptr half, half addrspace(1)* %in2, i32 4
298   %r0 = load half, half addrspace(1)* %in1, align 4
299   %r1 = load half, half addrspace(1)* %gep2, align 4
300   %r2 = frem half %r0, %r1
301   store half %r2, half addrspace(1)* %out, align 4
302   ret void
303}
304
305define amdgpu_kernel void @frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
306; SI-LABEL: frem_f32:
307; SI:       ; %bb.0:
308; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
309; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
310; SI-NEXT:    s_mov_b32 s3, 0xf000
311; SI-NEXT:    s_mov_b32 s2, -1
312; SI-NEXT:    s_waitcnt lgkmcnt(0)
313; SI-NEXT:    s_mov_b32 s0, s4
314; SI-NEXT:    s_mov_b32 s1, s5
315; SI-NEXT:    s_mov_b32 s4, s6
316; SI-NEXT:    s_mov_b32 s5, s7
317; SI-NEXT:    s_mov_b32 s6, s2
318; SI-NEXT:    s_mov_b32 s7, s3
319; SI-NEXT:    s_mov_b32 s10, s2
320; SI-NEXT:    s_mov_b32 s11, s3
321; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
322; SI-NEXT:    buffer_load_dword v1, off, s[8:11], 0 offset:16
323; SI-NEXT:    s_waitcnt vmcnt(0)
324; SI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
325; SI-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
326; SI-NEXT:    v_rcp_f32_e32 v4, v3
327; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
328; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
329; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
330; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
331; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
332; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
333; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
334; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
335; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
336; SI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
337; SI-NEXT:    v_trunc_f32_e32 v2, v2
338; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
339; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
340; SI-NEXT:    s_endpgm
341;
342; CI-LABEL: frem_f32:
343; CI:       ; %bb.0:
344; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
345; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
346; CI-NEXT:    s_mov_b32 s11, 0xf000
347; CI-NEXT:    s_mov_b32 s10, -1
348; CI-NEXT:    s_mov_b32 s2, s10
349; CI-NEXT:    s_waitcnt lgkmcnt(0)
350; CI-NEXT:    s_mov_b32 s8, s4
351; CI-NEXT:    s_mov_b32 s9, s5
352; CI-NEXT:    s_mov_b32 s4, s6
353; CI-NEXT:    s_mov_b32 s5, s7
354; CI-NEXT:    s_mov_b32 s6, s10
355; CI-NEXT:    s_mov_b32 s7, s11
356; CI-NEXT:    s_mov_b32 s3, s11
357; CI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
358; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:16
359; CI-NEXT:    s_waitcnt vmcnt(0)
360; CI-NEXT:    v_div_scale_f32 v3, s[0:1], v1, v1, v0
361; CI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
362; CI-NEXT:    v_rcp_f32_e32 v4, v3
363; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
364; CI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
365; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
366; CI-NEXT:    v_mul_f32_e32 v5, v2, v4
367; CI-NEXT:    v_fma_f32 v6, -v3, v5, v2
368; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
369; CI-NEXT:    v_fma_f32 v2, -v3, v5, v2
370; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
371; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
372; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
373; CI-NEXT:    v_trunc_f32_e32 v2, v2
374; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
375; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
376; CI-NEXT:    s_endpgm
377;
378; VI-LABEL: frem_f32:
379; VI:       ; %bb.0:
380; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
381; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
382; VI-NEXT:    s_waitcnt lgkmcnt(0)
383; VI-NEXT:    v_mov_b32_e32 v2, s6
384; VI-NEXT:    s_add_u32 s0, s0, 16
385; VI-NEXT:    v_mov_b32_e32 v3, s7
386; VI-NEXT:    s_addc_u32 s1, s1, 0
387; VI-NEXT:    flat_load_dword v4, v[2:3]
388; VI-NEXT:    v_mov_b32_e32 v3, s1
389; VI-NEXT:    v_mov_b32_e32 v2, s0
390; VI-NEXT:    flat_load_dword v2, v[2:3]
391; VI-NEXT:    v_mov_b32_e32 v0, s4
392; VI-NEXT:    v_mov_b32_e32 v1, s5
393; VI-NEXT:    s_waitcnt vmcnt(0)
394; VI-NEXT:    v_div_scale_f32 v5, s[0:1], v2, v2, v4
395; VI-NEXT:    v_div_scale_f32 v3, vcc, v4, v2, v4
396; VI-NEXT:    v_rcp_f32_e32 v6, v5
397; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
398; VI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
399; VI-NEXT:    v_fma_f32 v6, v7, v6, v6
400; VI-NEXT:    v_mul_f32_e32 v7, v3, v6
401; VI-NEXT:    v_fma_f32 v8, -v5, v7, v3
402; VI-NEXT:    v_fma_f32 v7, v8, v6, v7
403; VI-NEXT:    v_fma_f32 v3, -v5, v7, v3
404; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
405; VI-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
406; VI-NEXT:    v_div_fixup_f32 v3, v3, v2, v4
407; VI-NEXT:    v_trunc_f32_e32 v3, v3
408; VI-NEXT:    v_fma_f32 v2, -v3, v2, v4
409; VI-NEXT:    flat_store_dword v[0:1], v2
410; VI-NEXT:    s_endpgm
411                      float addrspace(1)* %in2) #0 {
412   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
413   %r0 = load float, float addrspace(1)* %in1, align 4
414   %r1 = load float, float addrspace(1)* %gep2, align 4
415   %r2 = frem float %r0, %r1
416   store float %r2, float addrspace(1)* %out, align 4
417   ret void
418}
419
420define amdgpu_kernel void @fast_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
421; SI-LABEL: fast_frem_f32:
422; SI:       ; %bb.0:
423; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
424; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
425; SI-NEXT:    s_mov_b32 s3, 0xf000
426; SI-NEXT:    s_mov_b32 s2, -1
427; SI-NEXT:    s_waitcnt lgkmcnt(0)
428; SI-NEXT:    s_mov_b32 s0, s4
429; SI-NEXT:    s_mov_b32 s1, s5
430; SI-NEXT:    s_mov_b32 s4, s6
431; SI-NEXT:    s_mov_b32 s5, s7
432; SI-NEXT:    s_mov_b32 s6, s2
433; SI-NEXT:    s_mov_b32 s7, s3
434; SI-NEXT:    s_mov_b32 s10, s2
435; SI-NEXT:    s_mov_b32 s11, s3
436; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
437; SI-NEXT:    buffer_load_dword v1, off, s[8:11], 0 offset:16
438; SI-NEXT:    s_waitcnt vmcnt(0)
439; SI-NEXT:    v_rcp_f32_e32 v2, v1
440; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
441; SI-NEXT:    v_trunc_f32_e32 v2, v2
442; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
443; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
444; SI-NEXT:    s_endpgm
445;
446; CI-LABEL: fast_frem_f32:
447; CI:       ; %bb.0:
448; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
449; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
450; CI-NEXT:    s_mov_b32 s11, 0xf000
451; CI-NEXT:    s_mov_b32 s10, -1
452; CI-NEXT:    s_mov_b32 s2, s10
453; CI-NEXT:    s_waitcnt lgkmcnt(0)
454; CI-NEXT:    s_mov_b32 s8, s4
455; CI-NEXT:    s_mov_b32 s9, s5
456; CI-NEXT:    s_mov_b32 s4, s6
457; CI-NEXT:    s_mov_b32 s5, s7
458; CI-NEXT:    s_mov_b32 s6, s10
459; CI-NEXT:    s_mov_b32 s7, s11
460; CI-NEXT:    s_mov_b32 s3, s11
461; CI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
462; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:16
463; CI-NEXT:    s_waitcnt vmcnt(0)
464; CI-NEXT:    v_rcp_f32_e32 v2, v1
465; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
466; CI-NEXT:    v_trunc_f32_e32 v2, v2
467; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
468; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
469; CI-NEXT:    s_endpgm
470;
471; VI-LABEL: fast_frem_f32:
472; VI:       ; %bb.0:
473; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
474; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
475; VI-NEXT:    s_waitcnt lgkmcnt(0)
476; VI-NEXT:    v_mov_b32_e32 v2, s6
477; VI-NEXT:    s_add_u32 s0, s0, 16
478; VI-NEXT:    v_mov_b32_e32 v3, s7
479; VI-NEXT:    s_addc_u32 s1, s1, 0
480; VI-NEXT:    flat_load_dword v4, v[2:3]
481; VI-NEXT:    v_mov_b32_e32 v3, s1
482; VI-NEXT:    v_mov_b32_e32 v2, s0
483; VI-NEXT:    flat_load_dword v2, v[2:3]
484; VI-NEXT:    v_mov_b32_e32 v0, s4
485; VI-NEXT:    v_mov_b32_e32 v1, s5
486; VI-NEXT:    s_waitcnt vmcnt(0)
487; VI-NEXT:    v_rcp_f32_e32 v3, v2
488; VI-NEXT:    v_mul_f32_e32 v3, v4, v3
489; VI-NEXT:    v_trunc_f32_e32 v3, v3
490; VI-NEXT:    v_fma_f32 v2, -v3, v2, v4
491; VI-NEXT:    flat_store_dword v[0:1], v2
492; VI-NEXT:    s_endpgm
493                      float addrspace(1)* %in2) #0 {
494   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
495   %r0 = load float, float addrspace(1)* %in1, align 4
496   %r1 = load float, float addrspace(1)* %gep2, align 4
497   %r2 = frem fast float %r0, %r1
498   store float %r2, float addrspace(1)* %out, align 4
499   ret void
500}
501
502define amdgpu_kernel void @unsafe_frem_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
503; SI-LABEL: unsafe_frem_f32:
504; SI:       ; %bb.0:
505; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
506; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
507; SI-NEXT:    s_mov_b32 s3, 0xf000
508; SI-NEXT:    s_mov_b32 s2, -1
509; SI-NEXT:    s_waitcnt lgkmcnt(0)
510; SI-NEXT:    s_mov_b32 s0, s4
511; SI-NEXT:    s_mov_b32 s1, s5
512; SI-NEXT:    s_mov_b32 s4, s6
513; SI-NEXT:    s_mov_b32 s5, s7
514; SI-NEXT:    s_mov_b32 s6, s2
515; SI-NEXT:    s_mov_b32 s7, s3
516; SI-NEXT:    s_mov_b32 s10, s2
517; SI-NEXT:    s_mov_b32 s11, s3
518; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
519; SI-NEXT:    buffer_load_dword v1, off, s[8:11], 0 offset:16
520; SI-NEXT:    s_waitcnt vmcnt(0)
521; SI-NEXT:    v_rcp_f32_e32 v2, v1
522; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
523; SI-NEXT:    v_trunc_f32_e32 v2, v2
524; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
525; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
526; SI-NEXT:    s_endpgm
527;
528; CI-LABEL: unsafe_frem_f32:
529; CI:       ; %bb.0:
530; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
531; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
532; CI-NEXT:    s_mov_b32 s11, 0xf000
533; CI-NEXT:    s_mov_b32 s10, -1
534; CI-NEXT:    s_mov_b32 s2, s10
535; CI-NEXT:    s_waitcnt lgkmcnt(0)
536; CI-NEXT:    s_mov_b32 s8, s4
537; CI-NEXT:    s_mov_b32 s9, s5
538; CI-NEXT:    s_mov_b32 s4, s6
539; CI-NEXT:    s_mov_b32 s5, s7
540; CI-NEXT:    s_mov_b32 s6, s10
541; CI-NEXT:    s_mov_b32 s7, s11
542; CI-NEXT:    s_mov_b32 s3, s11
543; CI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
544; CI-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:16
545; CI-NEXT:    s_waitcnt vmcnt(0)
546; CI-NEXT:    v_rcp_f32_e32 v2, v1
547; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
548; CI-NEXT:    v_trunc_f32_e32 v2, v2
549; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
550; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
551; CI-NEXT:    s_endpgm
552;
553; VI-LABEL: unsafe_frem_f32:
554; VI:       ; %bb.0:
555; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
556; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
557; VI-NEXT:    s_waitcnt lgkmcnt(0)
558; VI-NEXT:    v_mov_b32_e32 v2, s6
559; VI-NEXT:    s_add_u32 s0, s0, 16
560; VI-NEXT:    v_mov_b32_e32 v3, s7
561; VI-NEXT:    s_addc_u32 s1, s1, 0
562; VI-NEXT:    flat_load_dword v4, v[2:3]
563; VI-NEXT:    v_mov_b32_e32 v3, s1
564; VI-NEXT:    v_mov_b32_e32 v2, s0
565; VI-NEXT:    flat_load_dword v2, v[2:3]
566; VI-NEXT:    v_mov_b32_e32 v0, s4
567; VI-NEXT:    v_mov_b32_e32 v1, s5
568; VI-NEXT:    s_waitcnt vmcnt(0)
569; VI-NEXT:    v_rcp_f32_e32 v3, v2
570; VI-NEXT:    v_mul_f32_e32 v3, v4, v3
571; VI-NEXT:    v_trunc_f32_e32 v3, v3
572; VI-NEXT:    v_fma_f32 v2, -v3, v2, v4
573; VI-NEXT:    flat_store_dword v[0:1], v2
574; VI-NEXT:    s_endpgm
575                             float addrspace(1)* %in2) #1 {
576   %gep2 = getelementptr float, float addrspace(1)* %in2, i32 4
577   %r0 = load float, float addrspace(1)* %in1, align 4
578   %r1 = load float, float addrspace(1)* %gep2, align 4
579   %r2 = frem float %r0, %r1
580   store float %r2, float addrspace(1)* %out, align 4
581   ret void
582}
583
584define amdgpu_kernel void @frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
585; SI-LABEL: frem_f64:
586; SI:       ; %bb.0:
587; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
588; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
589; SI-NEXT:    s_mov_b32 s7, 0xf000
590; SI-NEXT:    s_mov_b32 s6, -1
591; SI-NEXT:    s_waitcnt lgkmcnt(0)
592; SI-NEXT:    s_mov_b32 s4, s8
593; SI-NEXT:    s_mov_b32 s5, s9
594; SI-NEXT:    s_mov_b32 s0, s10
595; SI-NEXT:    s_mov_b32 s1, s11
596; SI-NEXT:    s_mov_b32 s2, s6
597; SI-NEXT:    s_mov_b32 s3, s7
598; SI-NEXT:    s_mov_b32 s14, s6
599; SI-NEXT:    s_mov_b32 s15, s7
600; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
601; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[12:15], 0
602; SI-NEXT:    s_waitcnt vmcnt(0)
603; SI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
604; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
605; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
606; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
607; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
608; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
609; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[0:1], v[2:3], v[0:1]
610; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
611; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
612; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
613; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v9
614; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
615; SI-NEXT:    s_nop 1
616; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
617; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
618; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
619; SI-NEXT:    v_add_i32_e32 v8, vcc, 0xfffffc01, v6
620; SI-NEXT:    s_mov_b32 s1, 0xfffff
621; SI-NEXT:    s_mov_b32 s0, s6
622; SI-NEXT:    v_lshr_b64 v[6:7], s[0:1], v8
623; SI-NEXT:    v_not_b32_e32 v6, v6
624; SI-NEXT:    v_and_b32_e32 v6, v4, v6
625; SI-NEXT:    v_not_b32_e32 v7, v7
626; SI-NEXT:    v_and_b32_e32 v7, v5, v7
627; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v5
628; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
629; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
630; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v8
631; SI-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[0:1]
632; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
633; SI-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[0:1]
634; SI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
635; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
636; SI-NEXT:    s_endpgm
637;
638; CI-LABEL: frem_f64:
639; CI:       ; %bb.0:
640; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
641; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
642; CI-NEXT:    s_mov_b32 s11, 0xf000
643; CI-NEXT:    s_mov_b32 s10, -1
644; CI-NEXT:    s_mov_b32 s2, s10
645; CI-NEXT:    s_waitcnt lgkmcnt(0)
646; CI-NEXT:    s_mov_b32 s8, s4
647; CI-NEXT:    s_mov_b32 s9, s5
648; CI-NEXT:    s_mov_b32 s4, s6
649; CI-NEXT:    s_mov_b32 s5, s7
650; CI-NEXT:    s_mov_b32 s6, s10
651; CI-NEXT:    s_mov_b32 s7, s11
652; CI-NEXT:    s_mov_b32 s3, s11
653; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
654; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
655; CI-NEXT:    s_waitcnt vmcnt(0)
656; CI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
657; CI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
658; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
659; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
660; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
661; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
662; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
663; CI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
664; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
665; CI-NEXT:    s_nop 1
666; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
667; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
668; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
669; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
670; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
671; CI-NEXT:    s_endpgm
672;
673; VI-LABEL: frem_f64:
674; VI:       ; %bb.0:
675; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
676; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
677; VI-NEXT:    s_waitcnt lgkmcnt(0)
678; VI-NEXT:    v_mov_b32_e32 v2, s6
679; VI-NEXT:    v_mov_b32_e32 v3, s7
680; VI-NEXT:    v_mov_b32_e32 v4, s0
681; VI-NEXT:    v_mov_b32_e32 v5, s1
682; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
683; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
684; VI-NEXT:    v_mov_b32_e32 v0, s4
685; VI-NEXT:    v_mov_b32_e32 v1, s5
686; VI-NEXT:    s_waitcnt vmcnt(0)
687; VI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[2:3]
688; VI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
689; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
690; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
691; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
692; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
693; VI-NEXT:    v_div_scale_f64 v[10:11], vcc, v[2:3], v[4:5], v[2:3]
694; VI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
695; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
696; VI-NEXT:    s_nop 1
697; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
698; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[2:3]
699; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
700; VI-NEXT:    v_fma_f64 v[2:3], -v[6:7], v[4:5], v[2:3]
701; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
702; VI-NEXT:    s_endpgm
703                      double addrspace(1)* %in2) #0 {
704   %r0 = load double, double addrspace(1)* %in1, align 8
705   %r1 = load double, double addrspace(1)* %in2, align 8
706   %r2 = frem double %r0, %r1
707   store double %r2, double addrspace(1)* %out, align 8
708   ret void
709}
710
711define amdgpu_kernel void @fast_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
712; SI-LABEL: fast_frem_f64:
713; SI:       ; %bb.0:
714; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
715; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
716; SI-NEXT:    s_mov_b32 s7, 0xf000
717; SI-NEXT:    s_mov_b32 s6, -1
718; SI-NEXT:    s_waitcnt lgkmcnt(0)
719; SI-NEXT:    s_mov_b32 s4, s8
720; SI-NEXT:    s_mov_b32 s5, s9
721; SI-NEXT:    s_mov_b32 s0, s10
722; SI-NEXT:    s_mov_b32 s1, s11
723; SI-NEXT:    s_mov_b32 s2, s6
724; SI-NEXT:    s_mov_b32 s3, s7
725; SI-NEXT:    s_mov_b32 s14, s6
726; SI-NEXT:    s_mov_b32 s15, s7
727; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
728; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[12:15], 0
729; SI-NEXT:    s_waitcnt vmcnt(0)
730; SI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
731; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
732; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
733; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
734; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
735; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
736; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[0:1], v[2:3], v[0:1]
737; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
738; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
739; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
740; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v9
741; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
742; SI-NEXT:    s_nop 1
743; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
744; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
745; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
746; SI-NEXT:    v_add_i32_e32 v8, vcc, 0xfffffc01, v6
747; SI-NEXT:    s_mov_b32 s1, 0xfffff
748; SI-NEXT:    s_mov_b32 s0, s6
749; SI-NEXT:    v_lshr_b64 v[6:7], s[0:1], v8
750; SI-NEXT:    v_not_b32_e32 v6, v6
751; SI-NEXT:    v_and_b32_e32 v6, v4, v6
752; SI-NEXT:    v_not_b32_e32 v7, v7
753; SI-NEXT:    v_and_b32_e32 v7, v5, v7
754; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v5
755; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
756; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
757; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v8
758; SI-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[0:1]
759; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
760; SI-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[0:1]
761; SI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
762; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
763; SI-NEXT:    s_endpgm
764;
765; CI-LABEL: fast_frem_f64:
766; CI:       ; %bb.0:
767; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
768; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
769; CI-NEXT:    s_mov_b32 s11, 0xf000
770; CI-NEXT:    s_mov_b32 s10, -1
771; CI-NEXT:    s_mov_b32 s2, s10
772; CI-NEXT:    s_waitcnt lgkmcnt(0)
773; CI-NEXT:    s_mov_b32 s8, s4
774; CI-NEXT:    s_mov_b32 s9, s5
775; CI-NEXT:    s_mov_b32 s4, s6
776; CI-NEXT:    s_mov_b32 s5, s7
777; CI-NEXT:    s_mov_b32 s6, s10
778; CI-NEXT:    s_mov_b32 s7, s11
779; CI-NEXT:    s_mov_b32 s3, s11
780; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
781; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
782; CI-NEXT:    s_waitcnt vmcnt(0)
783; CI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
784; CI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
785; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
786; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
787; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
788; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
789; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
790; CI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
791; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
792; CI-NEXT:    s_nop 1
793; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
794; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
795; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
796; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
797; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
798; CI-NEXT:    s_endpgm
799;
800; VI-LABEL: fast_frem_f64:
801; VI:       ; %bb.0:
802; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
803; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
804; VI-NEXT:    s_waitcnt lgkmcnt(0)
805; VI-NEXT:    v_mov_b32_e32 v2, s6
806; VI-NEXT:    v_mov_b32_e32 v3, s7
807; VI-NEXT:    v_mov_b32_e32 v4, s0
808; VI-NEXT:    v_mov_b32_e32 v5, s1
809; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
810; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
811; VI-NEXT:    v_mov_b32_e32 v0, s4
812; VI-NEXT:    v_mov_b32_e32 v1, s5
813; VI-NEXT:    s_waitcnt vmcnt(0)
814; VI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[2:3]
815; VI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
816; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
817; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
818; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
819; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
820; VI-NEXT:    v_div_scale_f64 v[10:11], vcc, v[2:3], v[4:5], v[2:3]
821; VI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
822; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
823; VI-NEXT:    s_nop 1
824; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
825; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[2:3]
826; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
827; VI-NEXT:    v_fma_f64 v[2:3], -v[6:7], v[4:5], v[2:3]
828; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
829; VI-NEXT:    s_endpgm
830                      double addrspace(1)* %in2) #0 {
831   %r0 = load double, double addrspace(1)* %in1, align 8
832   %r1 = load double, double addrspace(1)* %in2, align 8
833   %r2 = frem fast double %r0, %r1
834   store double %r2, double addrspace(1)* %out, align 8
835   ret void
836}
837
838define amdgpu_kernel void @unsafe_frem_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
839; SI-LABEL: unsafe_frem_f64:
840; SI:       ; %bb.0:
841; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
842; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
843; SI-NEXT:    s_mov_b32 s15, 0xf000
844; SI-NEXT:    s_mov_b32 s14, -1
845; SI-NEXT:    s_waitcnt lgkmcnt(0)
846; SI-NEXT:    s_mov_b32 s12, s4
847; SI-NEXT:    s_mov_b32 s13, s5
848; SI-NEXT:    s_mov_b32 s0, s6
849; SI-NEXT:    s_mov_b32 s1, s7
850; SI-NEXT:    s_mov_b32 s2, s14
851; SI-NEXT:    s_mov_b32 s3, s15
852; SI-NEXT:    s_mov_b32 s10, s14
853; SI-NEXT:    s_mov_b32 s11, s15
854; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
855; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[8:11], 0
856; SI-NEXT:    s_waitcnt vmcnt(0)
857; SI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
858; SI-NEXT:    v_mul_f64 v[4:5], v[0:1], v[4:5]
859; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
860; SI-NEXT:    v_add_i32_e32 v8, vcc, 0xfffffc01, v6
861; SI-NEXT:    s_mov_b32 s1, 0xfffff
862; SI-NEXT:    s_mov_b32 s0, s14
863; SI-NEXT:    v_lshr_b64 v[6:7], s[0:1], v8
864; SI-NEXT:    v_not_b32_e32 v6, v6
865; SI-NEXT:    v_and_b32_e32 v6, v4, v6
866; SI-NEXT:    v_not_b32_e32 v7, v7
867; SI-NEXT:    v_and_b32_e32 v7, v5, v7
868; SI-NEXT:    v_and_b32_e32 v9, 0x80000000, v5
869; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
870; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
871; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v8
872; SI-NEXT:    v_cndmask_b32_e64 v5, v7, v5, s[0:1]
873; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
874; SI-NEXT:    v_cndmask_b32_e64 v4, v6, v4, s[0:1]
875; SI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
876; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[12:15], 0
877; SI-NEXT:    s_endpgm
878;
879; CI-LABEL: unsafe_frem_f64:
880; CI:       ; %bb.0:
881; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
882; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
883; CI-NEXT:    s_mov_b32 s11, 0xf000
884; CI-NEXT:    s_mov_b32 s10, -1
885; CI-NEXT:    s_mov_b32 s2, s10
886; CI-NEXT:    s_waitcnt lgkmcnt(0)
887; CI-NEXT:    s_mov_b32 s8, s4
888; CI-NEXT:    s_mov_b32 s9, s5
889; CI-NEXT:    s_mov_b32 s4, s6
890; CI-NEXT:    s_mov_b32 s5, s7
891; CI-NEXT:    s_mov_b32 s6, s10
892; CI-NEXT:    s_mov_b32 s7, s11
893; CI-NEXT:    s_mov_b32 s3, s11
894; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
895; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
896; CI-NEXT:    s_waitcnt vmcnt(0)
897; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
898; CI-NEXT:    v_mul_f64 v[4:5], v[0:1], v[4:5]
899; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
900; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
901; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
902; CI-NEXT:    s_endpgm
903;
904; VI-LABEL: unsafe_frem_f64:
905; VI:       ; %bb.0:
906; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
907; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
908; VI-NEXT:    s_waitcnt lgkmcnt(0)
909; VI-NEXT:    v_mov_b32_e32 v2, s6
910; VI-NEXT:    v_mov_b32_e32 v3, s7
911; VI-NEXT:    v_mov_b32_e32 v4, s0
912; VI-NEXT:    v_mov_b32_e32 v5, s1
913; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
914; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
915; VI-NEXT:    v_mov_b32_e32 v0, s4
916; VI-NEXT:    v_mov_b32_e32 v1, s5
917; VI-NEXT:    s_waitcnt vmcnt(0)
918; VI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
919; VI-NEXT:    v_mul_f64 v[6:7], v[2:3], v[6:7]
920; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
921; VI-NEXT:    v_fma_f64 v[2:3], -v[6:7], v[4:5], v[2:3]
922; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
923; VI-NEXT:    s_endpgm
924                             double addrspace(1)* %in2) #1 {
925   %r0 = load double, double addrspace(1)* %in1, align 8
926   %r1 = load double, double addrspace(1)* %in2, align 8
927   %r2 = frem double %r0, %r1
928   store double %r2, double addrspace(1)* %out, align 8
929   ret void
930}
931
932define amdgpu_kernel void @frem_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in1,
933; SI-LABEL: frem_v2f16:
934; SI:       ; %bb.0:
935; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
936; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
937; SI-NEXT:    s_mov_b32 s3, 0xf000
938; SI-NEXT:    s_mov_b32 s2, -1
939; SI-NEXT:    s_waitcnt lgkmcnt(0)
940; SI-NEXT:    s_mov_b32 s0, s4
941; SI-NEXT:    s_mov_b32 s1, s5
942; SI-NEXT:    s_mov_b32 s4, s6
943; SI-NEXT:    s_mov_b32 s5, s7
944; SI-NEXT:    s_mov_b32 s6, s2
945; SI-NEXT:    s_mov_b32 s7, s3
946; SI-NEXT:    s_mov_b32 s10, s2
947; SI-NEXT:    s_mov_b32 s11, s3
948; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
949; SI-NEXT:    s_waitcnt vmcnt(0)
950; SI-NEXT:    v_cvt_f32_f16_e32 v1, v0
951; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
952; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
953; SI-NEXT:    buffer_load_dword v2, off, s[8:11], 0 offset:16
954; SI-NEXT:    s_waitcnt vmcnt(0)
955; SI-NEXT:    v_cvt_f32_f16_e32 v3, v2
956; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
957; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
958; SI-NEXT:    v_div_scale_f32 v4, vcc, v0, v2, v0
959; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v2, v2, v0
960; SI-NEXT:    v_rcp_f32_e32 v6, v5
961; SI-NEXT:    s_mov_b32 s6, 3
962; SI-NEXT:    s_mov_b32 s7, 0
963; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
964; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
965; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
966; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
967; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
968; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
969; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
970; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
971; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
972; SI-NEXT:    v_div_fixup_f32 v4, v4, v2, v0
973; SI-NEXT:    v_trunc_f32_e32 v4, v4
974; SI-NEXT:    v_fma_f32 v0, -v4, v2, v0
975; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
976; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
977; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
978; SI-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
979; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v1
980; SI-NEXT:    v_rcp_f32_e32 v5, v4
981; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
982; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
983; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
984; SI-NEXT:    v_mul_f32_e32 v6, v2, v5
985; SI-NEXT:    v_fma_f32 v7, -v4, v6, v2
986; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
987; SI-NEXT:    v_fma_f32 v2, -v4, v6, v2
988; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
989; SI-NEXT:    v_div_fmas_f32 v2, v2, v5, v6
990; SI-NEXT:    v_div_fixup_f32 v2, v2, v3, v1
991; SI-NEXT:    v_trunc_f32_e32 v2, v2
992; SI-NEXT:    v_fma_f32 v1, -v2, v3, v1
993; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
994; SI-NEXT:    v_or_b32_e32 v0, v1, v0
995; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
996; SI-NEXT:    s_endpgm
997;
998; CI-LABEL: frem_v2f16:
999; CI:       ; %bb.0:
1000; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1001; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1002; CI-NEXT:    s_mov_b32 s3, 0xf000
1003; CI-NEXT:    s_mov_b32 s2, -1
1004; CI-NEXT:    s_mov_b32 s10, s2
1005; CI-NEXT:    s_waitcnt lgkmcnt(0)
1006; CI-NEXT:    s_mov_b32 s0, s4
1007; CI-NEXT:    s_mov_b32 s1, s5
1008; CI-NEXT:    s_mov_b32 s4, s6
1009; CI-NEXT:    s_mov_b32 s5, s7
1010; CI-NEXT:    s_mov_b32 s11, s3
1011; CI-NEXT:    s_mov_b32 s6, s2
1012; CI-NEXT:    s_mov_b32 s7, s3
1013; CI-NEXT:    buffer_load_dword v0, off, s[4:7], 0
1014; CI-NEXT:    buffer_load_dword v2, off, s[8:11], 0 offset:16
1015; CI-NEXT:    s_mov_b32 s6, 3
1016; CI-NEXT:    s_mov_b32 s7, 0
1017; CI-NEXT:    s_waitcnt vmcnt(1)
1018; CI-NEXT:    v_cvt_f32_f16_e32 v1, v0
1019; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1020; CI-NEXT:    s_waitcnt vmcnt(0)
1021; CI-NEXT:    v_cvt_f32_f16_e32 v3, v2
1022; CI-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
1023; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
1024; CI-NEXT:    v_cvt_f32_f16_e32 v2, v2
1025; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v2, v2, v0
1026; CI-NEXT:    v_div_scale_f32 v4, vcc, v0, v2, v0
1027; CI-NEXT:    v_rcp_f32_e32 v6, v5
1028; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1029; CI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
1030; CI-NEXT:    v_fma_f32 v6, v7, v6, v6
1031; CI-NEXT:    v_mul_f32_e32 v7, v4, v6
1032; CI-NEXT:    v_fma_f32 v8, -v5, v7, v4
1033; CI-NEXT:    v_fma_f32 v7, v8, v6, v7
1034; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1035; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1036; CI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
1037; CI-NEXT:    v_div_fixup_f32 v4, v4, v2, v0
1038; CI-NEXT:    v_trunc_f32_e32 v4, v4
1039; CI-NEXT:    v_fma_f32 v0, -v4, v2, v0
1040; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v1
1041; CI-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
1042; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
1043; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
1044; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1045; CI-NEXT:    v_rcp_f32_e32 v5, v4
1046; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1047; CI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
1048; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
1049; CI-NEXT:    v_mul_f32_e32 v6, v2, v5
1050; CI-NEXT:    v_fma_f32 v7, -v4, v6, v2
1051; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
1052; CI-NEXT:    v_fma_f32 v2, -v4, v6, v2
1053; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1054; CI-NEXT:    v_div_fmas_f32 v2, v2, v5, v6
1055; CI-NEXT:    v_div_fixup_f32 v2, v2, v3, v1
1056; CI-NEXT:    v_trunc_f32_e32 v2, v2
1057; CI-NEXT:    v_fma_f32 v1, -v2, v3, v1
1058; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
1059; CI-NEXT:    v_or_b32_e32 v0, v1, v0
1060; CI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1061; CI-NEXT:    s_endpgm
1062;
1063; VI-LABEL: frem_v2f16:
1064; VI:       ; %bb.0:
1065; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1066; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1067; VI-NEXT:    s_waitcnt lgkmcnt(0)
1068; VI-NEXT:    v_mov_b32_e32 v2, s6
1069; VI-NEXT:    s_add_u32 s0, s0, 16
1070; VI-NEXT:    v_mov_b32_e32 v3, s7
1071; VI-NEXT:    s_addc_u32 s1, s1, 0
1072; VI-NEXT:    flat_load_dword v4, v[2:3]
1073; VI-NEXT:    v_mov_b32_e32 v3, s1
1074; VI-NEXT:    v_mov_b32_e32 v2, s0
1075; VI-NEXT:    flat_load_dword v2, v[2:3]
1076; VI-NEXT:    v_mov_b32_e32 v0, s4
1077; VI-NEXT:    v_mov_b32_e32 v1, s5
1078; VI-NEXT:    s_waitcnt vmcnt(1)
1079; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v4
1080; VI-NEXT:    v_cvt_f32_f16_e32 v5, v3
1081; VI-NEXT:    s_waitcnt vmcnt(0)
1082; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
1083; VI-NEXT:    v_cvt_f32_f16_e32 v7, v6
1084; VI-NEXT:    v_rcp_f32_e32 v7, v7
1085; VI-NEXT:    v_mul_f32_e32 v5, v5, v7
1086; VI-NEXT:    v_cvt_f16_f32_e32 v5, v5
1087; VI-NEXT:    v_div_fixup_f16 v5, v5, v6, v3
1088; VI-NEXT:    v_trunc_f16_e32 v5, v5
1089; VI-NEXT:    v_fma_f16 v3, -v5, v6, v3
1090; VI-NEXT:    v_cvt_f32_f16_e32 v6, v2
1091; VI-NEXT:    v_cvt_f32_f16_e32 v5, v4
1092; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
1093; VI-NEXT:    v_rcp_f32_e32 v6, v6
1094; VI-NEXT:    v_mul_f32_e32 v5, v5, v6
1095; VI-NEXT:    v_cvt_f16_f32_e32 v5, v5
1096; VI-NEXT:    v_div_fixup_f16 v5, v5, v2, v4
1097; VI-NEXT:    v_trunc_f16_e32 v5, v5
1098; VI-NEXT:    v_fma_f16 v2, -v5, v2, v4
1099; VI-NEXT:    v_or_b32_e32 v2, v2, v3
1100; VI-NEXT:    flat_store_dword v[0:1], v2
1101; VI-NEXT:    s_endpgm
1102                        <2 x half> addrspace(1)* %in2) #0 {
1103   %gep2 = getelementptr <2 x half>, <2 x half> addrspace(1)* %in2, i32 4
1104   %r0 = load <2 x half>, <2 x half> addrspace(1)* %in1, align 8
1105   %r1 = load <2 x half>, <2 x half> addrspace(1)* %gep2, align 8
1106   %r2 = frem <2 x half> %r0, %r1
1107   store <2 x half> %r2, <2 x half> addrspace(1)* %out, align 8
1108   ret void
1109}
1110
1111define amdgpu_kernel void @frem_v4f16(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %in1,
1112; SI-LABEL: frem_v4f16:
1113; SI:       ; %bb.0:
1114; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1115; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1116; SI-NEXT:    s_mov_b32 s3, 0xf000
1117; SI-NEXT:    s_mov_b32 s2, -1
1118; SI-NEXT:    s_waitcnt lgkmcnt(0)
1119; SI-NEXT:    s_mov_b32 s0, s4
1120; SI-NEXT:    s_mov_b32 s1, s5
1121; SI-NEXT:    s_mov_b32 s4, s6
1122; SI-NEXT:    s_mov_b32 s5, s7
1123; SI-NEXT:    s_mov_b32 s6, s2
1124; SI-NEXT:    s_mov_b32 s7, s3
1125; SI-NEXT:    s_mov_b32 s10, s2
1126; SI-NEXT:    s_mov_b32 s11, s3
1127; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
1128; SI-NEXT:    s_waitcnt vmcnt(0)
1129; SI-NEXT:    v_cvt_f32_f16_e32 v2, v0
1130; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1131; SI-NEXT:    v_cvt_f32_f16_e32 v3, v0
1132; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
1133; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
1134; SI-NEXT:    v_cvt_f32_f16_e32 v5, v0
1135; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0 offset:32
1136; SI-NEXT:    s_waitcnt vmcnt(0)
1137; SI-NEXT:    v_cvt_f32_f16_e32 v6, v0
1138; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1139; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
1140; SI-NEXT:    v_cvt_f32_f16_e32 v7, v1
1141; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
1142; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
1143; SI-NEXT:    v_div_scale_f32 v8, vcc, v5, v1, v5
1144; SI-NEXT:    v_div_scale_f32 v9, s[4:5], v1, v1, v5
1145; SI-NEXT:    v_rcp_f32_e32 v10, v9
1146; SI-NEXT:    s_mov_b32 s6, 3
1147; SI-NEXT:    s_mov_b32 s7, 0
1148; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1149; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
1150; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
1151; SI-NEXT:    v_mul_f32_e32 v11, v8, v10
1152; SI-NEXT:    v_fma_f32 v12, -v9, v11, v8
1153; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
1154; SI-NEXT:    v_fma_f32 v8, -v9, v11, v8
1155; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1156; SI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
1157; SI-NEXT:    v_div_fixup_f32 v8, v8, v1, v5
1158; SI-NEXT:    v_trunc_f32_e32 v8, v8
1159; SI-NEXT:    v_fma_f32 v1, -v8, v1, v5
1160; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
1161; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
1162; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1163; SI-NEXT:    v_div_scale_f32 v5, vcc, v4, v7, v4
1164; SI-NEXT:    v_div_scale_f32 v8, s[4:5], v7, v7, v4
1165; SI-NEXT:    v_rcp_f32_e32 v9, v8
1166; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1167; SI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
1168; SI-NEXT:    v_fma_f32 v9, v10, v9, v9
1169; SI-NEXT:    v_mul_f32_e32 v10, v5, v9
1170; SI-NEXT:    v_fma_f32 v11, -v8, v10, v5
1171; SI-NEXT:    v_fma_f32 v10, v11, v9, v10
1172; SI-NEXT:    v_fma_f32 v5, -v8, v10, v5
1173; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1174; SI-NEXT:    v_div_fmas_f32 v5, v5, v9, v10
1175; SI-NEXT:    v_div_fixup_f32 v5, v5, v7, v4
1176; SI-NEXT:    v_trunc_f32_e32 v5, v5
1177; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1178; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
1179; SI-NEXT:    v_or_b32_e32 v1, v4, v1
1180; SI-NEXT:    v_div_scale_f32 v4, vcc, v3, v0, v3
1181; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v0, v0, v3
1182; SI-NEXT:    v_rcp_f32_e32 v7, v5
1183; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1184; SI-NEXT:    v_fma_f32 v8, -v5, v7, 1.0
1185; SI-NEXT:    v_fma_f32 v7, v8, v7, v7
1186; SI-NEXT:    v_mul_f32_e32 v8, v4, v7
1187; SI-NEXT:    v_fma_f32 v9, -v5, v8, v4
1188; SI-NEXT:    v_fma_f32 v8, v9, v7, v8
1189; SI-NEXT:    v_fma_f32 v4, -v5, v8, v4
1190; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1191; SI-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
1192; SI-NEXT:    v_div_fixup_f32 v4, v4, v0, v3
1193; SI-NEXT:    v_trunc_f32_e32 v4, v4
1194; SI-NEXT:    v_fma_f32 v0, -v4, v0, v3
1195; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
1196; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1197; SI-NEXT:    v_div_scale_f32 v3, vcc, v2, v6, v2
1198; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v6, v6, v2
1199; SI-NEXT:    v_rcp_f32_e32 v5, v4
1200; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1201; SI-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1202; SI-NEXT:    v_fma_f32 v5, v7, v5, v5
1203; SI-NEXT:    v_mul_f32_e32 v7, v3, v5
1204; SI-NEXT:    v_fma_f32 v8, -v4, v7, v3
1205; SI-NEXT:    v_fma_f32 v7, v8, v5, v7
1206; SI-NEXT:    v_fma_f32 v3, -v4, v7, v3
1207; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1208; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v7
1209; SI-NEXT:    v_div_fixup_f32 v3, v3, v6, v2
1210; SI-NEXT:    v_trunc_f32_e32 v3, v3
1211; SI-NEXT:    v_fma_f32 v2, -v3, v6, v2
1212; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
1213; SI-NEXT:    v_or_b32_e32 v0, v2, v0
1214; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1215; SI-NEXT:    s_endpgm
1216;
1217; CI-LABEL: frem_v4f16:
1218; CI:       ; %bb.0:
1219; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1220; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1221; CI-NEXT:    s_mov_b32 s3, 0xf000
1222; CI-NEXT:    s_mov_b32 s2, -1
1223; CI-NEXT:    s_mov_b32 s10, s2
1224; CI-NEXT:    s_waitcnt lgkmcnt(0)
1225; CI-NEXT:    s_mov_b32 s0, s4
1226; CI-NEXT:    s_mov_b32 s1, s5
1227; CI-NEXT:    s_mov_b32 s4, s6
1228; CI-NEXT:    s_mov_b32 s5, s7
1229; CI-NEXT:    s_mov_b32 s6, s2
1230; CI-NEXT:    s_mov_b32 s7, s3
1231; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
1232; CI-NEXT:    s_mov_b32 s11, s3
1233; CI-NEXT:    s_mov_b32 s6, 3
1234; CI-NEXT:    s_mov_b32 s7, 0
1235; CI-NEXT:    s_waitcnt vmcnt(0)
1236; CI-NEXT:    v_cvt_f32_f16_e32 v2, v0
1237; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1238; CI-NEXT:    v_cvt_f32_f16_e32 v3, v0
1239; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
1240; CI-NEXT:    v_cvt_f32_f16_e32 v4, v1
1241; CI-NEXT:    v_cvt_f32_f16_e32 v5, v0
1242; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0 offset:32
1243; CI-NEXT:    s_waitcnt vmcnt(0)
1244; CI-NEXT:    v_cvt_f32_f16_e32 v7, v1
1245; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
1246; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
1247; CI-NEXT:    v_cvt_f32_f16_e32 v6, v0
1248; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
1249; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
1250; CI-NEXT:    v_div_scale_f32 v9, s[4:5], v1, v1, v5
1251; CI-NEXT:    v_div_scale_f32 v8, vcc, v5, v1, v5
1252; CI-NEXT:    v_rcp_f32_e32 v10, v9
1253; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1254; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
1255; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
1256; CI-NEXT:    v_mul_f32_e32 v11, v8, v10
1257; CI-NEXT:    v_fma_f32 v12, -v9, v11, v8
1258; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
1259; CI-NEXT:    v_fma_f32 v8, -v9, v11, v8
1260; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1261; CI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
1262; CI-NEXT:    v_div_fixup_f32 v8, v8, v1, v5
1263; CI-NEXT:    v_trunc_f32_e32 v8, v8
1264; CI-NEXT:    v_fma_f32 v1, -v8, v1, v5
1265; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v7, v7, v4
1266; CI-NEXT:    v_div_scale_f32 v5, vcc, v4, v7, v4
1267; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
1268; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
1269; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
1270; CI-NEXT:    v_rcp_f32_e32 v9, v8
1271; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1272; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
1273; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
1274; CI-NEXT:    v_mul_f32_e32 v10, v5, v9
1275; CI-NEXT:    v_fma_f32 v11, -v8, v10, v5
1276; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
1277; CI-NEXT:    v_fma_f32 v5, -v8, v10, v5
1278; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1279; CI-NEXT:    v_div_fmas_f32 v5, v5, v9, v10
1280; CI-NEXT:    v_div_fixup_f32 v5, v5, v7, v4
1281; CI-NEXT:    v_trunc_f32_e32 v5, v5
1282; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1283; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v0, v0, v3
1284; CI-NEXT:    v_cvt_f16_f32_e32 v4, v4
1285; CI-NEXT:    v_or_b32_e32 v1, v4, v1
1286; CI-NEXT:    v_div_scale_f32 v4, vcc, v3, v0, v3
1287; CI-NEXT:    v_rcp_f32_e32 v7, v5
1288; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1289; CI-NEXT:    v_fma_f32 v8, -v5, v7, 1.0
1290; CI-NEXT:    v_fma_f32 v7, v8, v7, v7
1291; CI-NEXT:    v_mul_f32_e32 v8, v4, v7
1292; CI-NEXT:    v_fma_f32 v9, -v5, v8, v4
1293; CI-NEXT:    v_fma_f32 v8, v9, v7, v8
1294; CI-NEXT:    v_fma_f32 v4, -v5, v8, v4
1295; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1296; CI-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
1297; CI-NEXT:    v_div_fixup_f32 v4, v4, v0, v3
1298; CI-NEXT:    v_trunc_f32_e32 v4, v4
1299; CI-NEXT:    v_fma_f32 v0, -v4, v0, v3
1300; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v6, v6, v2
1301; CI-NEXT:    v_div_scale_f32 v3, vcc, v2, v6, v2
1302; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
1303; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
1304; CI-NEXT:    v_rcp_f32_e32 v5, v4
1305; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1306; CI-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
1307; CI-NEXT:    v_fma_f32 v5, v7, v5, v5
1308; CI-NEXT:    v_mul_f32_e32 v7, v3, v5
1309; CI-NEXT:    v_fma_f32 v8, -v4, v7, v3
1310; CI-NEXT:    v_fma_f32 v7, v8, v5, v7
1311; CI-NEXT:    v_fma_f32 v3, -v4, v7, v3
1312; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1313; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v7
1314; CI-NEXT:    v_div_fixup_f32 v3, v3, v6, v2
1315; CI-NEXT:    v_trunc_f32_e32 v3, v3
1316; CI-NEXT:    v_fma_f32 v2, -v3, v6, v2
1317; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
1318; CI-NEXT:    v_or_b32_e32 v0, v2, v0
1319; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1320; CI-NEXT:    s_endpgm
1321;
1322; VI-LABEL: frem_v4f16:
1323; VI:       ; %bb.0:
1324; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1325; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1326; VI-NEXT:    s_waitcnt lgkmcnt(0)
1327; VI-NEXT:    v_mov_b32_e32 v2, s6
1328; VI-NEXT:    s_add_u32 s0, s0, 32
1329; VI-NEXT:    s_addc_u32 s1, s1, 0
1330; VI-NEXT:    v_mov_b32_e32 v5, s1
1331; VI-NEXT:    v_mov_b32_e32 v4, s0
1332; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
1333; VI-NEXT:    v_mov_b32_e32 v3, s7
1334; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
1335; VI-NEXT:    v_mov_b32_e32 v0, s4
1336; VI-NEXT:    v_mov_b32_e32 v1, s5
1337; VI-NEXT:    s_waitcnt vmcnt(1)
1338; VI-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
1339; VI-NEXT:    v_cvt_f32_f16_e32 v9, v8
1340; VI-NEXT:    s_waitcnt vmcnt(0)
1341; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
1342; VI-NEXT:    v_cvt_f32_f16_e32 v7, v6
1343; VI-NEXT:    v_rcp_f32_e32 v9, v9
1344; VI-NEXT:    v_mul_f32_e32 v7, v7, v9
1345; VI-NEXT:    v_cvt_f16_f32_e32 v7, v7
1346; VI-NEXT:    v_div_fixup_f16 v7, v7, v8, v6
1347; VI-NEXT:    v_trunc_f16_e32 v7, v7
1348; VI-NEXT:    v_fma_f16 v6, -v7, v8, v6
1349; VI-NEXT:    v_cvt_f32_f16_e32 v8, v5
1350; VI-NEXT:    v_cvt_f32_f16_e32 v7, v3
1351; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
1352; VI-NEXT:    v_rcp_f32_e32 v8, v8
1353; VI-NEXT:    v_mul_f32_e32 v7, v7, v8
1354; VI-NEXT:    v_cvt_f16_f32_e32 v7, v7
1355; VI-NEXT:    v_div_fixup_f16 v7, v7, v5, v3
1356; VI-NEXT:    v_trunc_f16_e32 v7, v7
1357; VI-NEXT:    v_fma_f16 v3, -v7, v5, v3
1358; VI-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
1359; VI-NEXT:    v_cvt_f32_f16_e32 v8, v7
1360; VI-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
1361; VI-NEXT:    v_or_b32_e32 v3, v3, v6
1362; VI-NEXT:    v_cvt_f32_f16_e32 v6, v5
1363; VI-NEXT:    v_rcp_f32_e32 v8, v8
1364; VI-NEXT:    v_mul_f32_e32 v6, v6, v8
1365; VI-NEXT:    v_cvt_f16_f32_e32 v6, v6
1366; VI-NEXT:    v_div_fixup_f16 v6, v6, v7, v5
1367; VI-NEXT:    v_trunc_f16_e32 v6, v6
1368; VI-NEXT:    v_fma_f16 v5, -v6, v7, v5
1369; VI-NEXT:    v_cvt_f32_f16_e32 v7, v4
1370; VI-NEXT:    v_cvt_f32_f16_e32 v6, v2
1371; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
1372; VI-NEXT:    v_rcp_f32_e32 v7, v7
1373; VI-NEXT:    v_mul_f32_e32 v6, v6, v7
1374; VI-NEXT:    v_cvt_f16_f32_e32 v6, v6
1375; VI-NEXT:    v_div_fixup_f16 v6, v6, v4, v2
1376; VI-NEXT:    v_trunc_f16_e32 v6, v6
1377; VI-NEXT:    v_fma_f16 v2, -v6, v4, v2
1378; VI-NEXT:    v_or_b32_e32 v2, v2, v5
1379; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
1380; VI-NEXT:    s_endpgm
1381                        <4 x half> addrspace(1)* %in2) #0 {
1382   %gep2 = getelementptr <4 x half>, <4 x half> addrspace(1)* %in2, i32 4
1383   %r0 = load <4 x half>, <4 x half> addrspace(1)* %in1, align 16
1384   %r1 = load <4 x half>, <4 x half> addrspace(1)* %gep2, align 16
1385   %r2 = frem <4 x half> %r0, %r1
1386   store <4 x half> %r2, <4 x half> addrspace(1)* %out, align 16
1387   ret void
1388}
1389
1390define amdgpu_kernel void @frem_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
1391; SI-LABEL: frem_v2f32:
1392; SI:       ; %bb.0:
1393; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1394; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1395; SI-NEXT:    s_mov_b32 s3, 0xf000
1396; SI-NEXT:    s_mov_b32 s2, -1
1397; SI-NEXT:    s_waitcnt lgkmcnt(0)
1398; SI-NEXT:    s_mov_b32 s0, s4
1399; SI-NEXT:    s_mov_b32 s1, s5
1400; SI-NEXT:    s_mov_b32 s4, s6
1401; SI-NEXT:    s_mov_b32 s5, s7
1402; SI-NEXT:    s_mov_b32 s6, s2
1403; SI-NEXT:    s_mov_b32 s7, s3
1404; SI-NEXT:    s_mov_b32 s10, s2
1405; SI-NEXT:    s_mov_b32 s11, s3
1406; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
1407; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[8:11], 0 offset:32
1408; SI-NEXT:    s_waitcnt vmcnt(0)
1409; SI-NEXT:    v_div_scale_f32 v4, vcc, v1, v3, v1
1410; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1411; SI-NEXT:    v_rcp_f32_e32 v6, v5
1412; SI-NEXT:    s_mov_b32 s6, 3
1413; SI-NEXT:    s_mov_b32 s7, 0
1414; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1415; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
1416; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
1417; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
1418; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
1419; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
1420; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1421; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1422; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
1423; SI-NEXT:    v_div_fixup_f32 v4, v4, v3, v1
1424; SI-NEXT:    v_trunc_f32_e32 v4, v4
1425; SI-NEXT:    v_fma_f32 v1, -v4, v3, v1
1426; SI-NEXT:    v_div_scale_f32 v3, vcc, v0, v2, v0
1427; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1428; SI-NEXT:    v_rcp_f32_e32 v5, v4
1429; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1430; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
1431; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
1432; SI-NEXT:    v_mul_f32_e32 v6, v3, v5
1433; SI-NEXT:    v_fma_f32 v7, -v4, v6, v3
1434; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
1435; SI-NEXT:    v_fma_f32 v3, -v4, v6, v3
1436; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1437; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
1438; SI-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
1439; SI-NEXT:    v_trunc_f32_e32 v3, v3
1440; SI-NEXT:    v_fma_f32 v0, -v3, v2, v0
1441; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1442; SI-NEXT:    s_endpgm
1443;
1444; CI-LABEL: frem_v2f32:
1445; CI:       ; %bb.0:
1446; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1447; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1448; CI-NEXT:    s_mov_b32 s3, 0xf000
1449; CI-NEXT:    s_mov_b32 s2, -1
1450; CI-NEXT:    s_mov_b32 s10, s2
1451; CI-NEXT:    s_waitcnt lgkmcnt(0)
1452; CI-NEXT:    s_mov_b32 s0, s4
1453; CI-NEXT:    s_mov_b32 s1, s5
1454; CI-NEXT:    s_mov_b32 s4, s6
1455; CI-NEXT:    s_mov_b32 s5, s7
1456; CI-NEXT:    s_mov_b32 s6, s2
1457; CI-NEXT:    s_mov_b32 s7, s3
1458; CI-NEXT:    s_mov_b32 s11, s3
1459; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
1460; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[8:11], 0 offset:32
1461; CI-NEXT:    s_mov_b32 s6, 3
1462; CI-NEXT:    s_mov_b32 s7, 0
1463; CI-NEXT:    s_waitcnt vmcnt(0)
1464; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
1465; CI-NEXT:    v_div_scale_f32 v4, vcc, v1, v3, v1
1466; CI-NEXT:    v_rcp_f32_e32 v6, v5
1467; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1468; CI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
1469; CI-NEXT:    v_fma_f32 v6, v7, v6, v6
1470; CI-NEXT:    v_mul_f32_e32 v7, v4, v6
1471; CI-NEXT:    v_fma_f32 v8, -v5, v7, v4
1472; CI-NEXT:    v_fma_f32 v7, v8, v6, v7
1473; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
1474; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1475; CI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
1476; CI-NEXT:    v_div_fixup_f32 v4, v4, v3, v1
1477; CI-NEXT:    v_trunc_f32_e32 v4, v4
1478; CI-NEXT:    v_fma_f32 v1, -v4, v3, v1
1479; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
1480; CI-NEXT:    v_div_scale_f32 v3, vcc, v0, v2, v0
1481; CI-NEXT:    v_rcp_f32_e32 v5, v4
1482; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1483; CI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
1484; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
1485; CI-NEXT:    v_mul_f32_e32 v6, v3, v5
1486; CI-NEXT:    v_fma_f32 v7, -v4, v6, v3
1487; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
1488; CI-NEXT:    v_fma_f32 v3, -v4, v6, v3
1489; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1490; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
1491; CI-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
1492; CI-NEXT:    v_trunc_f32_e32 v3, v3
1493; CI-NEXT:    v_fma_f32 v0, -v3, v2, v0
1494; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1495; CI-NEXT:    s_endpgm
1496;
1497; VI-LABEL: frem_v2f32:
1498; VI:       ; %bb.0:
1499; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1500; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1501; VI-NEXT:    s_mov_b32 s2, 3
1502; VI-NEXT:    s_mov_b32 s3, 0
1503; VI-NEXT:    s_waitcnt lgkmcnt(0)
1504; VI-NEXT:    v_mov_b32_e32 v2, s6
1505; VI-NEXT:    s_add_u32 s0, s0, 32
1506; VI-NEXT:    s_addc_u32 s1, s1, 0
1507; VI-NEXT:    v_mov_b32_e32 v5, s1
1508; VI-NEXT:    v_mov_b32_e32 v3, s7
1509; VI-NEXT:    v_mov_b32_e32 v4, s0
1510; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
1511; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
1512; VI-NEXT:    v_mov_b32_e32 v0, s4
1513; VI-NEXT:    v_mov_b32_e32 v1, s5
1514; VI-NEXT:    s_waitcnt vmcnt(0)
1515; VI-NEXT:    v_div_scale_f32 v7, s[0:1], v5, v5, v3
1516; VI-NEXT:    v_div_scale_f32 v6, vcc, v3, v5, v3
1517; VI-NEXT:    v_rcp_f32_e32 v8, v7
1518; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1519; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
1520; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
1521; VI-NEXT:    v_mul_f32_e32 v9, v6, v8
1522; VI-NEXT:    v_fma_f32 v10, -v7, v9, v6
1523; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
1524; VI-NEXT:    v_fma_f32 v6, -v7, v9, v6
1525; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1526; VI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
1527; VI-NEXT:    v_div_fixup_f32 v6, v6, v5, v3
1528; VI-NEXT:    v_trunc_f32_e32 v6, v6
1529; VI-NEXT:    v_fma_f32 v3, -v6, v5, v3
1530; VI-NEXT:    v_div_scale_f32 v6, s[0:1], v4, v4, v2
1531; VI-NEXT:    v_div_scale_f32 v5, vcc, v2, v4, v2
1532; VI-NEXT:    v_rcp_f32_e32 v7, v6
1533; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1534; VI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
1535; VI-NEXT:    v_fma_f32 v7, v8, v7, v7
1536; VI-NEXT:    v_mul_f32_e32 v8, v5, v7
1537; VI-NEXT:    v_fma_f32 v9, -v6, v8, v5
1538; VI-NEXT:    v_fma_f32 v8, v9, v7, v8
1539; VI-NEXT:    v_fma_f32 v5, -v6, v8, v5
1540; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1541; VI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
1542; VI-NEXT:    v_div_fixup_f32 v5, v5, v4, v2
1543; VI-NEXT:    v_trunc_f32_e32 v5, v5
1544; VI-NEXT:    v_fma_f32 v2, -v5, v4, v2
1545; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
1546; VI-NEXT:    s_endpgm
1547                        <2 x float> addrspace(1)* %in2) #0 {
1548   %gep2 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in2, i32 4
1549   %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1, align 8
1550   %r1 = load <2 x float>, <2 x float> addrspace(1)* %gep2, align 8
1551   %r2 = frem <2 x float> %r0, %r1
1552   store <2 x float> %r2, <2 x float> addrspace(1)* %out, align 8
1553   ret void
1554}
1555
1556define amdgpu_kernel void @frem_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
1557; SI-LABEL: frem_v4f32:
1558; SI:       ; %bb.0:
1559; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1560; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1561; SI-NEXT:    s_mov_b32 s3, 0xf000
1562; SI-NEXT:    s_mov_b32 s2, -1
1563; SI-NEXT:    s_waitcnt lgkmcnt(0)
1564; SI-NEXT:    s_mov_b32 s0, s4
1565; SI-NEXT:    s_mov_b32 s1, s5
1566; SI-NEXT:    s_mov_b32 s4, s6
1567; SI-NEXT:    s_mov_b32 s5, s7
1568; SI-NEXT:    s_mov_b32 s6, s2
1569; SI-NEXT:    s_mov_b32 s7, s3
1570; SI-NEXT:    s_mov_b32 s10, s2
1571; SI-NEXT:    s_mov_b32 s11, s3
1572; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
1573; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:64
1574; SI-NEXT:    s_waitcnt vmcnt(0)
1575; SI-NEXT:    v_div_scale_f32 v8, vcc, v3, v7, v3
1576; SI-NEXT:    v_div_scale_f32 v9, s[4:5], v7, v7, v3
1577; SI-NEXT:    v_rcp_f32_e32 v10, v9
1578; SI-NEXT:    s_mov_b32 s6, 3
1579; SI-NEXT:    s_mov_b32 s7, 0
1580; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1581; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
1582; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
1583; SI-NEXT:    v_mul_f32_e32 v11, v8, v10
1584; SI-NEXT:    v_fma_f32 v12, -v9, v11, v8
1585; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
1586; SI-NEXT:    v_fma_f32 v8, -v9, v11, v8
1587; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1588; SI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
1589; SI-NEXT:    v_div_fixup_f32 v8, v8, v7, v3
1590; SI-NEXT:    v_trunc_f32_e32 v8, v8
1591; SI-NEXT:    v_fma_f32 v3, -v8, v7, v3
1592; SI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
1593; SI-NEXT:    v_div_scale_f32 v8, s[4:5], v6, v6, v2
1594; SI-NEXT:    v_rcp_f32_e32 v9, v8
1595; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1596; SI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
1597; SI-NEXT:    v_fma_f32 v9, v10, v9, v9
1598; SI-NEXT:    v_mul_f32_e32 v10, v7, v9
1599; SI-NEXT:    v_fma_f32 v11, -v8, v10, v7
1600; SI-NEXT:    v_fma_f32 v10, v11, v9, v10
1601; SI-NEXT:    v_fma_f32 v7, -v8, v10, v7
1602; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1603; SI-NEXT:    v_div_fmas_f32 v7, v7, v9, v10
1604; SI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
1605; SI-NEXT:    v_trunc_f32_e32 v7, v7
1606; SI-NEXT:    v_fma_f32 v2, -v7, v6, v2
1607; SI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
1608; SI-NEXT:    v_div_scale_f32 v7, s[4:5], v5, v5, v1
1609; SI-NEXT:    v_rcp_f32_e32 v8, v7
1610; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1611; SI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
1612; SI-NEXT:    v_fma_f32 v8, v9, v8, v8
1613; SI-NEXT:    v_mul_f32_e32 v9, v6, v8
1614; SI-NEXT:    v_fma_f32 v10, -v7, v9, v6
1615; SI-NEXT:    v_fma_f32 v9, v10, v8, v9
1616; SI-NEXT:    v_fma_f32 v6, -v7, v9, v6
1617; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1618; SI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
1619; SI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
1620; SI-NEXT:    v_trunc_f32_e32 v6, v6
1621; SI-NEXT:    v_fma_f32 v1, -v6, v5, v1
1622; SI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
1623; SI-NEXT:    v_div_scale_f32 v6, s[4:5], v4, v4, v0
1624; SI-NEXT:    v_rcp_f32_e32 v7, v6
1625; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1626; SI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
1627; SI-NEXT:    v_fma_f32 v7, v8, v7, v7
1628; SI-NEXT:    v_mul_f32_e32 v8, v5, v7
1629; SI-NEXT:    v_fma_f32 v9, -v6, v8, v5
1630; SI-NEXT:    v_fma_f32 v8, v9, v7, v8
1631; SI-NEXT:    v_fma_f32 v5, -v6, v8, v5
1632; SI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1633; SI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
1634; SI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
1635; SI-NEXT:    v_trunc_f32_e32 v5, v5
1636; SI-NEXT:    v_fma_f32 v0, -v5, v4, v0
1637; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1638; SI-NEXT:    s_endpgm
1639;
1640; CI-LABEL: frem_v4f32:
1641; CI:       ; %bb.0:
1642; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1643; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1644; CI-NEXT:    s_mov_b32 s3, 0xf000
1645; CI-NEXT:    s_mov_b32 s2, -1
1646; CI-NEXT:    s_mov_b32 s10, s2
1647; CI-NEXT:    s_waitcnt lgkmcnt(0)
1648; CI-NEXT:    s_mov_b32 s0, s4
1649; CI-NEXT:    s_mov_b32 s1, s5
1650; CI-NEXT:    s_mov_b32 s4, s6
1651; CI-NEXT:    s_mov_b32 s5, s7
1652; CI-NEXT:    s_mov_b32 s6, s2
1653; CI-NEXT:    s_mov_b32 s7, s3
1654; CI-NEXT:    s_mov_b32 s11, s3
1655; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
1656; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:64
1657; CI-NEXT:    s_mov_b32 s6, 3
1658; CI-NEXT:    s_mov_b32 s7, 0
1659; CI-NEXT:    s_waitcnt vmcnt(0)
1660; CI-NEXT:    v_div_scale_f32 v9, s[4:5], v7, v7, v3
1661; CI-NEXT:    v_div_scale_f32 v8, vcc, v3, v7, v3
1662; CI-NEXT:    v_rcp_f32_e32 v10, v9
1663; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1664; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
1665; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
1666; CI-NEXT:    v_mul_f32_e32 v11, v8, v10
1667; CI-NEXT:    v_fma_f32 v12, -v9, v11, v8
1668; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
1669; CI-NEXT:    v_fma_f32 v8, -v9, v11, v8
1670; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1671; CI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
1672; CI-NEXT:    v_div_fixup_f32 v8, v8, v7, v3
1673; CI-NEXT:    v_trunc_f32_e32 v8, v8
1674; CI-NEXT:    v_fma_f32 v3, -v8, v7, v3
1675; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v6, v6, v2
1676; CI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
1677; CI-NEXT:    v_rcp_f32_e32 v9, v8
1678; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1679; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
1680; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
1681; CI-NEXT:    v_mul_f32_e32 v10, v7, v9
1682; CI-NEXT:    v_fma_f32 v11, -v8, v10, v7
1683; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
1684; CI-NEXT:    v_fma_f32 v7, -v8, v10, v7
1685; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1686; CI-NEXT:    v_div_fmas_f32 v7, v7, v9, v10
1687; CI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
1688; CI-NEXT:    v_trunc_f32_e32 v7, v7
1689; CI-NEXT:    v_fma_f32 v2, -v7, v6, v2
1690; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v5, v5, v1
1691; CI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
1692; CI-NEXT:    v_rcp_f32_e32 v8, v7
1693; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1694; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
1695; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
1696; CI-NEXT:    v_mul_f32_e32 v9, v6, v8
1697; CI-NEXT:    v_fma_f32 v10, -v7, v9, v6
1698; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
1699; CI-NEXT:    v_fma_f32 v6, -v7, v9, v6
1700; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1701; CI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
1702; CI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
1703; CI-NEXT:    v_trunc_f32_e32 v6, v6
1704; CI-NEXT:    v_fma_f32 v1, -v6, v5, v1
1705; CI-NEXT:    v_div_scale_f32 v6, s[4:5], v4, v4, v0
1706; CI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
1707; CI-NEXT:    v_rcp_f32_e32 v7, v6
1708; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s6
1709; CI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
1710; CI-NEXT:    v_fma_f32 v7, v8, v7, v7
1711; CI-NEXT:    v_mul_f32_e32 v8, v5, v7
1712; CI-NEXT:    v_fma_f32 v9, -v6, v8, v5
1713; CI-NEXT:    v_fma_f32 v8, v9, v7, v8
1714; CI-NEXT:    v_fma_f32 v5, -v6, v8, v5
1715; CI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s7
1716; CI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
1717; CI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
1718; CI-NEXT:    v_trunc_f32_e32 v5, v5
1719; CI-NEXT:    v_fma_f32 v0, -v5, v4, v0
1720; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1721; CI-NEXT:    s_endpgm
1722;
1723; VI-LABEL: frem_v4f32:
1724; VI:       ; %bb.0:
1725; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1726; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1727; VI-NEXT:    s_mov_b32 s2, 3
1728; VI-NEXT:    s_mov_b32 s3, 0
1729; VI-NEXT:    s_waitcnt lgkmcnt(0)
1730; VI-NEXT:    v_mov_b32_e32 v0, s6
1731; VI-NEXT:    s_add_u32 s0, s0, 64
1732; VI-NEXT:    s_addc_u32 s1, s1, 0
1733; VI-NEXT:    v_mov_b32_e32 v5, s1
1734; VI-NEXT:    v_mov_b32_e32 v1, s7
1735; VI-NEXT:    v_mov_b32_e32 v4, s0
1736; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
1737; VI-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]
1738; VI-NEXT:    v_mov_b32_e32 v8, s4
1739; VI-NEXT:    v_mov_b32_e32 v9, s5
1740; VI-NEXT:    s_waitcnt vmcnt(0)
1741; VI-NEXT:    v_div_scale_f32 v11, s[0:1], v7, v7, v3
1742; VI-NEXT:    v_div_scale_f32 v10, vcc, v3, v7, v3
1743; VI-NEXT:    v_rcp_f32_e32 v12, v11
1744; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1745; VI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
1746; VI-NEXT:    v_fma_f32 v12, v13, v12, v12
1747; VI-NEXT:    v_mul_f32_e32 v13, v10, v12
1748; VI-NEXT:    v_fma_f32 v14, -v11, v13, v10
1749; VI-NEXT:    v_fma_f32 v13, v14, v12, v13
1750; VI-NEXT:    v_fma_f32 v10, -v11, v13, v10
1751; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1752; VI-NEXT:    v_div_fmas_f32 v10, v10, v12, v13
1753; VI-NEXT:    v_div_fixup_f32 v10, v10, v7, v3
1754; VI-NEXT:    v_trunc_f32_e32 v10, v10
1755; VI-NEXT:    v_fma_f32 v3, -v10, v7, v3
1756; VI-NEXT:    v_div_scale_f32 v10, s[0:1], v6, v6, v2
1757; VI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
1758; VI-NEXT:    v_rcp_f32_e32 v11, v10
1759; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1760; VI-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
1761; VI-NEXT:    v_fma_f32 v11, v12, v11, v11
1762; VI-NEXT:    v_mul_f32_e32 v12, v7, v11
1763; VI-NEXT:    v_fma_f32 v13, -v10, v12, v7
1764; VI-NEXT:    v_fma_f32 v12, v13, v11, v12
1765; VI-NEXT:    v_fma_f32 v7, -v10, v12, v7
1766; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1767; VI-NEXT:    v_div_fmas_f32 v7, v7, v11, v12
1768; VI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
1769; VI-NEXT:    v_trunc_f32_e32 v7, v7
1770; VI-NEXT:    v_fma_f32 v2, -v7, v6, v2
1771; VI-NEXT:    v_div_scale_f32 v7, s[0:1], v5, v5, v1
1772; VI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
1773; VI-NEXT:    v_rcp_f32_e32 v10, v7
1774; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1775; VI-NEXT:    v_fma_f32 v11, -v7, v10, 1.0
1776; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
1777; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
1778; VI-NEXT:    v_fma_f32 v12, -v7, v11, v6
1779; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
1780; VI-NEXT:    v_fma_f32 v6, -v7, v11, v6
1781; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1782; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
1783; VI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
1784; VI-NEXT:    v_trunc_f32_e32 v6, v6
1785; VI-NEXT:    v_fma_f32 v1, -v6, v5, v1
1786; VI-NEXT:    v_div_scale_f32 v6, s[0:1], v4, v4, v0
1787; VI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
1788; VI-NEXT:    v_rcp_f32_e32 v7, v6
1789; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s2
1790; VI-NEXT:    v_fma_f32 v10, -v6, v7, 1.0
1791; VI-NEXT:    v_fma_f32 v7, v10, v7, v7
1792; VI-NEXT:    v_mul_f32_e32 v10, v5, v7
1793; VI-NEXT:    v_fma_f32 v11, -v6, v10, v5
1794; VI-NEXT:    v_fma_f32 v10, v11, v7, v10
1795; VI-NEXT:    v_fma_f32 v5, -v6, v10, v5
1796; VI-NEXT:    s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s3
1797; VI-NEXT:    v_div_fmas_f32 v5, v5, v7, v10
1798; VI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
1799; VI-NEXT:    v_trunc_f32_e32 v5, v5
1800; VI-NEXT:    v_fma_f32 v0, -v5, v4, v0
1801; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
1802; VI-NEXT:    s_endpgm
1803                        <4 x float> addrspace(1)* %in2) #0 {
1804   %gep2 = getelementptr <4 x float>, <4 x float> addrspace(1)* %in2, i32 4
1805   %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1, align 16
1806   %r1 = load <4 x float>, <4 x float> addrspace(1)* %gep2, align 16
1807   %r2 = frem <4 x float> %r0, %r1
1808   store <4 x float> %r2, <4 x float> addrspace(1)* %out, align 16
1809   ret void
1810}
1811
1812define amdgpu_kernel void @frem_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
1813; SI-LABEL: frem_v2f64:
1814; SI:       ; %bb.0:
1815; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
1816; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
1817; SI-NEXT:    s_mov_b32 s7, 0xf000
1818; SI-NEXT:    s_mov_b32 s6, -1
1819; SI-NEXT:    s_waitcnt lgkmcnt(0)
1820; SI-NEXT:    s_mov_b32 s4, s8
1821; SI-NEXT:    s_mov_b32 s5, s9
1822; SI-NEXT:    s_mov_b32 s0, s10
1823; SI-NEXT:    s_mov_b32 s1, s11
1824; SI-NEXT:    s_mov_b32 s2, s6
1825; SI-NEXT:    s_mov_b32 s3, s7
1826; SI-NEXT:    s_mov_b32 s14, s6
1827; SI-NEXT:    s_mov_b32 s15, s7
1828; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
1829; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[12:15], 0 offset:64
1830; SI-NEXT:    s_waitcnt vmcnt(0)
1831; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[6:7], v[6:7], v[2:3]
1832; SI-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
1833; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
1834; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1835; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
1836; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1837; SI-NEXT:    v_div_scale_f64 v[12:13], s[0:1], v[2:3], v[6:7], v[2:3]
1838; SI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
1839; SI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], v[12:13]
1840; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v9
1841; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v3, v13
1842; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
1843; SI-NEXT:    s_nop 1
1844; SI-NEXT:    v_div_fmas_f64 v[8:9], v[16:17], v[10:11], v[14:15]
1845; SI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
1846; SI-NEXT:    v_bfe_u32 v10, v9, 20, 11
1847; SI-NEXT:    s_movk_i32 s8, 0xfc01
1848; SI-NEXT:    v_add_i32_e32 v12, vcc, s8, v10
1849; SI-NEXT:    s_mov_b32 s3, 0xfffff
1850; SI-NEXT:    v_lshr_b64 v[10:11], s[2:3], v12
1851; SI-NEXT:    v_not_b32_e32 v10, v10
1852; SI-NEXT:    v_and_b32_e32 v10, v8, v10
1853; SI-NEXT:    v_not_b32_e32 v11, v11
1854; SI-NEXT:    v_and_b32_e32 v11, v9, v11
1855; SI-NEXT:    s_brev_b32 s9, 1
1856; SI-NEXT:    v_and_b32_e32 v13, s9, v9
1857; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v12
1858; SI-NEXT:    v_cndmask_b32_e32 v11, v11, v13, vcc
1859; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v12
1860; SI-NEXT:    v_cndmask_b32_e64 v9, v11, v9, s[0:1]
1861; SI-NEXT:    v_cndmask_b32_e64 v10, v10, 0, vcc
1862; SI-NEXT:    v_cndmask_b32_e64 v8, v10, v8, s[0:1]
1863; SI-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
1864; SI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[0:1]
1865; SI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
1866; SI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
1867; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
1868; SI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
1869; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
1870; SI-NEXT:    v_div_scale_f64 v[10:11], s[0:1], v[0:1], v[4:5], v[0:1]
1871; SI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
1872; SI-NEXT:    v_fma_f64 v[14:15], -v[6:7], v[12:13], v[10:11]
1873; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v7
1874; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v11
1875; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
1876; SI-NEXT:    s_nop 1
1877; SI-NEXT:    v_div_fmas_f64 v[6:7], v[14:15], v[8:9], v[12:13]
1878; SI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
1879; SI-NEXT:    v_bfe_u32 v8, v7, 20, 11
1880; SI-NEXT:    v_add_i32_e32 v10, vcc, s8, v8
1881; SI-NEXT:    v_lshr_b64 v[8:9], s[2:3], v10
1882; SI-NEXT:    v_not_b32_e32 v8, v8
1883; SI-NEXT:    v_and_b32_e32 v8, v6, v8
1884; SI-NEXT:    v_not_b32_e32 v9, v9
1885; SI-NEXT:    v_and_b32_e32 v9, v7, v9
1886; SI-NEXT:    v_and_b32_e32 v11, s9, v7
1887; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v10
1888; SI-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
1889; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], 51, v10
1890; SI-NEXT:    v_cndmask_b32_e64 v7, v9, v7, s[0:1]
1891; SI-NEXT:    v_cndmask_b32_e64 v8, v8, 0, vcc
1892; SI-NEXT:    v_cndmask_b32_e64 v6, v8, v6, s[0:1]
1893; SI-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
1894; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
1895; SI-NEXT:    s_endpgm
1896;
1897; CI-LABEL: frem_v2f64:
1898; CI:       ; %bb.0:
1899; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1900; CI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
1901; CI-NEXT:    s_mov_b32 s3, 0xf000
1902; CI-NEXT:    s_mov_b32 s2, -1
1903; CI-NEXT:    s_mov_b32 s10, s2
1904; CI-NEXT:    s_waitcnt lgkmcnt(0)
1905; CI-NEXT:    s_mov_b32 s0, s4
1906; CI-NEXT:    s_mov_b32 s1, s5
1907; CI-NEXT:    s_mov_b32 s4, s6
1908; CI-NEXT:    s_mov_b32 s5, s7
1909; CI-NEXT:    s_mov_b32 s6, s2
1910; CI-NEXT:    s_mov_b32 s7, s3
1911; CI-NEXT:    s_mov_b32 s11, s3
1912; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
1913; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:64
1914; CI-NEXT:    s_waitcnt vmcnt(0)
1915; CI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[6:7], v[6:7], v[2:3]
1916; CI-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
1917; CI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
1918; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1919; CI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
1920; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1921; CI-NEXT:    v_div_scale_f64 v[12:13], vcc, v[2:3], v[6:7], v[2:3]
1922; CI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
1923; CI-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
1924; CI-NEXT:    s_nop 1
1925; CI-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
1926; CI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
1927; CI-NEXT:    v_trunc_f64_e32 v[8:9], v[8:9]
1928; CI-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
1929; CI-NEXT:    v_div_scale_f64 v[6:7], s[4:5], v[4:5], v[4:5], v[0:1]
1930; CI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
1931; CI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
1932; CI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
1933; CI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
1934; CI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
1935; CI-NEXT:    v_div_scale_f64 v[10:11], vcc, v[0:1], v[4:5], v[0:1]
1936; CI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
1937; CI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
1938; CI-NEXT:    s_nop 1
1939; CI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
1940; CI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
1941; CI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
1942; CI-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
1943; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
1944; CI-NEXT:    s_endpgm
1945;
1946; VI-LABEL: frem_v2f64:
1947; VI:       ; %bb.0:
1948; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
1949; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
1950; VI-NEXT:    s_waitcnt lgkmcnt(0)
1951; VI-NEXT:    v_mov_b32_e32 v0, s6
1952; VI-NEXT:    s_add_u32 s0, s0, 64
1953; VI-NEXT:    s_addc_u32 s1, s1, 0
1954; VI-NEXT:    v_mov_b32_e32 v5, s1
1955; VI-NEXT:    v_mov_b32_e32 v1, s7
1956; VI-NEXT:    v_mov_b32_e32 v4, s0
1957; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
1958; VI-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]
1959; VI-NEXT:    v_mov_b32_e32 v8, s4
1960; VI-NEXT:    v_mov_b32_e32 v9, s5
1961; VI-NEXT:    s_waitcnt vmcnt(0)
1962; VI-NEXT:    v_div_scale_f64 v[10:11], s[0:1], v[6:7], v[6:7], v[2:3]
1963; VI-NEXT:    v_rcp_f64_e32 v[12:13], v[10:11]
1964; VI-NEXT:    v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
1965; VI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
1966; VI-NEXT:    v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
1967; VI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
1968; VI-NEXT:    v_div_scale_f64 v[14:15], vcc, v[2:3], v[6:7], v[2:3]
1969; VI-NEXT:    v_mul_f64 v[16:17], v[14:15], v[12:13]
1970; VI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
1971; VI-NEXT:    s_nop 1
1972; VI-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
1973; VI-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[6:7], v[2:3]
1974; VI-NEXT:    v_trunc_f64_e32 v[10:11], v[10:11]
1975; VI-NEXT:    v_fma_f64 v[2:3], -v[10:11], v[6:7], v[2:3]
1976; VI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[0:1]
1977; VI-NEXT:    v_rcp_f64_e32 v[10:11], v[6:7]
1978; VI-NEXT:    v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
1979; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1980; VI-NEXT:    v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
1981; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
1982; VI-NEXT:    v_div_scale_f64 v[12:13], vcc, v[0:1], v[4:5], v[0:1]
1983; VI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
1984; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[14:15], v[12:13]
1985; VI-NEXT:    s_nop 1
1986; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[14:15]
1987; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
1988; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
1989; VI-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
1990; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
1991; VI-NEXT:    s_endpgm
1992                        <2 x double> addrspace(1)* %in2) #0 {
1993   %gep2 = getelementptr <2 x double>, <2 x double> addrspace(1)* %in2, i32 4
1994   %r0 = load <2 x double>, <2 x double> addrspace(1)* %in1, align 16
1995   %r1 = load <2 x double>, <2 x double> addrspace(1)* %gep2, align 16
1996   %r2 = frem <2 x double> %r0, %r1
1997   store <2 x double> %r2, <2 x double> addrspace(1)* %out, align 16
1998   ret void
1999}
2000
2001attributes #0 = { nounwind "unsafe-fp-math"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
2002attributes #1 = { nounwind "unsafe-fp-math"="true" "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
2003