1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
4
5declare double @llvm.fabs.f64(double) #0
6declare double @llvm.floor.f64(double) #0
7
8; FUNC-LABEL: {{^}}fract_f64:
9; GCN-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
10; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
11; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
12; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
13; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
14; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
15; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
16; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
17; CI: buffer_store_dwordx2 [[FRC]]
18define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) #1 {
19  %x = load double, double addrspace(1)* %src
20  %floor.x = call double @llvm.floor.f64(double %x)
21  %fract = fsub double %x, %floor.x
22  store double %fract, double addrspace(1)* %out
23  ret void
24}
25
26; FUNC-LABEL: {{^}}fract_f64_neg:
27; GCN-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
28; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
29; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
30; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
31; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
32; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
33; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
34; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
35; CI: buffer_store_dwordx2 [[FRC]]
36define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) #1 {
37  %x = load double, double addrspace(1)* %src
38  %neg.x = fsub double -0.0, %x
39  %floor.neg.x = call double @llvm.floor.f64(double %neg.x)
40  %fract = fsub double %neg.x, %floor.neg.x
41  store double %fract, double addrspace(1)* %out
42  ret void
43}
44
45; FUNC-LABEL: {{^}}fract_f64_neg_abs:
46; GCN-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
47; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
48; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
49; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
50; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
51; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
52; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
53; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
54; CI: buffer_store_dwordx2 [[FRC]]
55define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) #1 {
56  %x = load double, double addrspace(1)* %src
57  %abs.x = call double @llvm.fabs.f64(double %x)
58  %neg.abs.x = fsub double -0.0, %abs.x
59  %floor.neg.abs.x = call double @llvm.floor.f64(double %neg.abs.x)
60  %fract = fsub double %neg.abs.x, %floor.neg.abs.x
61  store double %fract, double addrspace(1)* %out
62  ret void
63}
64
65attributes #0 = { nounwind readnone }
66attributes #1 = { nounwind }
67