1; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI %s 2; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI %s 3; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global,+fp64-fp16-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX9-DENORM %s 4; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX9-FLUSH %s 5 6; GCN-LABEL: {{^}}fptrunc_f32_to_f16: 7; GCN: buffer_load_dword v[[A_F32:[0-9]+]] 8; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]] 9; GCN: buffer_store_short v[[R_F16]] 10; GCN: s_endpgm 11define void @fptrunc_f32_to_f16( 12 half addrspace(1)* %r, 13 float addrspace(1)* %a) { 14entry: 15 %a.val = load float, float addrspace(1)* %a 16 %r.val = fptrunc float %a.val to half 17 store half %r.val, half addrspace(1)* %r 18 ret void 19} 20 21; GCN-LABEL: {{^}}fptrunc_f64_to_f16: 22; GCN: buffer_load_dwordx2 v{{\[}}[[A_F64_0:[0-9]+]]:[[A_F64_1:[0-9]+]]{{\]}} 23; GCN: v_cvt_f32_f64_e32 v[[A_F32:[0-9]+]], v{{\[}}[[A_F64_0]]:[[A_F64_1]]{{\]}} 24; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]] 25; GCN: buffer_store_short v[[R_F16]] 26; GCN: s_endpgm 27define void @fptrunc_f64_to_f16( 28 half addrspace(1)* %r, 29 double addrspace(1)* %a) { 30entry: 31 %a.val = load double, double addrspace(1)* %a 32 %r.val = fptrunc double %a.val to half 33 store half %r.val, half addrspace(1)* %r 34 ret void 35} 36 37; GCN-LABEL: {{^}}fptrunc_v2f32_to_v2f16: 38; GCN: buffer_load_dwordx2 v{{\[}}[[A_F32_0:[0-9]+]]:[[A_F32_1:[0-9]+]]{{\]}} 39; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[A_F32_0]] 40; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[A_F32_1]] 41; SIVI-DAG: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], 0xffff, v[[R_F16_0]] 42; SIVI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 43; SIVI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_LO]] 44 45; GFX9-FLUSH: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], 0xffff, v[[R_F16_0]] 46; GFX9-FLUSH: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], 16, v[[R_F16_LO]] 47 48; GFX9-DENORM: v_pack_b32_f16 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] 49 50; GCN: buffer_store_dword v[[R_V2_F16]] 51; GCN: s_endpgm 52define void @fptrunc_v2f32_to_v2f16( 53 <2 x half> addrspace(1)* %r, 54 <2 x float> addrspace(1)* %a) { 55entry: 56 %a.val = load <2 x float>, <2 x float> addrspace(1)* %a 57 %r.val = fptrunc <2 x float> %a.val to <2 x half> 58 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 59 ret void 60} 61 62; GCN-LABEL: {{^}}fptrunc_v2f64_to_v2f16: 63; GCN: buffer_load_dwordx4 v{{\[}}[[A_F64_0:[0-9]+]]:[[A_F64_3:[0-9]+]]{{\]}} 64; GCN: v_cvt_f32_f64_e32 v[[A_F32_0:[0-9]+]], v{{\[}}[[A_F64_0]]:{{[0-9]+}}{{\]}} 65; GCN: v_cvt_f32_f64_e32 v[[A_F32_1:[0-9]+]], v{{\[}}{{[0-9]+}}:[[A_F64_3]]{{\]}} 66; GCN: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[A_F32_0]] 67; GCN: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[A_F32_1]] 68 69; SIVI: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], 0xffff, v[[R_F16_0]] 70; SIVI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] 71; SIVI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_LO]] 72 73; GFX9-FLUSH: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], 0xffff, v[[R_F16_0]] 74; GFX9-FLUSH: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], 16, v[[R_F16_LO]] 75 76; GFX9-DENORM: v_pack_b32_f16 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] 77 78; GCN: buffer_store_dword v[[R_V2_F16]] 79define void @fptrunc_v2f64_to_v2f16( 80 <2 x half> addrspace(1)* %r, 81 <2 x double> addrspace(1)* %a) { 82entry: 83 %a.val = load <2 x double>, <2 x double> addrspace(1)* %a 84 %r.val = fptrunc <2 x double> %a.val to <2 x half> 85 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 86 ret void 87} 88 89; GCN-LABEL: {{^}}fneg_fptrunc_f32_to_f16: 90; GCN: buffer_load_dword v[[A_F32:[0-9]+]] 91; GCN: v_cvt_f16_f32_e64 v[[R_F16:[0-9]+]], -v[[A_F32]] 92; GCN: buffer_store_short v[[R_F16]] 93; GCN: s_endpgm 94define void @fneg_fptrunc_f32_to_f16( 95 half addrspace(1)* %r, 96 float addrspace(1)* %a) { 97entry: 98 %a.val = load float, float addrspace(1)* %a 99 %a.fneg = fsub float -0.0, %a.val 100 %r.val = fptrunc float %a.fneg to half 101 store half %r.val, half addrspace(1)* %r 102 ret void 103} 104 105; GCN-LABEL: {{^}}fabs_fptrunc_f32_to_f16: 106; GCN: buffer_load_dword v[[A_F32:[0-9]+]] 107; GCN: v_cvt_f16_f32_e64 v[[R_F16:[0-9]+]], |v[[A_F32]]| 108; GCN: buffer_store_short v[[R_F16]] 109; GCN: s_endpgm 110define void @fabs_fptrunc_f32_to_f16( 111 half addrspace(1)* %r, 112 float addrspace(1)* %a) { 113entry: 114 %a.val = load float, float addrspace(1)* %a 115 %a.fabs = call float @llvm.fabs.f32(float %a.val) 116 %r.val = fptrunc float %a.fabs to half 117 store half %r.val, half addrspace(1)* %r 118 ret void 119} 120 121; GCN-LABEL: {{^}}fneg_fabs_fptrunc_f32_to_f16: 122; GCN: buffer_load_dword v[[A_F32:[0-9]+]] 123; GCN: v_cvt_f16_f32_e64 v[[R_F16:[0-9]+]], -|v[[A_F32]]| 124; GCN: buffer_store_short v[[R_F16]] 125; GCN: s_endpgm 126define void @fneg_fabs_fptrunc_f32_to_f16( 127 half addrspace(1)* %r, 128 float addrspace(1)* %a) { 129entry: 130 %a.val = load float, float addrspace(1)* %a 131 %a.fabs = call float @llvm.fabs.f32(float %a.val) 132 %a.fneg.fabs = fsub float -0.0, %a.fabs 133 %r.val = fptrunc float %a.fneg.fabs to half 134 store half %r.val, half addrspace(1)* %r 135 ret void 136} 137 138declare float @llvm.fabs.f32(float) #1 139 140attributes #1 = { nounwind readnone } 141