1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s 3; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s 4; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s 5; RUN: llc -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s 6 7define float @v_pow_f32(float %x, float %y) { 8; GFX6-LABEL: v_pow_f32: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_log_f32_e32 v0, v0 12; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 13; GFX6-NEXT: v_exp_f32_e32 v0, v0 14; GFX6-NEXT: s_setpc_b64 s[30:31] 15; 16; GFX8-LABEL: v_pow_f32: 17; GFX8: ; %bb.0: 18; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 19; GFX8-NEXT: v_log_f32_e32 v0, v0 20; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 21; GFX8-NEXT: v_exp_f32_e32 v0, v0 22; GFX8-NEXT: s_setpc_b64 s[30:31] 23; 24; GFX9-LABEL: v_pow_f32: 25; GFX9: ; %bb.0: 26; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 27; GFX9-NEXT: v_log_f32_e32 v0, v0 28; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 29; GFX9-NEXT: v_exp_f32_e32 v0, v0 30; GFX9-NEXT: s_setpc_b64 s[30:31] 31; 32; GFX10-LABEL: v_pow_f32: 33; GFX10: ; %bb.0: 34; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 35; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 36; GFX10-NEXT: v_log_f32_e32 v0, v0 37; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 38; GFX10-NEXT: v_exp_f32_e32 v0, v0 39; GFX10-NEXT: s_setpc_b64 s[30:31] 40 %pow = call float @llvm.pow.f32(float %x, float %y) 41 ret float %pow 42} 43 44define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { 45; GFX6-LABEL: v_pow_v2f32: 46; GFX6: ; %bb.0: 47; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 48; GFX6-NEXT: v_log_f32_e32 v0, v0 49; GFX6-NEXT: v_log_f32_e32 v1, v1 50; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 51; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 52; GFX6-NEXT: v_exp_f32_e32 v0, v0 53; GFX6-NEXT: v_exp_f32_e32 v1, v1 54; GFX6-NEXT: s_setpc_b64 s[30:31] 55; 56; GFX8-LABEL: v_pow_v2f32: 57; GFX8: ; %bb.0: 58; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 59; GFX8-NEXT: v_log_f32_e32 v0, v0 60; GFX8-NEXT: v_log_f32_e32 v1, v1 61; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 62; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 63; GFX8-NEXT: v_exp_f32_e32 v0, v0 64; GFX8-NEXT: v_exp_f32_e32 v1, v1 65; GFX8-NEXT: s_setpc_b64 s[30:31] 66; 67; GFX9-LABEL: v_pow_v2f32: 68; GFX9: ; %bb.0: 69; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 70; GFX9-NEXT: v_log_f32_e32 v0, v0 71; GFX9-NEXT: v_log_f32_e32 v1, v1 72; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 73; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 74; GFX9-NEXT: v_exp_f32_e32 v0, v0 75; GFX9-NEXT: v_exp_f32_e32 v1, v1 76; GFX9-NEXT: s_setpc_b64 s[30:31] 77; 78; GFX10-LABEL: v_pow_v2f32: 79; GFX10: ; %bb.0: 80; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 81; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 82; GFX10-NEXT: v_log_f32_e32 v0, v0 83; GFX10-NEXT: v_log_f32_e32 v1, v1 84; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 85; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 86; GFX10-NEXT: v_exp_f32_e32 v0, v0 87; GFX10-NEXT: v_exp_f32_e32 v1, v1 88; GFX10-NEXT: s_setpc_b64 s[30:31] 89 %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y) 90 ret <2 x float> %pow 91} 92 93define half @v_pow_f16(half %x, half %y) { 94; GFX6-LABEL: v_pow_f16: 95; GFX6: ; %bb.0: 96; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 97; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 98; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 99; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 100; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 101; GFX6-NEXT: v_log_f32_e32 v0, v0 102; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 103; GFX6-NEXT: v_exp_f32_e32 v0, v0 104; GFX6-NEXT: s_setpc_b64 s[30:31] 105; 106; GFX8-LABEL: v_pow_f16: 107; GFX8: ; %bb.0: 108; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 109; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 110; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 111; GFX8-NEXT: v_log_f32_e32 v0, v0 112; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 113; GFX8-NEXT: v_exp_f32_e32 v0, v0 114; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 115; GFX8-NEXT: s_setpc_b64 s[30:31] 116; 117; GFX9-LABEL: v_pow_f16: 118; GFX9: ; %bb.0: 119; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 120; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 121; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 122; GFX9-NEXT: v_log_f32_e32 v0, v0 123; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 124; GFX9-NEXT: v_exp_f32_e32 v0, v0 125; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 126; GFX9-NEXT: s_setpc_b64 s[30:31] 127; 128; GFX10-LABEL: v_pow_f16: 129; GFX10: ; %bb.0: 130; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 131; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 132; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 133; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 134; GFX10-NEXT: v_log_f32_e32 v0, v0 135; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 136; GFX10-NEXT: v_exp_f32_e32 v0, v0 137; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 138; GFX10-NEXT: s_setpc_b64 s[30:31] 139 %pow = call half @llvm.pow.f16(half %x, half %y) 140 ret half %pow 141} 142 143define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) { 144; GFX6-LABEL: v_pow_v2f16: 145; GFX6: ; %bb.0: 146; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 147; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 148; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 149; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2 150; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3 151; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 152; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 153; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 154; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 155; GFX6-NEXT: v_log_f32_e32 v0, v0 156; GFX6-NEXT: v_log_f32_e32 v1, v1 157; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 158; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 159; GFX6-NEXT: v_exp_f32_e32 v0, v0 160; GFX6-NEXT: v_exp_f32_e32 v1, v1 161; GFX6-NEXT: s_setpc_b64 s[30:31] 162; 163; GFX8-LABEL: v_pow_v2f16: 164; GFX8: ; %bb.0: 165; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 166; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 167; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 168; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 169; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 170; GFX8-NEXT: v_log_f32_e32 v2, v2 171; GFX8-NEXT: v_log_f32_e32 v0, v0 172; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 173; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 174; GFX8-NEXT: v_exp_f32_e32 v0, v0 175; GFX8-NEXT: v_exp_f32_e32 v2, v2 176; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 177; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 178; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 179; GFX8-NEXT: s_setpc_b64 s[30:31] 180; 181; GFX9-LABEL: v_pow_v2f16: 182; GFX9: ; %bb.0: 183; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 184; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 185; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 186; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 187; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 188; GFX9-NEXT: v_log_f32_e32 v2, v2 189; GFX9-NEXT: v_log_f32_e32 v0, v0 190; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 191; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 192; GFX9-NEXT: v_exp_f32_e32 v0, v0 193; GFX9-NEXT: v_exp_f32_e32 v1, v2 194; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 195; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1 196; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 197; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0 198; GFX9-NEXT: s_setpc_b64 s[30:31] 199; 200; GFX10-LABEL: v_pow_v2f16: 201; GFX10: ; %bb.0: 202; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 203; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 204; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0 205; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 206; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 207; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 208; GFX10-NEXT: v_log_f32_e32 v2, v2 209; GFX10-NEXT: v_log_f32_e32 v0, v0 210; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 211; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 212; GFX10-NEXT: v_exp_f32_e32 v1, v2 213; GFX10-NEXT: v_exp_f32_e32 v0, v0 214; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 215; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 216; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 217; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1 218; GFX10-NEXT: s_setpc_b64 s[30:31] 219 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y) 220 ret <2 x half> %pow 221} 222 223define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) { 224; GFX6-LABEL: v_pow_v2f16_fneg_lhs: 225; GFX6: ; %bb.0: 226; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 227; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 228; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 229; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2 230; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 231; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 232; GFX6-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 233; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v3 234; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v0 235; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0 236; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 237; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 238; GFX6-NEXT: v_log_f32_e32 v3, v3 239; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 240; GFX6-NEXT: v_log_f32_e32 v4, v0 241; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v2, v3 242; GFX6-NEXT: v_exp_f32_e32 v0, v0 243; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v4 244; GFX6-NEXT: v_exp_f32_e32 v1, v1 245; GFX6-NEXT: s_setpc_b64 s[30:31] 246; 247; GFX8-LABEL: v_pow_v2f16_fneg_lhs: 248; GFX8: ; %bb.0: 249; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 250; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 251; GFX8-NEXT: v_cvt_f32_f16_e64 v0, -v0 252; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 253; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 254; GFX8-NEXT: v_log_f32_e32 v2, v2 255; GFX8-NEXT: v_log_f32_e32 v0, v0 256; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 257; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 258; GFX8-NEXT: v_exp_f32_e32 v0, v0 259; GFX8-NEXT: v_exp_f32_e32 v2, v2 260; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 261; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 262; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 263; GFX8-NEXT: s_setpc_b64 s[30:31] 264; 265; GFX9-LABEL: v_pow_v2f16_fneg_lhs: 266; GFX9: ; %bb.0: 267; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 268; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 269; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -v0 270; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 271; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 272; GFX9-NEXT: v_log_f32_e32 v2, v2 273; GFX9-NEXT: v_log_f32_e32 v0, v0 274; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 275; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 276; GFX9-NEXT: v_exp_f32_e32 v0, v0 277; GFX9-NEXT: v_exp_f32_e32 v1, v2 278; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 279; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1 280; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 281; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0 282; GFX9-NEXT: s_setpc_b64 s[30:31] 283; 284; GFX10-LABEL: v_pow_v2f16_fneg_lhs: 285; GFX10: ; %bb.0: 286; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 287; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 288; GFX10-NEXT: v_cvt_f32_f16_e64 v2, -v0 289; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 290; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 291; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 292; GFX10-NEXT: v_log_f32_e32 v2, v2 293; GFX10-NEXT: v_log_f32_e32 v0, v0 294; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 295; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 296; GFX10-NEXT: v_exp_f32_e32 v1, v2 297; GFX10-NEXT: v_exp_f32_e32 v0, v0 298; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 299; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 300; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 301; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1 302; GFX10-NEXT: s_setpc_b64 s[30:31] 303 %x.fneg = fneg <2 x half> %x 304 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y) 305 ret <2 x half> %pow 306} 307 308define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) { 309; GFX6-LABEL: v_pow_v2f16_fneg_rhs: 310; GFX6: ; %bb.0: 311; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 312; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3 313; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 314; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 315; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2 316; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 317; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 318; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 319; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 320; GFX6-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 321; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2 322; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 323; GFX6-NEXT: v_log_f32_e32 v0, v0 324; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 325; GFX6-NEXT: v_log_f32_e32 v1, v1 326; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 327; GFX6-NEXT: v_exp_f32_e32 v0, v0 328; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 329; GFX6-NEXT: v_exp_f32_e32 v1, v1 330; GFX6-NEXT: s_setpc_b64 s[30:31] 331; 332; GFX8-LABEL: v_pow_v2f16_fneg_rhs: 333; GFX8: ; %bb.0: 334; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 335; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 336; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 337; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 338; GFX8-NEXT: v_cvt_f32_f16_e64 v1, -v1 339; GFX8-NEXT: v_log_f32_e32 v2, v2 340; GFX8-NEXT: v_log_f32_e32 v0, v0 341; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 342; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 343; GFX8-NEXT: v_exp_f32_e32 v0, v0 344; GFX8-NEXT: v_exp_f32_e32 v2, v2 345; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 346; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 347; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 348; GFX8-NEXT: s_setpc_b64 s[30:31] 349; 350; GFX9-LABEL: v_pow_v2f16_fneg_rhs: 351; GFX9: ; %bb.0: 352; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 353; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 354; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 355; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 356; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1 357; GFX9-NEXT: v_log_f32_e32 v2, v2 358; GFX9-NEXT: v_log_f32_e32 v0, v0 359; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 360; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 361; GFX9-NEXT: v_exp_f32_e32 v0, v0 362; GFX9-NEXT: v_exp_f32_e32 v1, v2 363; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 364; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1 365; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 366; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0 367; GFX9-NEXT: s_setpc_b64 s[30:31] 368; 369; GFX10-LABEL: v_pow_v2f16_fneg_rhs: 370; GFX10: ; %bb.0: 371; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 372; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 373; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0 374; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 375; GFX10-NEXT: v_cvt_f32_f16_e64 v3, -v1 376; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 377; GFX10-NEXT: v_log_f32_e32 v2, v2 378; GFX10-NEXT: v_log_f32_e32 v0, v0 379; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 380; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 381; GFX10-NEXT: v_exp_f32_e32 v1, v2 382; GFX10-NEXT: v_exp_f32_e32 v0, v0 383; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 384; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 385; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 386; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1 387; GFX10-NEXT: s_setpc_b64 s[30:31] 388 %y.fneg = fneg <2 x half> %y 389 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x, <2 x half> %y.fneg) 390 ret <2 x half> %pow 391} 392 393define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) { 394; GFX6-LABEL: v_pow_v2f16_fneg_lhs_rhs: 395; GFX6: ; %bb.0: 396; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 397; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 398; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 399; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3 400; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2 401; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 402; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 403; GFX6-NEXT: s_mov_b32 s4, 0x80008000 404; GFX6-NEXT: v_xor_b32_e32 v0, s4, v0 405; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 406; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1 407; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0 408; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3 409; GFX6-NEXT: v_or_b32_e32 v2, v2, v3 410; GFX6-NEXT: v_xor_b32_e32 v2, s4, v2 411; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v2 412; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v2 413; GFX6-NEXT: v_log_f32_e32 v0, v0 414; GFX6-NEXT: v_cvt_f32_f16_e32 v3, v3 415; GFX6-NEXT: v_log_f32_e32 v1, v1 416; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 417; GFX6-NEXT: v_exp_f32_e32 v0, v0 418; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 419; GFX6-NEXT: v_exp_f32_e32 v1, v1 420; GFX6-NEXT: s_setpc_b64 s[30:31] 421; 422; GFX8-LABEL: v_pow_v2f16_fneg_lhs_rhs: 423; GFX8: ; %bb.0: 424; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 425; GFX8-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 426; GFX8-NEXT: v_cvt_f32_f16_e64 v0, -v0 427; GFX8-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 428; GFX8-NEXT: v_cvt_f32_f16_e64 v1, -v1 429; GFX8-NEXT: v_log_f32_e32 v2, v2 430; GFX8-NEXT: v_log_f32_e32 v0, v0 431; GFX8-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 432; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 433; GFX8-NEXT: v_exp_f32_e32 v0, v0 434; GFX8-NEXT: v_exp_f32_e32 v2, v2 435; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0 436; GFX8-NEXT: v_cvt_f16_f32_sdwa v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD 437; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 438; GFX8-NEXT: s_setpc_b64 s[30:31] 439; 440; GFX9-LABEL: v_pow_v2f16_fneg_lhs_rhs: 441; GFX9: ; %bb.0: 442; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 443; GFX9-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 444; GFX9-NEXT: v_cvt_f32_f16_e64 v0, -v0 445; GFX9-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 446; GFX9-NEXT: v_cvt_f32_f16_e64 v1, -v1 447; GFX9-NEXT: v_log_f32_e32 v2, v2 448; GFX9-NEXT: v_log_f32_e32 v0, v0 449; GFX9-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 450; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 451; GFX9-NEXT: v_exp_f32_e32 v0, v0 452; GFX9-NEXT: v_exp_f32_e32 v1, v2 453; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 454; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v1 455; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 456; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0 457; GFX9-NEXT: s_setpc_b64 s[30:31] 458; 459; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs: 460; GFX10: ; %bb.0: 461; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 462; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 463; GFX10-NEXT: v_cvt_f32_f16_e64 v2, -v0 464; GFX10-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 465; GFX10-NEXT: v_cvt_f32_f16_e64 v3, -v1 466; GFX10-NEXT: v_cvt_f32_f16_sdwa v1, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 467; GFX10-NEXT: v_log_f32_e32 v2, v2 468; GFX10-NEXT: v_log_f32_e32 v0, v0 469; GFX10-NEXT: v_mul_legacy_f32_e32 v2, v3, v2 470; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 471; GFX10-NEXT: v_exp_f32_e32 v1, v2 472; GFX10-NEXT: v_exp_f32_e32 v0, v0 473; GFX10-NEXT: v_cvt_f16_f32_e32 v1, v1 474; GFX10-NEXT: v_cvt_f16_f32_e32 v0, v0 475; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 476; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1 477; GFX10-NEXT: s_setpc_b64 s[30:31] 478 %x.fneg = fneg <2 x half> %x 479 %y.fneg = fneg <2 x half> %y 480 %pow = call <2 x half> @llvm.pow.v2f16(<2 x half> %x.fneg, <2 x half> %y.fneg) 481 ret <2 x half> %pow 482} 483 484; FIXME 485; define double @v_pow_f64(double %x, double %y) { 486; %pow = call double @llvm.pow.f64(double %x, double %y) 487; ret double %pow 488; } 489 490define float @v_pow_f32_fabs_lhs(float %x, float %y) { 491; GFX6-LABEL: v_pow_f32_fabs_lhs: 492; GFX6: ; %bb.0: 493; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 494; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 495; GFX6-NEXT: v_log_f32_e32 v0, v0 496; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 497; GFX6-NEXT: v_exp_f32_e32 v0, v0 498; GFX6-NEXT: s_setpc_b64 s[30:31] 499; 500; GFX8-LABEL: v_pow_f32_fabs_lhs: 501; GFX8: ; %bb.0: 502; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 503; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 504; GFX8-NEXT: v_log_f32_e32 v0, v0 505; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 506; GFX8-NEXT: v_exp_f32_e32 v0, v0 507; GFX8-NEXT: s_setpc_b64 s[30:31] 508; 509; GFX9-LABEL: v_pow_f32_fabs_lhs: 510; GFX9: ; %bb.0: 511; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 512; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 513; GFX9-NEXT: v_log_f32_e32 v0, v0 514; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 515; GFX9-NEXT: v_exp_f32_e32 v0, v0 516; GFX9-NEXT: s_setpc_b64 s[30:31] 517; 518; GFX10-LABEL: v_pow_f32_fabs_lhs: 519; GFX10: ; %bb.0: 520; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 521; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 522; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 523; GFX10-NEXT: v_log_f32_e32 v0, v0 524; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 525; GFX10-NEXT: v_exp_f32_e32 v0, v0 526; GFX10-NEXT: s_setpc_b64 s[30:31] 527 %fabs.x = call float @llvm.fabs.f32(float %x) 528 %pow = call float @llvm.pow.f32(float %fabs.x, float %y) 529 ret float %pow 530} 531 532define float @v_pow_f32_fabs_rhs(float %x, float %y) { 533; GFX6-LABEL: v_pow_f32_fabs_rhs: 534; GFX6: ; %bb.0: 535; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 536; GFX6-NEXT: v_log_f32_e32 v0, v0 537; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 538; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 539; GFX6-NEXT: v_exp_f32_e32 v0, v0 540; GFX6-NEXT: s_setpc_b64 s[30:31] 541; 542; GFX8-LABEL: v_pow_f32_fabs_rhs: 543; GFX8: ; %bb.0: 544; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 545; GFX8-NEXT: v_log_f32_e32 v0, v0 546; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 547; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 548; GFX8-NEXT: v_exp_f32_e32 v0, v0 549; GFX8-NEXT: s_setpc_b64 s[30:31] 550; 551; GFX9-LABEL: v_pow_f32_fabs_rhs: 552; GFX9: ; %bb.0: 553; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 554; GFX9-NEXT: v_log_f32_e32 v0, v0 555; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 556; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 557; GFX9-NEXT: v_exp_f32_e32 v0, v0 558; GFX9-NEXT: s_setpc_b64 s[30:31] 559; 560; GFX10-LABEL: v_pow_f32_fabs_rhs: 561; GFX10: ; %bb.0: 562; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 563; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 564; GFX10-NEXT: v_log_f32_e32 v0, v0 565; GFX10-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 566; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 567; GFX10-NEXT: v_exp_f32_e32 v0, v0 568; GFX10-NEXT: s_setpc_b64 s[30:31] 569 %fabs.y = call float @llvm.fabs.f32(float %y) 570 %pow = call float @llvm.pow.f32(float %x, float %fabs.y) 571 ret float %pow 572} 573 574define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { 575; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs: 576; GFX6: ; %bb.0: 577; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 578; GFX6-NEXT: s_brev_b32 s4, -2 579; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 580; GFX6-NEXT: v_log_f32_e32 v0, v0 581; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 582; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 583; GFX6-NEXT: v_exp_f32_e32 v0, v0 584; GFX6-NEXT: s_setpc_b64 s[30:31] 585; 586; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: 587; GFX8: ; %bb.0: 588; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 589; GFX8-NEXT: s_brev_b32 s4, -2 590; GFX8-NEXT: v_and_b32_e32 v0, s4, v0 591; GFX8-NEXT: v_log_f32_e32 v0, v0 592; GFX8-NEXT: v_and_b32_e32 v1, s4, v1 593; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 594; GFX8-NEXT: v_exp_f32_e32 v0, v0 595; GFX8-NEXT: s_setpc_b64 s[30:31] 596; 597; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: 598; GFX9: ; %bb.0: 599; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 600; GFX9-NEXT: s_brev_b32 s4, -2 601; GFX9-NEXT: v_and_b32_e32 v0, s4, v0 602; GFX9-NEXT: v_log_f32_e32 v0, v0 603; GFX9-NEXT: v_and_b32_e32 v1, s4, v1 604; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 605; GFX9-NEXT: v_exp_f32_e32 v0, v0 606; GFX9-NEXT: s_setpc_b64 s[30:31] 607; 608; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs: 609; GFX10: ; %bb.0: 610; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 611; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 612; GFX10-NEXT: s_brev_b32 s4, -2 613; GFX10-NEXT: v_and_b32_e32 v0, s4, v0 614; GFX10-NEXT: v_and_b32_e32 v1, s4, v1 615; GFX10-NEXT: v_log_f32_e32 v0, v0 616; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 617; GFX10-NEXT: v_exp_f32_e32 v0, v0 618; GFX10-NEXT: s_setpc_b64 s[30:31] 619 %fabs.x = call float @llvm.fabs.f32(float %x) 620 %fabs.y = call float @llvm.fabs.f32(float %y) 621 %pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y) 622 ret float %pow 623} 624 625define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { 626; GFX6-LABEL: v_pow_f32_sgpr_vgpr: 627; GFX6: ; %bb.0: 628; GFX6-NEXT: v_log_f32_e32 v1, s0 629; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 630; GFX6-NEXT: v_exp_f32_e32 v0, v0 631; GFX6-NEXT: ; return to shader part epilog 632; 633; GFX8-LABEL: v_pow_f32_sgpr_vgpr: 634; GFX8: ; %bb.0: 635; GFX8-NEXT: v_log_f32_e32 v1, s0 636; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 637; GFX8-NEXT: v_exp_f32_e32 v0, v0 638; GFX8-NEXT: ; return to shader part epilog 639; 640; GFX9-LABEL: v_pow_f32_sgpr_vgpr: 641; GFX9: ; %bb.0: 642; GFX9-NEXT: v_log_f32_e32 v1, s0 643; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 644; GFX9-NEXT: v_exp_f32_e32 v0, v0 645; GFX9-NEXT: ; return to shader part epilog 646; 647; GFX10-LABEL: v_pow_f32_sgpr_vgpr: 648; GFX10: ; %bb.0: 649; GFX10-NEXT: v_log_f32_e32 v1, s0 650; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 651; GFX10-NEXT: v_exp_f32_e32 v0, v0 652; GFX10-NEXT: ; return to shader part epilog 653 %pow = call float @llvm.pow.f32(float %x, float %y) 654 ret float %pow 655} 656 657define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { 658; GFX6-LABEL: v_pow_f32_vgpr_sgpr: 659; GFX6: ; %bb.0: 660; GFX6-NEXT: v_log_f32_e32 v0, v0 661; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 662; GFX6-NEXT: v_exp_f32_e32 v0, v0 663; GFX6-NEXT: ; return to shader part epilog 664; 665; GFX8-LABEL: v_pow_f32_vgpr_sgpr: 666; GFX8: ; %bb.0: 667; GFX8-NEXT: v_log_f32_e32 v0, v0 668; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 669; GFX8-NEXT: v_exp_f32_e32 v0, v0 670; GFX8-NEXT: ; return to shader part epilog 671; 672; GFX9-LABEL: v_pow_f32_vgpr_sgpr: 673; GFX9: ; %bb.0: 674; GFX9-NEXT: v_log_f32_e32 v0, v0 675; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 676; GFX9-NEXT: v_exp_f32_e32 v0, v0 677; GFX9-NEXT: ; return to shader part epilog 678; 679; GFX10-LABEL: v_pow_f32_vgpr_sgpr: 680; GFX10: ; %bb.0: 681; GFX10-NEXT: v_log_f32_e32 v0, v0 682; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 683; GFX10-NEXT: v_exp_f32_e32 v0, v0 684; GFX10-NEXT: ; return to shader part epilog 685 %pow = call float @llvm.pow.f32(float %x, float %y) 686 ret float %pow 687} 688 689define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { 690; GFX6-LABEL: v_pow_f32_sgpr_sgpr: 691; GFX6: ; %bb.0: 692; GFX6-NEXT: v_log_f32_e32 v0, s0 693; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 694; GFX6-NEXT: v_exp_f32_e32 v0, v0 695; GFX6-NEXT: ; return to shader part epilog 696; 697; GFX8-LABEL: v_pow_f32_sgpr_sgpr: 698; GFX8: ; %bb.0: 699; GFX8-NEXT: v_log_f32_e32 v0, s0 700; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 701; GFX8-NEXT: v_exp_f32_e32 v0, v0 702; GFX8-NEXT: ; return to shader part epilog 703; 704; GFX9-LABEL: v_pow_f32_sgpr_sgpr: 705; GFX9: ; %bb.0: 706; GFX9-NEXT: v_log_f32_e32 v0, s0 707; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 708; GFX9-NEXT: v_exp_f32_e32 v0, v0 709; GFX9-NEXT: ; return to shader part epilog 710; 711; GFX10-LABEL: v_pow_f32_sgpr_sgpr: 712; GFX10: ; %bb.0: 713; GFX10-NEXT: v_log_f32_e32 v0, s0 714; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 715; GFX10-NEXT: v_exp_f32_e32 v0, v0 716; GFX10-NEXT: ; return to shader part epilog 717 %pow = call float @llvm.pow.f32(float %x, float %y) 718 ret float %pow 719} 720 721declare half @llvm.pow.f16(half, half) 722declare float @llvm.pow.f32(float, float) 723declare double @llvm.pow.f64(double, double) 724 725declare half @llvm.fabs.f16(half) 726declare float @llvm.fabs.f32(float) 727 728declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>) 729declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>) 730