1; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4; GCN-LABEL: {{^}}fpext_f16_to_f32
5; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
6; GCN: v_cvt_f32_f16_e32 v[[R_F32:[0-9]+]], v[[A_F16]]
7; GCN: buffer_store_dword v[[R_F32]]
8; GCN: s_endpgm
9define void @fpext_f16_to_f32(
10    float addrspace(1)* %r,
11    half addrspace(1)* %a) {
12entry:
13  %a.val = load half, half addrspace(1)* %a
14  %r.val = fpext half %a.val to float
15  store float %r.val, float addrspace(1)* %r
16  ret void
17}
18
19; GCN-LABEL: {{^}}fpext_f16_to_f64
20; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
21; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
22; GCN: v_cvt_f64_f32_e32 v{{\[}}[[R_F64_0:[0-9]+]]:[[R_F64_1:[0-9]+]]{{\]}}, v[[A_F32]]
23; GCN: buffer_store_dwordx2 v{{\[}}[[R_F64_0]]:[[R_F64_1]]{{\]}}
24; GCN: s_endpgm
25define void @fpext_f16_to_f64(
26    double addrspace(1)* %r,
27    half addrspace(1)* %a) {
28entry:
29  %a.val = load half, half addrspace(1)* %a
30  %r.val = fpext half %a.val to double
31  store double %r.val, double addrspace(1)* %r
32  ret void
33}
34
35; GCN-LABEL: {{^}}fpext_v2f16_to_v2f32
36; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
37; VI:  v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
38; GCN: v_cvt_f32_f16_e32 v[[R_F32_0:[0-9]+]], v[[A_V2_F16]]
39; SI:  v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
40; GCN: v_cvt_f32_f16_e32 v[[R_F32_1:[0-9]+]], v[[A_F16_1]]
41; GCN: buffer_store_dwordx2 v{{\[}}[[R_F32_0]]:[[R_F32_1]]{{\]}}
42; GCN: s_endpgm
43define void @fpext_v2f16_to_v2f32(
44    <2 x float> addrspace(1)* %r,
45    <2 x half> addrspace(1)* %a) {
46entry:
47  %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
48  %r.val = fpext <2 x half> %a.val to <2 x float>
49  store <2 x float> %r.val, <2 x float> addrspace(1)* %r
50  ret void
51}
52
53; GCN-LABEL: {{^}}fpext_v2f16_to_v2f64
54; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
55; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
56; GCN: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
57; GCN: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
58; GCN: v_cvt_f64_f32_e32 v{{\[}}{{[0-9]+}}:[[R_F64_3:[0-9]+]]{{\]}}, v[[A_F32_1]]
59; GCN: v_cvt_f64_f32_e32 v{{\[}}[[R_F64_0:[0-9]+]]:{{[0-9]+}}{{\]}}, v[[A_F32_0]]
60; GCN: buffer_store_dwordx4 v{{\[}}[[R_F64_0]]:[[R_F64_3]]{{\]}}
61; GCN: s_endpgm
62define void @fpext_v2f16_to_v2f64(
63    <2 x double> addrspace(1)* %r,
64    <2 x half> addrspace(1)* %a) {
65entry:
66  %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
67  %r.val = fpext <2 x half> %a.val to <2 x double>
68  store <2 x double> %r.val, <2 x double> addrspace(1)* %r
69  ret void
70}
71