1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI 3; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI 4; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG 5 6declare float @llvm.fabs.f32(float) #1 7 8define amdgpu_kernel void @fp_to_uint_f32_to_i32 (i32 addrspace(1)* %out, float %in) { 9; SI-LABEL: fp_to_uint_f32_to_i32: 10; SI: ; %bb.0: 11; SI-NEXT: s_load_dword s4, s[0:1], 0xb 12; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 13; SI-NEXT: s_mov_b32 s3, 0xf000 14; SI-NEXT: s_mov_b32 s2, -1 15; SI-NEXT: s_waitcnt lgkmcnt(0) 16; SI-NEXT: v_cvt_u32_f32_e32 v0, s4 17; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 18; SI-NEXT: s_endpgm 19; 20; VI-LABEL: fp_to_uint_f32_to_i32: 21; VI: ; %bb.0: 22; VI-NEXT: s_load_dword s2, s[0:1], 0x2c 23; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 24; VI-NEXT: s_mov_b32 s3, 0xf000 25; VI-NEXT: s_waitcnt lgkmcnt(0) 26; VI-NEXT: v_cvt_u32_f32_e32 v0, s2 27; VI-NEXT: s_mov_b32 s2, -1 28; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 29; VI-NEXT: s_endpgm 30; 31; EG-LABEL: fp_to_uint_f32_to_i32: 32; EG: ; %bb.0: 33; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] 34; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 35; EG-NEXT: CF_END 36; EG-NEXT: PAD 37; EG-NEXT: ALU clause starting at 4: 38; EG-NEXT: TRUNC * T0.W, KC0[2].Z, 39; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x, 40; EG-NEXT: FLT_TO_UINT * T1.X, PV.W, 41; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 42 %conv = fptoui float %in to i32 43 store i32 %conv, i32 addrspace(1)* %out 44 ret void 45} 46 47define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) { 48; SI-LABEL: fp_to_uint_v2f32_to_v2i32: 49; SI: ; %bb.0: 50; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 51; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 52; SI-NEXT: s_mov_b32 s3, 0xf000 53; SI-NEXT: s_mov_b32 s2, -1 54; SI-NEXT: s_waitcnt lgkmcnt(0) 55; SI-NEXT: v_cvt_u32_f32_e32 v1, s5 56; SI-NEXT: v_cvt_u32_f32_e32 v0, s4 57; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 58; SI-NEXT: s_endpgm 59; 60; VI-LABEL: fp_to_uint_v2f32_to_v2i32: 61; VI: ; %bb.0: 62; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c 63; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 64; VI-NEXT: s_waitcnt lgkmcnt(0) 65; VI-NEXT: v_cvt_u32_f32_e32 v1, s3 66; VI-NEXT: v_cvt_u32_f32_e32 v0, s2 67; VI-NEXT: s_mov_b32 s3, 0xf000 68; VI-NEXT: s_mov_b32 s2, -1 69; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 70; VI-NEXT: s_endpgm 71; 72; EG-LABEL: fp_to_uint_v2f32_to_v2i32: 73; EG: ; %bb.0: 74; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] 75; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 76; EG-NEXT: CF_END 77; EG-NEXT: PAD 78; EG-NEXT: ALU clause starting at 4: 79; EG-NEXT: TRUNC T0.W, KC0[3].X, 80; EG-NEXT: TRUNC * T1.W, KC0[2].W, 81; EG-NEXT: FLT_TO_UINT * T0.Y, PV.W, 82; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x, 83; EG-NEXT: FLT_TO_UINT * T0.X, T1.W, 84; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 85 %result = fptoui <2 x float> %in to <2 x i32> 86 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 87 ret void 88} 89 90define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { 91; SI-LABEL: fp_to_uint_v4f32_to_v4i32: 92; SI: ; %bb.0: 93; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 94; SI-NEXT: s_waitcnt lgkmcnt(0) 95; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 96; SI-NEXT: s_mov_b32 s3, 0xf000 97; SI-NEXT: s_mov_b32 s2, -1 98; SI-NEXT: s_waitcnt lgkmcnt(0) 99; SI-NEXT: v_cvt_u32_f32_e32 v3, s7 100; SI-NEXT: v_cvt_u32_f32_e32 v2, s6 101; SI-NEXT: v_cvt_u32_f32_e32 v1, s5 102; SI-NEXT: v_cvt_u32_f32_e32 v0, s4 103; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 104; SI-NEXT: s_endpgm 105; 106; VI-LABEL: fp_to_uint_v4f32_to_v4i32: 107; VI: ; %bb.0: 108; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 109; VI-NEXT: s_waitcnt lgkmcnt(0) 110; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 111; VI-NEXT: s_mov_b32 s3, 0xf000 112; VI-NEXT: s_mov_b32 s2, -1 113; VI-NEXT: s_waitcnt lgkmcnt(0) 114; VI-NEXT: v_cvt_u32_f32_e32 v3, s7 115; VI-NEXT: v_cvt_u32_f32_e32 v2, s6 116; VI-NEXT: v_cvt_u32_f32_e32 v1, s5 117; VI-NEXT: v_cvt_u32_f32_e32 v0, s4 118; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 119; VI-NEXT: s_endpgm 120; 121; EG-LABEL: fp_to_uint_v4f32_to_v4i32: 122; EG: ; %bb.0: 123; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 124; EG-NEXT: TEX 0 @6 125; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[] 126; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 127; EG-NEXT: CF_END 128; EG-NEXT: PAD 129; EG-NEXT: Fetch clause starting at 6: 130; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 131; EG-NEXT: ALU clause starting at 8: 132; EG-NEXT: MOV * T0.X, KC0[2].Z, 133; EG-NEXT: ALU clause starting at 9: 134; EG-NEXT: TRUNC T0.W, T0.W, 135; EG-NEXT: TRUNC * T1.W, T0.Z, 136; EG-NEXT: FLT_TO_UINT * T0.W, PV.W, 137; EG-NEXT: TRUNC T2.W, T0.Y, 138; EG-NEXT: FLT_TO_UINT * T0.Z, T1.W, 139; EG-NEXT: TRUNC T1.W, T0.X, 140; EG-NEXT: FLT_TO_UINT * T0.Y, PV.W, 141; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x, 142; EG-NEXT: FLT_TO_UINT * T0.X, PV.W, 143; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 144 %value = load <4 x float>, <4 x float> addrspace(1) * %in 145 %result = fptoui <4 x float> %value to <4 x i32> 146 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 147 ret void 148} 149 150define amdgpu_kernel void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %x) { 151; SI-LABEL: fp_to_uint_f32_to_i64: 152; SI: ; %bb.0: 153; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 154; SI-NEXT: s_load_dword s0, s[0:1], 0xb 155; SI-NEXT: s_mov_b32 s7, 0xf000 156; SI-NEXT: s_mov_b32 s6, -1 157; SI-NEXT: s_mov_b32 s1, 0xcf800000 158; SI-NEXT: s_waitcnt lgkmcnt(0) 159; SI-NEXT: v_trunc_f32_e32 v0, s0 160; SI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 161; SI-NEXT: v_floor_f32_e32 v2, v1 162; SI-NEXT: v_cvt_u32_f32_e32 v1, v2 163; SI-NEXT: v_fma_f32 v0, v2, s1, v0 164; SI-NEXT: v_cvt_u32_f32_e32 v0, v0 165; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 166; SI-NEXT: s_endpgm 167; 168; VI-LABEL: fp_to_uint_f32_to_i64: 169; VI: ; %bb.0: 170; VI-NEXT: s_load_dword s2, s[0:1], 0x2c 171; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 172; VI-NEXT: s_mov_b32 s3, 0xcf800000 173; VI-NEXT: s_waitcnt lgkmcnt(0) 174; VI-NEXT: v_trunc_f32_e32 v0, s2 175; VI-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 176; VI-NEXT: v_floor_f32_e32 v2, v1 177; VI-NEXT: v_fma_f32 v0, v2, s3, v0 178; VI-NEXT: v_cvt_u32_f32_e32 v1, v2 179; VI-NEXT: v_cvt_u32_f32_e32 v0, v0 180; VI-NEXT: s_mov_b32 s3, 0xf000 181; VI-NEXT: s_mov_b32 s2, -1 182; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 183; VI-NEXT: s_endpgm 184; 185; EG-LABEL: fp_to_uint_f32_to_i64: 186; EG: ; %bb.0: 187; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[] 188; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 189; EG-NEXT: CF_END 190; EG-NEXT: PAD 191; EG-NEXT: ALU clause starting at 4: 192; EG-NEXT: MOV * T0.W, literal.x, 193; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) 194; EG-NEXT: BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W, 195; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.y, 196; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38) 197; EG-NEXT: OR_INT T1.W, PS, literal.x, 198; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y, 199; EG-NEXT: 8388608(1.175494e-38), -150(nan) 200; EG-NEXT: ADD_INT T0.X, T0.W, literal.x, 201; EG-NEXT: SUB_INT T0.Y, literal.y, T0.W, 202; EG-NEXT: AND_INT T0.Z, PS, literal.z, 203; EG-NEXT: NOT_INT T0.W, PS, 204; EG-NEXT: LSHR * T3.W, PV.W, 1, 205; EG-NEXT: -127(nan), 150(2.101948e-43) 206; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 207; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W, 208; EG-NEXT: LSHL T1.Y, T1.W, PV.Z, 209; EG-NEXT: AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212 210; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122 211; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x, 212; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 213; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0, 214; EG-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, 0.0, 215; EG-NEXT: CNDE_INT T0.W, PV.Z, PV.X, PV.Y, 216; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x, 217; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00) 218; EG-NEXT: CNDE_INT T0.Z, PS, 0.0, PV.W, 219; EG-NEXT: CNDE_INT T0.W, PS, PV.Y, PV.Z, 220; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x, 221; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 222; EG-NEXT: XOR_INT T0.W, PV.W, PS, 223; EG-NEXT: XOR_INT * T2.W, PV.Z, PS, 224; EG-NEXT: SUB_INT T2.W, PS, T1.W, 225; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W, 226; EG-NEXT: SUB_INT T2.W, PV.W, PS, 227; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X, 228; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0, 229; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W, 230; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0, 231; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 232; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 233 %conv = fptoui float %x to i64 234 store i64 %conv, i64 addrspace(1)* %out 235 ret void 236} 237 238define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) { 239; SI-LABEL: fp_to_uint_v2f32_to_v2i64: 240; SI: ; %bb.0: 241; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 242; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb 243; SI-NEXT: s_mov_b32 s7, 0xf000 244; SI-NEXT: s_mov_b32 s6, -1 245; SI-NEXT: s_mov_b32 s2, 0x2f800000 246; SI-NEXT: s_mov_b32 s3, 0xcf800000 247; SI-NEXT: s_waitcnt lgkmcnt(0) 248; SI-NEXT: v_trunc_f32_e32 v0, s1 249; SI-NEXT: v_trunc_f32_e32 v2, s0 250; SI-NEXT: v_mul_f32_e32 v1, s2, v0 251; SI-NEXT: v_mul_f32_e32 v3, s2, v2 252; SI-NEXT: v_floor_f32_e32 v4, v1 253; SI-NEXT: v_floor_f32_e32 v5, v3 254; SI-NEXT: v_cvt_u32_f32_e32 v3, v4 255; SI-NEXT: v_cvt_u32_f32_e32 v1, v5 256; SI-NEXT: v_fma_f32 v0, v4, s3, v0 257; SI-NEXT: v_fma_f32 v4, v5, s3, v2 258; SI-NEXT: v_cvt_u32_f32_e32 v2, v0 259; SI-NEXT: v_cvt_u32_f32_e32 v0, v4 260; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 261; SI-NEXT: s_endpgm 262; 263; VI-LABEL: fp_to_uint_v2f32_to_v2i64: 264; VI: ; %bb.0: 265; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c 266; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 267; VI-NEXT: s_mov_b32 s4, 0x2f800000 268; VI-NEXT: s_waitcnt lgkmcnt(0) 269; VI-NEXT: v_trunc_f32_e32 v0, s3 270; VI-NEXT: v_trunc_f32_e32 v4, s2 271; VI-NEXT: v_mul_f32_e32 v1, s4, v0 272; VI-NEXT: v_mul_f32_e32 v2, s4, v4 273; VI-NEXT: v_floor_f32_e32 v5, v1 274; VI-NEXT: s_mov_b32 s2, 0xcf800000 275; VI-NEXT: v_floor_f32_e32 v6, v2 276; VI-NEXT: v_fma_f32 v0, v5, s2, v0 277; VI-NEXT: v_cvt_u32_f32_e32 v2, v0 278; VI-NEXT: v_fma_f32 v0, v6, s2, v4 279; VI-NEXT: v_cvt_u32_f32_e32 v3, v5 280; VI-NEXT: v_cvt_u32_f32_e32 v1, v6 281; VI-NEXT: v_cvt_u32_f32_e32 v0, v0 282; VI-NEXT: s_mov_b32 s3, 0xf000 283; VI-NEXT: s_mov_b32 s2, -1 284; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 285; VI-NEXT: s_endpgm 286; 287; EG-LABEL: fp_to_uint_v2f32_to_v2i64: 288; EG: ; %bb.0: 289; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[] 290; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1 291; EG-NEXT: CF_END 292; EG-NEXT: PAD 293; EG-NEXT: ALU clause starting at 4: 294; EG-NEXT: MOV * T0.W, literal.x, 295; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) 296; EG-NEXT: BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W, 297; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00) 298; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x, 299; EG-NEXT: BFE_UINT T0.W, KC0[3].X, literal.y, T0.W, 300; EG-NEXT: ADD_INT * T2.W, PV.W, literal.z, 301; EG-NEXT: 8388607(1.175494e-38), 23(3.222986e-44) 302; EG-NEXT: -150(nan), 0(0.000000e+00) 303; EG-NEXT: SUB_INT T0.X, literal.x, PV.W, 304; EG-NEXT: SUB_INT T0.Y, literal.x, T1.W, 305; EG-NEXT: AND_INT T1.Z, PS, literal.y, 306; EG-NEXT: OR_INT T3.W, PV.Z, literal.z, 307; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w, 308; EG-NEXT: 150(2.101948e-43), 31(4.344025e-44) 309; EG-NEXT: 8388608(1.175494e-38), 8388607(1.175494e-38) 310; EG-NEXT: OR_INT T1.X, PS, literal.x, 311; EG-NEXT: LSHL T1.Y, PV.W, PV.Z, 312; EG-NEXT: AND_INT T0.Z, T2.W, literal.y, 313; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y, 314; EG-NEXT: AND_INT * T5.W, PV.Y, literal.y, 315; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44) 316; EG-NEXT: CNDE_INT T2.X, PS, PV.W, 0.0, 317; EG-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, 0.0, 318; EG-NEXT: ADD_INT T1.Z, T0.W, literal.x, 319; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X, 320; EG-NEXT: AND_INT * T5.W, T0.X, literal.y, 321; EG-NEXT: -150(nan), 32(4.484155e-44) 322; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0, 323; EG-NEXT: NOT_INT T2.Y, T2.W, 324; EG-NEXT: AND_INT T2.Z, PV.Z, literal.x, 325; EG-NEXT: NOT_INT T2.W, PV.Z, 326; EG-NEXT: LSHR * T4.W, T1.X, 1, 327; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 328; EG-NEXT: LSHR T3.X, T3.W, 1, 329; EG-NEXT: ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212 330; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W, 331; EG-NEXT: LSHL T0.W, T1.X, PV.Z, 332; EG-NEXT: AND_INT * T2.W, T1.Z, literal.y, 333; EG-NEXT: -127(nan), 32(4.484155e-44) 334; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0, 335; EG-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W, 336; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x, 337; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y, 338; EG-NEXT: ADD_INT * T1.W, T1.W, literal.y, 339; EG-NEXT: 23(3.222986e-44), -127(nan) 340; EG-NEXT: CNDE_INT T3.X, T0.Z, PV.W, T1.Y, 341; EG-NEXT: SETGT_INT T1.Y, PS, literal.x, 342; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y, 343; EG-NEXT: CNDE_INT T0.W, PV.Z, T0.X, PV.X, 344; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y, 345; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44) 346; EG-NEXT: XOR_INT T0.X, PV.W, PS, 347; EG-NEXT: XOR_INT T2.Y, PV.Z, PS, 348; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X, 349; EG-NEXT: CNDE_INT T0.W, PV.Y, T2.X, T0.Y, 350; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x, 351; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 352; EG-NEXT: XOR_INT T0.Y, PV.W, PS, 353; EG-NEXT: XOR_INT T0.Z, PV.Z, PS, 354; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W, 355; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W, 356; EG-NEXT: SUB_INT T1.Y, PV.W, PS, 357; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y, 358; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W, 359; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W, 360; EG-NEXT: SUB_INT T0.Z, PV.W, PS, 361; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W, 362; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0, 363; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0, 364; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W, 365; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0, 366; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W, 367; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0, 368; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 369; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 370 %conv = fptoui <2 x float> %x to <2 x i64> 371 store <2 x i64> %conv, <2 x i64> addrspace(1)* %out 372 ret void 373} 374 375define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) { 376; SI-LABEL: fp_to_uint_v4f32_to_v4i64: 377; SI: ; %bb.0: 378; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 379; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd 380; SI-NEXT: s_mov_b32 s7, 0xf000 381; SI-NEXT: s_mov_b32 s6, -1 382; SI-NEXT: s_mov_b32 s8, 0x2f800000 383; SI-NEXT: s_mov_b32 s9, 0xcf800000 384; SI-NEXT: s_waitcnt lgkmcnt(0) 385; SI-NEXT: v_trunc_f32_e32 v0, s1 386; SI-NEXT: v_trunc_f32_e32 v2, s0 387; SI-NEXT: v_trunc_f32_e32 v4, s3 388; SI-NEXT: v_trunc_f32_e32 v6, s2 389; SI-NEXT: v_mul_f32_e32 v1, s8, v0 390; SI-NEXT: v_mul_f32_e32 v3, s8, v2 391; SI-NEXT: v_mul_f32_e32 v5, s8, v4 392; SI-NEXT: v_mul_f32_e32 v7, s8, v6 393; SI-NEXT: v_floor_f32_e32 v8, v1 394; SI-NEXT: v_floor_f32_e32 v9, v3 395; SI-NEXT: v_floor_f32_e32 v10, v5 396; SI-NEXT: v_floor_f32_e32 v11, v7 397; SI-NEXT: v_cvt_u32_f32_e32 v3, v8 398; SI-NEXT: v_cvt_u32_f32_e32 v1, v9 399; SI-NEXT: v_fma_f32 v0, v8, s9, v0 400; SI-NEXT: v_fma_f32 v8, v9, s9, v2 401; SI-NEXT: v_cvt_u32_f32_e32 v7, v10 402; SI-NEXT: v_cvt_u32_f32_e32 v5, v11 403; SI-NEXT: v_fma_f32 v4, v10, s9, v4 404; SI-NEXT: v_fma_f32 v9, v11, s9, v6 405; SI-NEXT: v_cvt_u32_f32_e32 v2, v0 406; SI-NEXT: v_cvt_u32_f32_e32 v0, v8 407; SI-NEXT: v_cvt_u32_f32_e32 v6, v4 408; SI-NEXT: v_cvt_u32_f32_e32 v4, v9 409; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16 410; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 411; SI-NEXT: s_endpgm 412; 413; VI-LABEL: fp_to_uint_v4f32_to_v4i64: 414; VI: ; %bb.0: 415; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 416; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 417; VI-NEXT: s_mov_b32 s2, 0x2f800000 418; VI-NEXT: s_mov_b32 s3, 0xcf800000 419; VI-NEXT: s_waitcnt lgkmcnt(0) 420; VI-NEXT: v_trunc_f32_e32 v0, s5 421; VI-NEXT: v_trunc_f32_e32 v4, s4 422; VI-NEXT: v_mul_f32_e32 v1, s2, v0 423; VI-NEXT: v_mul_f32_e32 v2, s2, v4 424; VI-NEXT: v_floor_f32_e32 v5, v1 425; VI-NEXT: v_floor_f32_e32 v6, v2 426; VI-NEXT: v_fma_f32 v0, v5, s3, v0 427; VI-NEXT: v_cvt_u32_f32_e32 v2, v0 428; VI-NEXT: v_fma_f32 v0, v6, s3, v4 429; VI-NEXT: v_trunc_f32_e32 v4, s7 430; VI-NEXT: v_cvt_u32_f32_e32 v3, v5 431; VI-NEXT: v_mul_f32_e32 v5, s2, v4 432; VI-NEXT: v_trunc_f32_e32 v8, s6 433; VI-NEXT: v_cvt_u32_f32_e32 v1, v6 434; VI-NEXT: v_floor_f32_e32 v6, v5 435; VI-NEXT: v_mul_f32_e32 v5, s2, v8 436; VI-NEXT: v_floor_f32_e32 v9, v5 437; VI-NEXT: v_fma_f32 v4, v6, s3, v4 438; VI-NEXT: v_cvt_u32_f32_e32 v7, v6 439; VI-NEXT: v_cvt_u32_f32_e32 v6, v4 440; VI-NEXT: v_fma_f32 v4, v9, s3, v8 441; VI-NEXT: v_cvt_u32_f32_e32 v5, v9 442; VI-NEXT: v_cvt_u32_f32_e32 v4, v4 443; VI-NEXT: v_cvt_u32_f32_e32 v0, v0 444; VI-NEXT: s_mov_b32 s3, 0xf000 445; VI-NEXT: s_mov_b32 s2, -1 446; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 447; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 448; VI-NEXT: s_endpgm 449; 450; EG-LABEL: fp_to_uint_v4f32_to_v4i64: 451; EG: ; %bb.0: 452; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[] 453; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[] 454; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0 455; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1 456; EG-NEXT: CF_END 457; EG-NEXT: PAD 458; EG-NEXT: ALU clause starting at 6: 459; EG-NEXT: MOV * T0.W, literal.x, 460; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) 461; EG-NEXT: BFE_UINT T1.W, KC0[4].X, literal.x, PV.W, 462; EG-NEXT: AND_INT * T2.W, KC0[4].X, literal.y, 463; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38) 464; EG-NEXT: OR_INT T0.Z, PS, literal.x, 465; EG-NEXT: BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W, 466; EG-NEXT: ADD_INT * T3.W, PV.W, literal.z, 467; EG-NEXT: 8388608(1.175494e-38), 23(3.222986e-44) 468; EG-NEXT: -150(nan), 0(0.000000e+00) 469; EG-NEXT: ADD_INT T0.Y, PV.W, literal.x, 470; EG-NEXT: AND_INT T1.Z, PS, literal.y, 471; EG-NEXT: NOT_INT T4.W, PS, 472; EG-NEXT: LSHR * T5.W, PV.Z, 1, 473; EG-NEXT: -127(nan), 31(4.344025e-44) 474; EG-NEXT: ADD_INT T0.X, T1.W, literal.x, 475; EG-NEXT: BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W, 476; EG-NEXT: AND_INT T2.Z, T3.W, literal.y, BS:VEC_201 477; EG-NEXT: LSHL T3.W, T0.Z, PV.Z, 478; EG-NEXT: SUB_INT * T1.W, literal.z, T1.W, 479; EG-NEXT: -127(nan), 32(4.484155e-44) 480; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00) 481; EG-NEXT: AND_INT T1.X, PS, literal.x, 482; EG-NEXT: BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS, 483; EG-NEXT: AND_INT T0.Z, KC0[3].Z, literal.y, 484; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.Y, PV.W, 485; EG-NEXT: SETGT_INT * T4.W, PV.X, literal.z, 486; EG-NEXT: 32(4.484155e-44), 8388607(1.175494e-38) 487; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00) 488; EG-NEXT: CNDE_INT T2.X, PS, 0.0, PV.W, 489; EG-NEXT: OR_INT T1.Y, PV.Z, literal.x, 490; EG-NEXT: ADD_INT T0.Z, T2.W, literal.y, 491; EG-NEXT: CNDE_INT T1.W, PV.X, PV.Y, 0.0, 492; EG-NEXT: CNDE_INT * T3.W, T2.Z, T3.W, 0.0, 493; EG-NEXT: 8388608(1.175494e-38), -150(nan) 494; EG-NEXT: CNDE_INT T1.X, T4.W, PV.W, PS, 495; EG-NEXT: ASHR T2.Y, KC0[4].X, literal.x, 496; EG-NEXT: AND_INT T1.Z, PV.Z, literal.x, 497; EG-NEXT: NOT_INT T1.W, PV.Z, 498; EG-NEXT: LSHR * T3.W, PV.Y, 1, 499; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 500; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W, 501; EG-NEXT: LSHL T3.Y, T1.Y, PV.Z, 502; EG-NEXT: XOR_INT T1.Z, PV.X, PV.Y, 503; EG-NEXT: XOR_INT T1.W, T2.X, PV.Y, 504; EG-NEXT: SUB_INT * T2.W, literal.x, T2.W, 505; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00) 506; EG-NEXT: AND_INT T1.X, T0.Z, literal.x, 507; EG-NEXT: AND_INT T4.Y, PS, literal.x, 508; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122 509; EG-NEXT: SUB_INT T1.W, PV.W, T2.Y, 510; EG-NEXT: SUBB_UINT * T2.W, PV.Z, T2.Y, 511; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 512; EG-NEXT: SUB_INT T2.X, PV.W, PS, 513; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.Z, 0.0, 514; EG-NEXT: CNDE_INT T0.Z, PV.X, T3.Y, 0.0, 515; EG-NEXT: CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122 516; EG-NEXT: SETGT_INT * T2.W, T0.Y, literal.x, 517; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00) 518; EG-NEXT: BFE_UINT T1.X, KC0[3].W, literal.x, T0.W, 519; EG-NEXT: AND_INT T3.Y, KC0[3].W, literal.y, 520; EG-NEXT: CNDE_INT T2.Z, PS, 0.0, PV.W, 521; EG-NEXT: CNDE_INT T1.W, PS, PV.Y, PV.Z, 522; EG-NEXT: ASHR * T2.W, KC0[3].Z, literal.z, 523; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38) 524; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 525; EG-NEXT: BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W, 526; EG-NEXT: XOR_INT T1.Y, PV.W, PS, 527; EG-NEXT: XOR_INT T0.Z, PV.Z, PS, 528; EG-NEXT: OR_INT T0.W, PV.Y, literal.y, 529; EG-NEXT: SUB_INT * T1.W, literal.z, PV.X, 530; EG-NEXT: 23(3.222986e-44), 8388608(1.175494e-38) 531; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00) 532; EG-NEXT: AND_INT T4.X, KC0[3].Y, literal.x, 533; EG-NEXT: AND_INT T3.Y, PS, literal.y, 534; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS, 535; EG-NEXT: SUB_INT T1.W, PV.Z, T2.W, 536; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W, 537; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44) 538; EG-NEXT: SUB_INT T5.X, PV.W, PS, 539; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y, 540; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0, 541; EG-NEXT: OR_INT T1.W, PV.X, literal.x, 542; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y, 543; EG-NEXT: 8388608(1.175494e-38), -150(nan) 544; EG-NEXT: ADD_INT T4.X, T3.X, literal.x, 545; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X, 546; EG-NEXT: AND_INT T2.Z, PS, literal.z, 547; EG-NEXT: NOT_INT T4.W, PS, 548; EG-NEXT: LSHR * T5.W, PV.W, 1, 549; EG-NEXT: -127(nan), 150(2.101948e-43) 550; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 551; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W, 552; EG-NEXT: LSHL T4.Y, T1.W, PV.Z, 553; EG-NEXT: AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212 554; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122 555; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x, 556; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 557; EG-NEXT: ADD_INT T6.X, T1.X, literal.x, 558; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0, 559; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0, 560; EG-NEXT: -150(nan), 0(0.000000e+00) 561; EG-NEXT: ALU clause starting at 108: 562; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y, 563; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x, 564; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00) 565; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W, 566; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z, 567; EG-NEXT: AND_INT T2.Z, T6.X, literal.x, 568; EG-NEXT: NOT_INT T1.W, T6.X, 569; EG-NEXT: LSHR * T3.W, T0.W, 1, 570; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 571; EG-NEXT: ASHR T7.X, KC0[3].Y, literal.x, 572; EG-NEXT: ADD_INT T4.Y, T1.X, literal.y, 573; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W, 574; EG-NEXT: LSHL T0.W, T0.W, PV.Z, 575; EG-NEXT: AND_INT * T1.W, T6.X, literal.z, 576; EG-NEXT: 31(4.344025e-44), -127(nan) 577; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 578; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0, 579; EG-NEXT: CNDE_INT T5.Y, PS, PV.Z, PV.W, 580; EG-NEXT: SETGT_INT T2.Z, PV.Y, literal.x, 581; EG-NEXT: XOR_INT T0.W, T3.Y, PV.X, 582; EG-NEXT: XOR_INT * T1.W, T3.X, PV.X, 583; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00) 584; EG-NEXT: SUB_INT T3.X, PS, T7.X, 585; EG-NEXT: SUBB_UINT T3.Y, PV.W, T7.X, 586; EG-NEXT: CNDE_INT T3.Z, PV.Z, 0.0, PV.Y, 587; EG-NEXT: CNDE_INT T1.W, PV.Z, T0.Z, PV.X, 588; EG-NEXT: ASHR * T3.W, KC0[3].W, literal.x, 589; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 590; EG-NEXT: XOR_INT T1.X, PV.W, PS, 591; EG-NEXT: XOR_INT T5.Y, PV.Z, PS, 592; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y, 593; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122 594; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0, 595; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X, 596; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0, 597; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122 598; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W, 599; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W, 600; EG-NEXT: SUB_INT T3.X, PV.W, PS, 601; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y, 602; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0, 603; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122 604; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0, 605; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0, 606; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0, 607; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y, 608; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x, 609; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 610; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0, 611; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212 612; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0, 613; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, 614; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 615; EG-NEXT: LSHR * T0.X, PV.W, literal.x, 616; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 617 %conv = fptoui <4 x float> %x to <4 x i64> 618 store <4 x i64> %conv, <4 x i64> addrspace(1)* %out 619 ret void 620} 621 622define amdgpu_kernel void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 { 623; SI-LABEL: fp_to_uint_f32_to_i1: 624; SI: ; %bb.0: 625; SI-NEXT: s_load_dword s4, s[0:1], 0xb 626; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 627; SI-NEXT: s_mov_b32 s3, 0xf000 628; SI-NEXT: s_mov_b32 s2, -1 629; SI-NEXT: s_waitcnt lgkmcnt(0) 630; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, s4 631; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 632; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 633; SI-NEXT: s_endpgm 634; 635; VI-LABEL: fp_to_uint_f32_to_i1: 636; VI: ; %bb.0: 637; VI-NEXT: s_load_dword s4, s[0:1], 0x2c 638; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 639; VI-NEXT: s_mov_b32 s3, 0xf000 640; VI-NEXT: s_mov_b32 s2, -1 641; VI-NEXT: s_waitcnt lgkmcnt(0) 642; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, s4 643; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 644; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0 645; VI-NEXT: s_endpgm 646; 647; EG-LABEL: fp_to_uint_f32_to_i1: 648; EG: ; %bb.0: 649; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] 650; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 651; EG-NEXT: CF_END 652; EG-NEXT: PAD 653; EG-NEXT: ALU clause starting at 4: 654; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x, 655; EG-NEXT: SETE_DX10 * T1.W, KC0[2].Z, 1.0, 656; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 657; EG-NEXT: AND_INT T1.W, PS, 1, 658; EG-NEXT: LSHL * T0.W, PV.W, literal.x, 659; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 660; EG-NEXT: LSHL T0.X, PV.W, PS, 661; EG-NEXT: LSHL * T0.W, literal.x, PS, 662; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) 663; EG-NEXT: MOV T0.Y, 0.0, 664; EG-NEXT: MOV * T0.Z, 0.0, 665; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 666; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 667 %conv = fptoui float %in to i1 668 store i1 %conv, i1 addrspace(1)* %out 669 ret void 670} 671 672define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 { 673; SI-LABEL: fp_to_uint_fabs_f32_to_i1: 674; SI: ; %bb.0: 675; SI-NEXT: s_load_dword s4, s[0:1], 0xb 676; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 677; SI-NEXT: s_mov_b32 s3, 0xf000 678; SI-NEXT: s_mov_b32 s2, -1 679; SI-NEXT: s_waitcnt lgkmcnt(0) 680; SI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, |s4| 681; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 682; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 683; SI-NEXT: s_endpgm 684; 685; VI-LABEL: fp_to_uint_fabs_f32_to_i1: 686; VI: ; %bb.0: 687; VI-NEXT: s_load_dword s4, s[0:1], 0x2c 688; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 689; VI-NEXT: s_mov_b32 s3, 0xf000 690; VI-NEXT: s_mov_b32 s2, -1 691; VI-NEXT: s_waitcnt lgkmcnt(0) 692; VI-NEXT: v_cmp_eq_f32_e64 s[4:5], 1.0, |s4| 693; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] 694; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0 695; VI-NEXT: s_endpgm 696; 697; EG-LABEL: fp_to_uint_fabs_f32_to_i1: 698; EG: ; %bb.0: 699; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] 700; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 701; EG-NEXT: CF_END 702; EG-NEXT: PAD 703; EG-NEXT: ALU clause starting at 4: 704; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x, 705; EG-NEXT: SETE_DX10 * T1.W, |KC0[2].Z|, 1.0, 706; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 707; EG-NEXT: AND_INT T1.W, PS, 1, 708; EG-NEXT: LSHL * T0.W, PV.W, literal.x, 709; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 710; EG-NEXT: LSHL T0.X, PV.W, PS, 711; EG-NEXT: LSHL * T0.W, literal.x, PS, 712; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) 713; EG-NEXT: MOV T0.Y, 0.0, 714; EG-NEXT: MOV * T0.Z, 0.0, 715; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 716; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 717 %in.fabs = call float @llvm.fabs.f32(float %in) 718 %conv = fptoui float %in.fabs to i1 719 store i1 %conv, i1 addrspace(1)* %out 720 ret void 721} 722 723define amdgpu_kernel void @fp_to_uint_f32_to_i16(i16 addrspace(1)* %out, float %in) #0 { 724; SI-LABEL: fp_to_uint_f32_to_i16: 725; SI: ; %bb.0: 726; SI-NEXT: s_load_dword s4, s[0:1], 0xb 727; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 728; SI-NEXT: s_mov_b32 s3, 0xf000 729; SI-NEXT: s_mov_b32 s2, -1 730; SI-NEXT: s_waitcnt lgkmcnt(0) 731; SI-NEXT: v_cvt_u32_f32_e32 v0, s4 732; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 733; SI-NEXT: s_endpgm 734; 735; VI-LABEL: fp_to_uint_f32_to_i16: 736; VI: ; %bb.0: 737; VI-NEXT: s_load_dword s2, s[0:1], 0x2c 738; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 739; VI-NEXT: s_mov_b32 s3, 0xf000 740; VI-NEXT: s_waitcnt lgkmcnt(0) 741; VI-NEXT: v_cvt_u32_f32_e32 v0, s2 742; VI-NEXT: s_mov_b32 s2, -1 743; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 744; VI-NEXT: s_endpgm 745; 746; EG-LABEL: fp_to_uint_f32_to_i16: 747; EG: ; %bb.0: 748; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] 749; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 750; EG-NEXT: CF_END 751; EG-NEXT: PAD 752; EG-NEXT: ALU clause starting at 4: 753; EG-NEXT: TRUNC T0.W, KC0[2].Z, 754; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x, 755; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 756; EG-NEXT: LSHL T1.W, PS, literal.x, 757; EG-NEXT: FLT_TO_UINT * T0.X, PV.W, 758; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 759; EG-NEXT: LSHL T0.X, PS, PV.W, 760; EG-NEXT: LSHL * T0.W, literal.x, PV.W, 761; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 762; EG-NEXT: MOV T0.Y, 0.0, 763; EG-NEXT: MOV * T0.Z, 0.0, 764; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 765; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 766 %uint = fptoui float %in to i16 767 store i16 %uint, i16 addrspace(1)* %out 768 ret void 769} 770 771attributes #0 = { nounwind } 772attributes #1 = { nounwind readnone } 773