1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
3; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI
4; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck  %s -check-prefixes=EG
5
6declare float @llvm.fabs.f32(float) #1
7
8define amdgpu_kernel void @fp_to_uint_f32_to_i32 (i32 addrspace(1)* %out, float %in) {
9; SI-LABEL: fp_to_uint_f32_to_i32:
10; SI:       ; %bb.0:
11; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
12; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
13; SI-NEXT:    s_mov_b32 s3, 0xf000
14; SI-NEXT:    s_mov_b32 s2, -1
15; SI-NEXT:    s_waitcnt lgkmcnt(0)
16; SI-NEXT:    v_cvt_u32_f32_e32 v0, s4
17; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
18; SI-NEXT:    s_endpgm
19;
20; VI-LABEL: fp_to_uint_f32_to_i32:
21; VI:       ; %bb.0:
22; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
23; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
24; VI-NEXT:    s_mov_b32 s3, 0xf000
25; VI-NEXT:    s_waitcnt lgkmcnt(0)
26; VI-NEXT:    v_cvt_u32_f32_e32 v0, s2
27; VI-NEXT:    s_mov_b32 s2, -1
28; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
29; VI-NEXT:    s_endpgm
30;
31; EG-LABEL: fp_to_uint_f32_to_i32:
32; EG:       ; %bb.0:
33; EG-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
34; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
35; EG-NEXT:    CF_END
36; EG-NEXT:    PAD
37; EG-NEXT:    ALU clause starting at 4:
38; EG-NEXT:     TRUNC * T0.W, KC0[2].Z,
39; EG-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
40; EG-NEXT:     FLT_TO_UINT * T1.X, PV.W,
41; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
42  %conv = fptoui float %in to i32
43  store i32 %conv, i32 addrspace(1)* %out
44  ret void
45}
46
47define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
48; SI-LABEL: fp_to_uint_v2f32_to_v2i32:
49; SI:       ; %bb.0:
50; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
51; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
52; SI-NEXT:    s_mov_b32 s3, 0xf000
53; SI-NEXT:    s_mov_b32 s2, -1
54; SI-NEXT:    s_waitcnt lgkmcnt(0)
55; SI-NEXT:    v_cvt_u32_f32_e32 v1, s5
56; SI-NEXT:    v_cvt_u32_f32_e32 v0, s4
57; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
58; SI-NEXT:    s_endpgm
59;
60; VI-LABEL: fp_to_uint_v2f32_to_v2i32:
61; VI:       ; %bb.0:
62; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
63; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
64; VI-NEXT:    s_waitcnt lgkmcnt(0)
65; VI-NEXT:    v_cvt_u32_f32_e32 v1, s3
66; VI-NEXT:    v_cvt_u32_f32_e32 v0, s2
67; VI-NEXT:    s_mov_b32 s3, 0xf000
68; VI-NEXT:    s_mov_b32 s2, -1
69; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
70; VI-NEXT:    s_endpgm
71;
72; EG-LABEL: fp_to_uint_v2f32_to_v2i32:
73; EG:       ; %bb.0:
74; EG-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
75; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
76; EG-NEXT:    CF_END
77; EG-NEXT:    PAD
78; EG-NEXT:    ALU clause starting at 4:
79; EG-NEXT:     TRUNC T0.W, KC0[3].X,
80; EG-NEXT:     TRUNC * T1.W, KC0[2].W,
81; EG-NEXT:     FLT_TO_UINT * T0.Y, PV.W,
82; EG-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
83; EG-NEXT:     FLT_TO_UINT * T0.X, T1.W,
84; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
85  %result = fptoui <2 x float> %in to <2 x i32>
86  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
87  ret void
88}
89
90define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
91; SI-LABEL: fp_to_uint_v4f32_to_v4i32:
92; SI:       ; %bb.0:
93; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
94; SI-NEXT:    s_waitcnt lgkmcnt(0)
95; SI-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
96; SI-NEXT:    s_mov_b32 s3, 0xf000
97; SI-NEXT:    s_mov_b32 s2, -1
98; SI-NEXT:    s_waitcnt lgkmcnt(0)
99; SI-NEXT:    v_cvt_u32_f32_e32 v3, s7
100; SI-NEXT:    v_cvt_u32_f32_e32 v2, s6
101; SI-NEXT:    v_cvt_u32_f32_e32 v1, s5
102; SI-NEXT:    v_cvt_u32_f32_e32 v0, s4
103; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
104; SI-NEXT:    s_endpgm
105;
106; VI-LABEL: fp_to_uint_v4f32_to_v4i32:
107; VI:       ; %bb.0:
108; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
109; VI-NEXT:    s_waitcnt lgkmcnt(0)
110; VI-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
111; VI-NEXT:    s_mov_b32 s3, 0xf000
112; VI-NEXT:    s_mov_b32 s2, -1
113; VI-NEXT:    s_waitcnt lgkmcnt(0)
114; VI-NEXT:    v_cvt_u32_f32_e32 v3, s7
115; VI-NEXT:    v_cvt_u32_f32_e32 v2, s6
116; VI-NEXT:    v_cvt_u32_f32_e32 v1, s5
117; VI-NEXT:    v_cvt_u32_f32_e32 v0, s4
118; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
119; VI-NEXT:    s_endpgm
120;
121; EG-LABEL: fp_to_uint_v4f32_to_v4i32:
122; EG:       ; %bb.0:
123; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
124; EG-NEXT:    TEX 0 @6
125; EG-NEXT:    ALU 9, @9, KC0[CB0:0-32], KC1[]
126; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
127; EG-NEXT:    CF_END
128; EG-NEXT:    PAD
129; EG-NEXT:    Fetch clause starting at 6:
130; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
131; EG-NEXT:    ALU clause starting at 8:
132; EG-NEXT:     MOV * T0.X, KC0[2].Z,
133; EG-NEXT:    ALU clause starting at 9:
134; EG-NEXT:     TRUNC T0.W, T0.W,
135; EG-NEXT:     TRUNC * T1.W, T0.Z,
136; EG-NEXT:     FLT_TO_UINT * T0.W, PV.W,
137; EG-NEXT:     TRUNC T2.W, T0.Y,
138; EG-NEXT:     FLT_TO_UINT * T0.Z, T1.W,
139; EG-NEXT:     TRUNC T1.W, T0.X,
140; EG-NEXT:     FLT_TO_UINT * T0.Y, PV.W,
141; EG-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
142; EG-NEXT:     FLT_TO_UINT * T0.X, PV.W,
143; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
144  %value = load <4 x float>, <4 x float> addrspace(1) * %in
145  %result = fptoui <4 x float> %value to <4 x i32>
146  store <4 x i32> %result, <4 x i32> addrspace(1)* %out
147  ret void
148}
149
150define amdgpu_kernel void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %x) {
151; SI-LABEL: fp_to_uint_f32_to_i64:
152; SI:       ; %bb.0:
153; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
154; SI-NEXT:    s_load_dword s8, s[0:1], 0xb
155; SI-NEXT:    s_mov_b32 s7, 0xf000
156; SI-NEXT:    s_mov_b32 s6, -1
157; SI-NEXT:    s_movk_i32 s9, 0xff6a
158; SI-NEXT:    s_mov_b32 s2, 0x7fffff
159; SI-NEXT:    s_mov_b32 s10, 0x800000
160; SI-NEXT:    s_mov_b32 s1, 0
161; SI-NEXT:    s_movk_i32 s11, 0x96
162; SI-NEXT:    s_movk_i32 s12, 0xff81
163; SI-NEXT:    v_mov_b32_e32 v4, 0x5f000000
164; SI-NEXT:    v_mov_b32_e32 v1, 0
165; SI-NEXT:    s_waitcnt lgkmcnt(0)
166; SI-NEXT:    s_bfe_u32 s3, s8, 0x80017
167; SI-NEXT:    s_and_b32 s0, s8, s2
168; SI-NEXT:    s_ashr_i32 s13, s8, 31
169; SI-NEXT:    v_sub_f32_e32 v0, s8, v4
170; SI-NEXT:    s_add_i32 s14, s3, s9
171; SI-NEXT:    s_or_b32 s0, s0, s10
172; SI-NEXT:    s_sub_i32 s15, s11, s3
173; SI-NEXT:    s_add_i32 s16, s3, s12
174; SI-NEXT:    s_ashr_i32 s17, s13, 31
175; SI-NEXT:    v_bfe_u32 v2, v0, 23, 8
176; SI-NEXT:    v_and_b32_e32 v3, s2, v0
177; SI-NEXT:    v_ashrrev_i32_e32 v5, 31, v0
178; SI-NEXT:    s_lshl_b64 s[2:3], s[0:1], s14
179; SI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s15
180; SI-NEXT:    v_mov_b32_e32 v6, s17
181; SI-NEXT:    v_add_i32_e32 v7, vcc, s9, v2
182; SI-NEXT:    v_or_b32_e32 v0, s10, v3
183; SI-NEXT:    v_sub_i32_e32 v8, vcc, s11, v2
184; SI-NEXT:    v_add_i32_e32 v9, vcc, s12, v2
185; SI-NEXT:    v_ashrrev_i32_e32 v10, 31, v5
186; SI-NEXT:    v_mov_b32_e32 v2, s1
187; SI-NEXT:    v_mov_b32_e32 v3, s3
188; SI-NEXT:    v_cmp_gt_i32_e64 vcc, s16, 23
189; SI-NEXT:    v_cndmask_b32_e32 v11, v2, v3, vcc
190; SI-NEXT:    v_mov_b32_e32 v12, s0
191; SI-NEXT:    v_mov_b32_e32 v13, s2
192; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], v7
193; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], v8
194; SI-NEXT:    v_cndmask_b32_e32 v7, v12, v13, vcc
195; SI-NEXT:    v_xor_b32_e32 v8, s17, v11
196; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v9
197; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
198; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
199; SI-NEXT:    v_xor_b32_e32 v2, s13, v7
200; SI-NEXT:    v_xor_b32_e32 v0, v0, v5
201; SI-NEXT:    v_xor_b32_e32 v1, v1, v10
202; SI-NEXT:    v_subrev_i32_e32 v2, vcc, s13, v2
203; SI-NEXT:    v_subb_u32_e32 v3, vcc, v8, v6, vcc
204; SI-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
205; SI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v10, vcc
206; SI-NEXT:    v_cmp_lt_i32_e64 s[0:1], s16, 0
207; SI-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s[0:1]
208; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v9
209; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
210; SI-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s[0:1]
211; SI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
212; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s8, v4
213; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
214; SI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
215; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
216; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
217; SI-NEXT:    s_endpgm
218;
219; VI-LABEL: fp_to_uint_f32_to_i64:
220; VI:       ; %bb.0:
221; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
222; VI-NEXT:    s_load_dword s9, s[0:1], 0x2c
223; VI-NEXT:    s_mov_b32 s11, 0x7fffff
224; VI-NEXT:    s_movk_i32 s8, 0xff6a
225; VI-NEXT:    s_mov_b32 s12, 0x800000
226; VI-NEXT:    s_movk_i32 s13, 0x96
227; VI-NEXT:    s_waitcnt lgkmcnt(0)
228; VI-NEXT:    s_bfe_u32 s10, s9, 0x80017
229; VI-NEXT:    s_and_b32 s0, s9, s11
230; VI-NEXT:    s_add_i32 s2, s10, s8
231; VI-NEXT:    s_or_b32 s0, s0, s12
232; VI-NEXT:    s_mov_b32 s1, 0
233; VI-NEXT:    s_sub_i32 s14, s13, s10
234; VI-NEXT:    s_lshl_b64 s[2:3], s[0:1], s2
235; VI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s14
236; VI-NEXT:    s_movk_i32 s14, 0xff81
237; VI-NEXT:    s_add_i32 s10, s10, s14
238; VI-NEXT:    v_mov_b32_e32 v0, s1
239; VI-NEXT:    v_mov_b32_e32 v1, s3
240; VI-NEXT:    v_cmp_gt_i32_e64 vcc, s10, 23
241; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
242; VI-NEXT:    v_mov_b32_e32 v1, s0
243; VI-NEXT:    v_mov_b32_e32 v2, s2
244; VI-NEXT:    s_ashr_i32 s0, s9, 31
245; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
246; VI-NEXT:    s_ashr_i32 s1, s0, 31
247; VI-NEXT:    v_xor_b32_e32 v1, s0, v1
248; VI-NEXT:    v_mov_b32_e32 v6, 0x5f000000
249; VI-NEXT:    v_sub_f32_e32 v7, s9, v6
250; VI-NEXT:    v_xor_b32_e32 v0, s1, v0
251; VI-NEXT:    v_mov_b32_e32 v2, s1
252; VI-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1
253; VI-NEXT:    v_subb_u32_e32 v4, vcc, v0, v2, vcc
254; VI-NEXT:    v_bfe_u32 v8, v7, 23, 8
255; VI-NEXT:    v_and_b32_e32 v0, s11, v7
256; VI-NEXT:    v_cmp_lt_i32_e64 s[2:3], s10, 0
257; VI-NEXT:    v_cndmask_b32_e64 v5, v1, 0, s[2:3]
258; VI-NEXT:    v_add_u32_e32 v2, vcc, s8, v8
259; VI-NEXT:    v_sub_u32_e32 v9, vcc, s13, v8
260; VI-NEXT:    v_or_b32_e32 v0, s12, v0
261; VI-NEXT:    v_mov_b32_e32 v1, 0
262; VI-NEXT:    v_add_u32_e32 v8, vcc, s14, v8
263; VI-NEXT:    v_lshlrev_b64 v[2:3], v2, v[0:1]
264; VI-NEXT:    v_lshrrev_b64 v[0:1], v9, v[0:1]
265; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v8
266; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
267; VI-NEXT:    v_ashrrev_i32_e32 v2, 31, v7
268; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
269; VI-NEXT:    v_xor_b32_e32 v0, v0, v2
270; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
271; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v2
272; VI-NEXT:    v_xor_b32_e32 v1, v1, v3
273; VI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
274; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v8
275; VI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
276; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
277; VI-NEXT:    v_cmp_lt_f32_e64 s[0:1], s9, v6
278; VI-NEXT:    v_cndmask_b32_e64 v2, v4, 0, s[2:3]
279; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v1
280; VI-NEXT:    s_mov_b32 s7, 0xf000
281; VI-NEXT:    s_mov_b32 s6, -1
282; VI-NEXT:    v_cndmask_b32_e64 v0, v0, v5, s[0:1]
283; VI-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
284; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
285; VI-NEXT:    s_endpgm
286;
287; EG-LABEL: fp_to_uint_f32_to_i64:
288; EG:       ; %bb.0:
289; EG-NEXT:    ALU 41, @4, KC0[CB0:0-32], KC1[]
290; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
291; EG-NEXT:    CF_END
292; EG-NEXT:    PAD
293; EG-NEXT:    ALU clause starting at 4:
294; EG-NEXT:     MOV * T0.W, literal.x,
295; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
296; EG-NEXT:     BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,
297; EG-NEXT:     AND_INT * T1.W, KC0[2].Z, literal.y,
298; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
299; EG-NEXT:     OR_INT T1.W, PS, literal.x,
300; EG-NEXT:     ADD_INT * T2.W, PV.W, literal.y,
301; EG-NEXT:    8388608(1.175494e-38), -150(nan)
302; EG-NEXT:     ADD_INT T0.X, T0.W, literal.x,
303; EG-NEXT:     SUB_INT T0.Y, literal.y, T0.W,
304; EG-NEXT:     AND_INT T0.Z, PS, literal.z,
305; EG-NEXT:     NOT_INT T0.W, PS,
306; EG-NEXT:     LSHR * T3.W, PV.W, 1,
307; EG-NEXT:    -127(nan), 150(2.101948e-43)
308; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
309; EG-NEXT:     BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
310; EG-NEXT:     LSHL T1.Y, T1.W, PV.Z,
311; EG-NEXT:     AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
312; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
313; EG-NEXT:     AND_INT * T1.W, PV.Y, literal.x,
314; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
315; EG-NEXT:     CNDE_INT T0.Y, PS, PV.W, 0.0,
316; EG-NEXT:     CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
317; EG-NEXT:     CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
318; EG-NEXT:     SETGT_INT * T1.W, T0.X, literal.x,
319; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
320; EG-NEXT:     CNDE_INT T0.Z, PS, 0.0, PV.W,
321; EG-NEXT:     CNDE_INT T0.W, PS, PV.Y, PV.Z,
322; EG-NEXT:     ASHR * T1.W, KC0[2].Z, literal.x,
323; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
324; EG-NEXT:     XOR_INT T0.W, PV.W, PS,
325; EG-NEXT:     XOR_INT * T2.W, PV.Z, PS,
326; EG-NEXT:     SUB_INT T2.W, PS, T1.W,
327; EG-NEXT:     SUBB_UINT * T3.W, PV.W, T1.W,
328; EG-NEXT:     SUB_INT T2.W, PV.W, PS,
329; EG-NEXT:     SETGT_INT * T3.W, T0.X, literal.x,
330; EG-NEXT:    -1(nan), 0(0.000000e+00)
331; EG-NEXT:     CNDE_INT T0.Y, PS, 0.0, PV.W,
332; EG-NEXT:     SUB_INT * T0.W, T0.W, T1.W,
333; EG-NEXT:     CNDE_INT T0.X, T3.W, 0.0, PV.W,
334; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
335; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
336  %conv = fptoui float %x to i64
337  store i64 %conv, i64 addrspace(1)* %out
338  ret void
339}
340
341define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
342; SI-LABEL: fp_to_uint_v2f32_to_v2i64:
343; SI:       ; %bb.0:
344; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
345; SI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
346; SI-NEXT:    s_mov_b32 s7, 0xf000
347; SI-NEXT:    s_mov_b32 s6, -1
348; SI-NEXT:    s_movk_i32 s12, 0xff6a
349; SI-NEXT:    s_mov_b32 s8, 0x7fffff
350; SI-NEXT:    s_mov_b32 s13, 0x800000
351; SI-NEXT:    s_mov_b32 s1, 0
352; SI-NEXT:    s_movk_i32 s14, 0x96
353; SI-NEXT:    s_movk_i32 s15, 0xff81
354; SI-NEXT:    v_mov_b32_e32 v6, 0x5f000000
355; SI-NEXT:    v_mov_b32_e32 v1, 0
356; SI-NEXT:    s_brev_b32 s16, 1
357; SI-NEXT:    s_waitcnt lgkmcnt(0)
358; SI-NEXT:    s_bfe_u32 s9, s3, 0x80017
359; SI-NEXT:    s_and_b32 s0, s3, s8
360; SI-NEXT:    s_ashr_i32 s17, s3, 31
361; SI-NEXT:    v_sub_f32_e32 v0, s3, v6
362; SI-NEXT:    s_bfe_u32 s10, s2, 0x80017
363; SI-NEXT:    s_and_b32 s18, s2, s8
364; SI-NEXT:    s_ashr_i32 s19, s2, 31
365; SI-NEXT:    v_sub_f32_e32 v2, s2, v6
366; SI-NEXT:    s_add_i32 s11, s9, s12
367; SI-NEXT:    s_or_b32 s0, s0, s13
368; SI-NEXT:    s_sub_i32 s20, s14, s9
369; SI-NEXT:    s_add_i32 s21, s9, s15
370; SI-NEXT:    s_ashr_i32 s22, s17, 31
371; SI-NEXT:    v_bfe_u32 v3, v0, 23, 8
372; SI-NEXT:    v_and_b32_e32 v4, s8, v0
373; SI-NEXT:    v_ashrrev_i32_e32 v7, 31, v0
374; SI-NEXT:    s_add_i32 s23, s10, s12
375; SI-NEXT:    s_sub_i32 s24, s14, s10
376; SI-NEXT:    s_add_i32 s25, s10, s15
377; SI-NEXT:    s_ashr_i32 s26, s19, 31
378; SI-NEXT:    v_bfe_u32 v5, v2, 23, 8
379; SI-NEXT:    v_and_b32_e32 v8, s8, v2
380; SI-NEXT:    v_ashrrev_i32_e32 v9, 31, v2
381; SI-NEXT:    s_lshl_b64 s[8:9], s[0:1], s11
382; SI-NEXT:    s_lshr_b64 s[10:11], s[0:1], s20
383; SI-NEXT:    v_mov_b32_e32 v10, s22
384; SI-NEXT:    v_add_i32_e32 v2, vcc, s12, v3
385; SI-NEXT:    v_or_b32_e32 v0, s13, v4
386; SI-NEXT:    v_sub_i32_e32 v4, vcc, s14, v3
387; SI-NEXT:    v_add_i32_e32 v11, vcc, s15, v3
388; SI-NEXT:    v_ashrrev_i32_e32 v12, 31, v7
389; SI-NEXT:    s_or_b32 s0, s18, s13
390; SI-NEXT:    v_mov_b32_e32 v13, s26
391; SI-NEXT:    v_add_i32_e32 v14, vcc, s12, v5
392; SI-NEXT:    v_sub_i32_e32 v15, vcc, s14, v5
393; SI-NEXT:    v_add_i32_e32 v16, vcc, s15, v5
394; SI-NEXT:    v_ashrrev_i32_e32 v17, 31, v9
395; SI-NEXT:    v_mov_b32_e32 v3, s11
396; SI-NEXT:    v_mov_b32_e32 v5, s9
397; SI-NEXT:    v_cmp_gt_i32_e64 vcc, s21, 23
398; SI-NEXT:    v_cndmask_b32_e32 v18, v3, v5, vcc
399; SI-NEXT:    v_mov_b32_e32 v19, s10
400; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
401; SI-NEXT:    v_lshr_b64 v[4:5], v[0:1], v4
402; SI-NEXT:    v_or_b32_e32 v0, s13, v8
403; SI-NEXT:    v_mov_b32_e32 v8, s8
404; SI-NEXT:    s_lshl_b64 s[8:9], s[0:1], s23
405; SI-NEXT:    s_lshr_b64 s[0:1], s[0:1], s24
406; SI-NEXT:    v_cndmask_b32_e32 v8, v19, v8, vcc
407; SI-NEXT:    v_xor_b32_e32 v18, s22, v18
408; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v11
409; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v3, vcc
410; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v2, vcc
411; SI-NEXT:    v_mov_b32_e32 v2, s1
412; SI-NEXT:    v_mov_b32_e32 v3, s9
413; SI-NEXT:    v_cmp_gt_i32_e64 vcc, s25, 23
414; SI-NEXT:    v_cndmask_b32_e32 v19, v2, v3, vcc
415; SI-NEXT:    v_mov_b32_e32 v20, s0
416; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], v14
417; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], v15
418; SI-NEXT:    v_mov_b32_e32 v14, s8
419; SI-NEXT:    v_xor_b32_e32 v8, s17, v8
420; SI-NEXT:    v_xor_b32_e32 v4, v4, v7
421; SI-NEXT:    v_xor_b32_e32 v5, v5, v12
422; SI-NEXT:    v_cndmask_b32_e32 v14, v20, v14, vcc
423; SI-NEXT:    v_xor_b32_e32 v15, s26, v19
424; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v16
425; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
426; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
427; SI-NEXT:    v_subrev_i32_e32 v2, vcc, s17, v8
428; SI-NEXT:    v_subb_u32_e32 v3, vcc, v18, v10, vcc
429; SI-NEXT:    v_sub_i32_e32 v4, vcc, v4, v7
430; SI-NEXT:    v_subb_u32_e32 v5, vcc, v5, v12, vcc
431; SI-NEXT:    v_xor_b32_e32 v7, s19, v14
432; SI-NEXT:    v_xor_b32_e32 v0, v0, v9
433; SI-NEXT:    v_xor_b32_e32 v1, v1, v17
434; SI-NEXT:    v_cmp_lt_i32_e64 s[8:9], s21, 0
435; SI-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s[8:9]
436; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v11
437; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
438; SI-NEXT:    v_subrev_i32_e64 v7, s[0:1], s19, v7
439; SI-NEXT:    v_subb_u32_e64 v8, s[0:1], v15, v13, s[0:1]
440; SI-NEXT:    v_sub_i32_e64 v0, s[0:1], v0, v9
441; SI-NEXT:    v_subb_u32_e64 v1, s[0:1], v1, v17, s[0:1]
442; SI-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s[8:9]
443; SI-NEXT:    v_cndmask_b32_e64 v5, v5, 0, vcc
444; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s3, v6
445; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
446; SI-NEXT:    v_cmp_lt_i32_e64 s[8:9], s25, 0
447; SI-NEXT:    v_cndmask_b32_e64 v4, v7, 0, s[8:9]
448; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], 0, v16
449; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]
450; SI-NEXT:    v_xor_b32_e32 v5, s16, v5
451; SI-NEXT:    v_cndmask_b32_e64 v7, v8, 0, s[8:9]
452; SI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s[0:1]
453; SI-NEXT:    v_cmp_lt_f32_e64 s[0:1], s2, v6
454; SI-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
455; SI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
456; SI-NEXT:    v_xor_b32_e32 v1, s16, v1
457; SI-NEXT:    v_cndmask_b32_e64 v1, v1, v7, s[0:1]
458; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
459; SI-NEXT:    s_endpgm
460;
461; VI-LABEL: fp_to_uint_v2f32_to_v2i64:
462; VI:       ; %bb.0:
463; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
464; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
465; VI-NEXT:    s_mov_b32 s17, 0x7fffff
466; VI-NEXT:    s_movk_i32 s16, 0xff6a
467; VI-NEXT:    s_mov_b32 s18, 0x800000
468; VI-NEXT:    s_movk_i32 s19, 0x96
469; VI-NEXT:    s_waitcnt lgkmcnt(0)
470; VI-NEXT:    s_bfe_u32 s12, s5, 0x80017
471; VI-NEXT:    s_and_b32 s1, s5, s17
472; VI-NEXT:    s_add_i32 s0, s12, s16
473; VI-NEXT:    s_or_b32 s6, s1, s18
474; VI-NEXT:    s_mov_b32 s7, 0
475; VI-NEXT:    s_sub_i32 s2, s19, s12
476; VI-NEXT:    s_movk_i32 s20, 0xff81
477; VI-NEXT:    s_lshl_b64 s[0:1], s[6:7], s0
478; VI-NEXT:    s_lshr_b64 s[2:3], s[6:7], s2
479; VI-NEXT:    s_add_i32 s12, s12, s20
480; VI-NEXT:    v_cmp_gt_i32_e64 vcc, s12, 23
481; VI-NEXT:    v_mov_b32_e32 v0, s3
482; VI-NEXT:    v_mov_b32_e32 v1, s1
483; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
484; VI-NEXT:    v_mov_b32_e32 v2, s0
485; VI-NEXT:    v_mov_b32_e32 v1, s2
486; VI-NEXT:    s_ashr_i32 s0, s5, 31
487; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
488; VI-NEXT:    s_ashr_i32 s1, s0, 31
489; VI-NEXT:    v_xor_b32_e32 v1, s0, v1
490; VI-NEXT:    v_mov_b32_e32 v8, 0x5f000000
491; VI-NEXT:    v_sub_f32_e32 v9, s5, v8
492; VI-NEXT:    v_xor_b32_e32 v0, s1, v0
493; VI-NEXT:    v_mov_b32_e32 v2, s1
494; VI-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1
495; VI-NEXT:    v_subb_u32_e32 v6, vcc, v0, v2, vcc
496; VI-NEXT:    v_bfe_u32 v10, v9, 23, 8
497; VI-NEXT:    v_and_b32_e32 v0, s17, v9
498; VI-NEXT:    v_cmp_lt_i32_e64 s[12:13], s12, 0
499; VI-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[12:13]
500; VI-NEXT:    v_add_u32_e32 v2, vcc, s16, v10
501; VI-NEXT:    v_or_b32_e32 v0, s18, v0
502; VI-NEXT:    v_mov_b32_e32 v1, 0
503; VI-NEXT:    v_sub_u32_e32 v4, vcc, s19, v10
504; VI-NEXT:    v_lshlrev_b64 v[2:3], v2, v[0:1]
505; VI-NEXT:    v_lshrrev_b64 v[4:5], v4, v[0:1]
506; VI-NEXT:    v_add_u32_e32 v0, vcc, s20, v10
507; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v0
508; VI-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
509; VI-NEXT:    v_ashrrev_i32_e32 v4, 31, v9
510; VI-NEXT:    s_and_b32 s6, s4, s17
511; VI-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
512; VI-NEXT:    v_xor_b32_e32 v2, v2, v4
513; VI-NEXT:    v_ashrrev_i32_e32 v5, 31, v4
514; VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s5, v8
515; VI-NEXT:    s_bfe_u32 s5, s4, 0x80017
516; VI-NEXT:    v_xor_b32_e32 v3, v3, v5
517; VI-NEXT:    v_sub_u32_e32 v2, vcc, v2, v4
518; VI-NEXT:    v_cmp_gt_i32_e64 s[0:1], 0, v0
519; VI-NEXT:    s_add_i32 s14, s5, s16
520; VI-NEXT:    s_or_b32 s6, s6, s18
521; VI-NEXT:    s_sub_i32 s21, s19, s5
522; VI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, s[0:1]
523; VI-NEXT:    s_lshl_b64 s[14:15], s[6:7], s14
524; VI-NEXT:    v_subb_u32_e32 v5, vcc, v3, v5, vcc
525; VI-NEXT:    s_add_i32 s5, s5, s20
526; VI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s21
527; VI-NEXT:    v_cndmask_b32_e64 v2, v0, v7, s[2:3]
528; VI-NEXT:    v_mov_b32_e32 v0, s7
529; VI-NEXT:    v_mov_b32_e32 v3, s15
530; VI-NEXT:    v_cmp_gt_i32_e64 vcc, s5, 23
531; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
532; VI-NEXT:    v_mov_b32_e32 v3, s6
533; VI-NEXT:    v_mov_b32_e32 v4, s14
534; VI-NEXT:    s_ashr_i32 s6, s4, 31
535; VI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
536; VI-NEXT:    s_ashr_i32 s7, s6, 31
537; VI-NEXT:    v_xor_b32_e32 v3, s6, v3
538; VI-NEXT:    v_sub_f32_e32 v10, s4, v8
539; VI-NEXT:    v_xor_b32_e32 v0, s7, v0
540; VI-NEXT:    v_mov_b32_e32 v4, s7
541; VI-NEXT:    v_subrev_u32_e32 v3, vcc, s6, v3
542; VI-NEXT:    v_cmp_lt_i32_e64 s[6:7], s5, 0
543; VI-NEXT:    v_subb_u32_e32 v7, vcc, v0, v4, vcc
544; VI-NEXT:    v_and_b32_e32 v0, s17, v10
545; VI-NEXT:    v_bfe_u32 v11, v10, 23, 8
546; VI-NEXT:    v_cndmask_b32_e64 v9, v3, 0, s[6:7]
547; VI-NEXT:    v_add_u32_e32 v3, vcc, s16, v11
548; VI-NEXT:    v_or_b32_e32 v0, s18, v0
549; VI-NEXT:    v_sub_u32_e32 v12, vcc, s19, v11
550; VI-NEXT:    v_add_u32_e32 v11, vcc, s20, v11
551; VI-NEXT:    v_lshlrev_b64 v[3:4], v3, v[0:1]
552; VI-NEXT:    v_lshrrev_b64 v[0:1], v12, v[0:1]
553; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v11
554; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
555; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v10
556; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
557; VI-NEXT:    v_xor_b32_e32 v0, v0, v3
558; VI-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
559; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v3
560; VI-NEXT:    v_xor_b32_e32 v1, v1, v4
561; VI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
562; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v11
563; VI-NEXT:    v_cndmask_b32_e64 v4, v5, 0, s[0:1]
564; VI-NEXT:    s_brev_b32 s0, 1
565; VI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
566; VI-NEXT:    v_cndmask_b32_e64 v3, v6, 0, s[12:13]
567; VI-NEXT:    v_xor_b32_e32 v4, s0, v4
568; VI-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[2:3]
569; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
570; VI-NEXT:    v_cmp_lt_f32_e64 s[4:5], s4, v8
571; VI-NEXT:    v_cndmask_b32_e64 v4, v7, 0, s[6:7]
572; VI-NEXT:    v_xor_b32_e32 v1, s0, v1
573; VI-NEXT:    s_mov_b32 s11, 0xf000
574; VI-NEXT:    s_mov_b32 s10, -1
575; VI-NEXT:    v_cndmask_b32_e64 v0, v0, v9, s[4:5]
576; VI-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[4:5]
577; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
578; VI-NEXT:    s_endpgm
579;
580; EG-LABEL: fp_to_uint_v2f32_to_v2i64:
581; EG:       ; %bb.0:
582; EG-NEXT:    ALU 77, @4, KC0[CB0:0-32], KC1[]
583; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
584; EG-NEXT:    CF_END
585; EG-NEXT:    PAD
586; EG-NEXT:    ALU clause starting at 4:
587; EG-NEXT:     MOV * T0.W, literal.x,
588; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
589; EG-NEXT:     BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
590; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
591; EG-NEXT:     AND_INT T0.Z, KC0[2].W, literal.x,
592; EG-NEXT:     BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
593; EG-NEXT:     ADD_INT * T2.W, PV.W, literal.z,
594; EG-NEXT:    8388607(1.175494e-38), 23(3.222986e-44)
595; EG-NEXT:    -150(nan), 0(0.000000e+00)
596; EG-NEXT:     SUB_INT T0.X, literal.x, PV.W,
597; EG-NEXT:     SUB_INT T0.Y, literal.x, T1.W,
598; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
599; EG-NEXT:     OR_INT T3.W, PV.Z, literal.z,
600; EG-NEXT:     AND_INT * T4.W, KC0[3].X, literal.w,
601; EG-NEXT:    150(2.101948e-43), 31(4.344025e-44)
602; EG-NEXT:    8388608(1.175494e-38), 8388607(1.175494e-38)
603; EG-NEXT:     OR_INT T1.X, PS, literal.x,
604; EG-NEXT:     LSHL T1.Y, PV.W, PV.Z,
605; EG-NEXT:     AND_INT T0.Z, T2.W, literal.y,
606; EG-NEXT:     BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
607; EG-NEXT:     AND_INT * T5.W, PV.Y, literal.y,
608; EG-NEXT:    8388608(1.175494e-38), 32(4.484155e-44)
609; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, 0.0,
610; EG-NEXT:     CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
611; EG-NEXT:     ADD_INT T1.Z, T0.W, literal.x,
612; EG-NEXT:     BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
613; EG-NEXT:     AND_INT * T5.W, T0.X, literal.y,
614; EG-NEXT:    -150(nan), 32(4.484155e-44)
615; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, 0.0,
616; EG-NEXT:     NOT_INT T2.Y, T2.W,
617; EG-NEXT:     AND_INT T2.Z, PV.Z, literal.x,
618; EG-NEXT:     NOT_INT T2.W, PV.Z,
619; EG-NEXT:     LSHR * T4.W, T1.X, 1,
620; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
621; EG-NEXT:     LSHR T3.X, T3.W, 1,
622; EG-NEXT:     ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
623; EG-NEXT:     BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
624; EG-NEXT:     LSHL T0.W, T1.X, PV.Z,
625; EG-NEXT:     AND_INT * T2.W, T1.Z, literal.y,
626; EG-NEXT:    -127(nan), 32(4.484155e-44)
627; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
628; EG-NEXT:     CNDE_INT T4.Y, PS, PV.Z, PV.W,
629; EG-NEXT:     SETGT_INT T1.Z, PV.Y, literal.x,
630; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
631; EG-NEXT:     ADD_INT * T1.W, T1.W, literal.y,
632; EG-NEXT:    23(3.222986e-44), -127(nan)
633; EG-NEXT:     CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
634; EG-NEXT:     SETGT_INT T1.Y, PS, literal.x,
635; EG-NEXT:     CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
636; EG-NEXT:     CNDE_INT T0.W, PV.Z, T0.X, PV.X,
637; EG-NEXT:     ASHR * T2.W, KC0[3].X, literal.y,
638; EG-NEXT:    23(3.222986e-44), 31(4.344025e-44)
639; EG-NEXT:     XOR_INT T0.X, PV.W, PS,
640; EG-NEXT:     XOR_INT T2.Y, PV.Z, PS,
641; EG-NEXT:     CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
642; EG-NEXT:     CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
643; EG-NEXT:     ASHR * T3.W, KC0[2].W, literal.x,
644; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
645; EG-NEXT:     XOR_INT T0.Y, PV.W, PS,
646; EG-NEXT:     XOR_INT T0.Z, PV.Z, PS,
647; EG-NEXT:     SUB_INT T0.W, PV.Y, T2.W,
648; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T2.W,
649; EG-NEXT:     SUB_INT T1.Y, PV.W, PS,
650; EG-NEXT:     SETGT_INT T1.Z, T3.Y, literal.x,
651; EG-NEXT:     SUB_INT T0.W, PV.Z, T3.W,
652; EG-NEXT:     SUBB_UINT * T4.W, PV.Y, T3.W,
653; EG-NEXT:    -1(nan), 0(0.000000e+00)
654; EG-NEXT:     SUB_INT T0.Z, PV.W, PS,
655; EG-NEXT:     SETGT_INT T0.W, T1.W, literal.x,
656; EG-NEXT:     CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122
657; EG-NEXT:    -1(nan), 0(0.000000e+00)
658; EG-NEXT:     CNDE_INT T1.Y, PV.W, 0.0, PV.Z,
659; EG-NEXT:     SUB_INT * T2.W, T0.X, T2.W,
660; EG-NEXT:     CNDE_INT T1.Z, T1.Z, 0.0, PV.W,
661; EG-NEXT:     SUB_INT * T2.W, T0.Y, T3.W,
662; EG-NEXT:     CNDE_INT T1.X, T0.W, 0.0, PV.W,
663; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
664; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
665  %conv = fptoui <2 x float> %x to <2 x i64>
666  store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
667  ret void
668}
669
670define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
671; SI-LABEL: fp_to_uint_v4f32_to_v4i64:
672; SI:       ; %bb.0:
673; SI-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
674; SI-NEXT:    s_movk_i32 s6, 0xff6a
675; SI-NEXT:    s_mov_b32 s7, 0x7fffff
676; SI-NEXT:    s_mov_b32 s18, 0x800000
677; SI-NEXT:    s_mov_b32 s13, 0
678; SI-NEXT:    s_movk_i32 s19, 0x96
679; SI-NEXT:    s_movk_i32 s20, 0xff81
680; SI-NEXT:    v_mov_b32_e32 v7, 0x5f000000
681; SI-NEXT:    v_mov_b32_e32 v1, 0
682; SI-NEXT:    s_waitcnt lgkmcnt(0)
683; SI-NEXT:    s_bfe_u32 s2, s9, 0x80017
684; SI-NEXT:    s_and_b32 s3, s9, s7
685; SI-NEXT:    v_sub_f32_e32 v6, s9, v7
686; SI-NEXT:    s_bfe_u32 s4, s8, 0x80017
687; SI-NEXT:    s_and_b32 s14, s8, s7
688; SI-NEXT:    v_sub_f32_e32 v8, s8, v7
689; SI-NEXT:    v_sub_f32_e32 v9, s11, v7
690; SI-NEXT:    v_sub_f32_e32 v10, s10, v7
691; SI-NEXT:    s_add_i32 s5, s2, s6
692; SI-NEXT:    s_or_b32 s12, s3, s18
693; SI-NEXT:    s_sub_i32 s15, s19, s2
694; SI-NEXT:    s_add_i32 s21, s2, s20
695; SI-NEXT:    v_bfe_u32 v2, v6, 23, 8
696; SI-NEXT:    v_and_b32_e32 v0, s7, v6
697; SI-NEXT:    s_add_i32 s16, s4, s6
698; SI-NEXT:    s_sub_i32 s17, s19, s4
699; SI-NEXT:    s_add_i32 s22, s4, s20
700; SI-NEXT:    v_bfe_u32 v3, v8, 23, 8
701; SI-NEXT:    v_and_b32_e32 v11, s7, v8
702; SI-NEXT:    v_bfe_u32 v12, v9, 23, 8
703; SI-NEXT:    v_and_b32_e32 v13, s7, v9
704; SI-NEXT:    v_bfe_u32 v14, v10, 23, 8
705; SI-NEXT:    v_add_i32_e32 v4, vcc, s6, v2
706; SI-NEXT:    v_or_b32_e32 v0, s18, v0
707; SI-NEXT:    v_sub_i32_e32 v5, vcc, s19, v2
708; SI-NEXT:    v_add_i32_e32 v15, vcc, s20, v2
709; SI-NEXT:    v_add_i32_e32 v16, vcc, s6, v3
710; SI-NEXT:    v_sub_i32_e32 v17, vcc, s19, v3
711; SI-NEXT:    v_add_i32_e32 v18, vcc, s20, v3
712; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], v4
713; SI-NEXT:    v_lshr_b64 v[4:5], v[0:1], v5
714; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v15
715; SI-NEXT:    v_cndmask_b32_e32 v19, v5, v3, vcc
716; SI-NEXT:    v_cndmask_b32_e32 v20, v4, v2, vcc
717; SI-NEXT:    v_add_i32_e32 v21, vcc, s6, v12
718; SI-NEXT:    v_sub_i32_e32 v22, vcc, s19, v12
719; SI-NEXT:    v_add_i32_e32 v12, vcc, s20, v12
720; SI-NEXT:    v_or_b32_e32 v0, s18, v11
721; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], v16
722; SI-NEXT:    v_lshr_b64 v[4:5], v[0:1], v17
723; SI-NEXT:    v_or_b32_e32 v0, s18, v13
724; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v18
725; SI-NEXT:    v_cndmask_b32_e32 v11, v5, v3, vcc
726; SI-NEXT:    v_cndmask_b32_e32 v13, v4, v2, vcc
727; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], v21
728; SI-NEXT:    v_lshr_b64 v[4:5], v[0:1], v22
729; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v12
730; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v3, vcc
731; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v2, vcc
732; SI-NEXT:    v_and_b32_e32 v0, s7, v10
733; SI-NEXT:    s_lshl_b64 s[2:3], s[12:13], s5
734; SI-NEXT:    s_lshr_b64 s[4:5], s[12:13], s15
735; SI-NEXT:    s_or_b32 s12, s14, s18
736; SI-NEXT:    v_add_i32_e32 v2, vcc, s6, v14
737; SI-NEXT:    v_sub_i32_e32 v16, vcc, s19, v14
738; SI-NEXT:    v_add_i32_e32 v14, vcc, s20, v14
739; SI-NEXT:    v_or_b32_e32 v0, s18, v0
740; SI-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
741; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], v16
742; SI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v14
743; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
744; SI-NEXT:    v_cndmask_b32_e32 v16, v0, v2, vcc
745; SI-NEXT:    v_mov_b32_e32 v0, s5
746; SI-NEXT:    v_mov_b32_e32 v2, s3
747; SI-NEXT:    v_cmp_gt_i32_e64 vcc, s21, 23
748; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
749; SI-NEXT:    v_mov_b32_e32 v2, s4
750; SI-NEXT:    v_mov_b32_e32 v3, s2
751; SI-NEXT:    s_lshl_b64 s[2:3], s[12:13], s16
752; SI-NEXT:    s_lshr_b64 s[4:5], s[12:13], s17
753; SI-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
754; SI-NEXT:    v_mov_b32_e32 v3, s5
755; SI-NEXT:    v_mov_b32_e32 v17, s3
756; SI-NEXT:    v_cmp_gt_i32_e64 vcc, s22, 23
757; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v17, vcc
758; SI-NEXT:    v_mov_b32_e32 v17, s4
759; SI-NEXT:    v_mov_b32_e32 v21, s2
760; SI-NEXT:    v_cndmask_b32_e32 v17, v17, v21, vcc
761; SI-NEXT:    s_bfe_u32 s2, s11, 0x80017
762; SI-NEXT:    s_and_b32 s3, s11, s7
763; SI-NEXT:    s_add_i32 s4, s2, s6
764; SI-NEXT:    s_sub_i32 s5, s19, s2
765; SI-NEXT:    s_or_b32 s12, s3, s18
766; SI-NEXT:    s_lshl_b64 s[14:15], s[12:13], s4
767; SI-NEXT:    s_lshr_b64 s[16:17], s[12:13], s5
768; SI-NEXT:    s_add_i32 s24, s2, s20
769; SI-NEXT:    v_mov_b32_e32 v21, s17
770; SI-NEXT:    v_mov_b32_e32 v22, s15
771; SI-NEXT:    v_cmp_gt_i32_e64 vcc, s24, 23
772; SI-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc
773; SI-NEXT:    s_ashr_i32 s2, s9, 31
774; SI-NEXT:    s_ashr_i32 s3, s2, 31
775; SI-NEXT:    v_xor_b32_e32 v0, s3, v0
776; SI-NEXT:    v_xor_b32_e32 v2, s2, v2
777; SI-NEXT:    v_mov_b32_e32 v22, s3
778; SI-NEXT:    v_subrev_i32_e64 v2, s[2:3], s2, v2
779; SI-NEXT:    v_subb_u32_e64 v22, s[2:3], v0, v22, s[2:3]
780; SI-NEXT:    v_ashrrev_i32_e32 v0, 31, v6
781; SI-NEXT:    v_xor_b32_e32 v6, v20, v0
782; SI-NEXT:    v_ashrrev_i32_e32 v20, 31, v0
783; SI-NEXT:    v_xor_b32_e32 v19, v19, v20
784; SI-NEXT:    v_sub_i32_e64 v0, s[2:3], v6, v0
785; SI-NEXT:    v_subb_u32_e64 v6, s[2:3], v19, v20, s[2:3]
786; SI-NEXT:    v_cmp_gt_i32_e64 s[2:3], 0, v15
787; SI-NEXT:    s_ashr_i32 s4, s8, 31
788; SI-NEXT:    s_ashr_i32 s5, s4, 31
789; SI-NEXT:    v_xor_b32_e32 v3, s5, v3
790; SI-NEXT:    v_xor_b32_e32 v15, s4, v17
791; SI-NEXT:    v_mov_b32_e32 v17, s5
792; SI-NEXT:    v_subrev_i32_e64 v15, s[4:5], s4, v15
793; SI-NEXT:    v_subb_u32_e64 v17, s[4:5], v3, v17, s[4:5]
794; SI-NEXT:    v_ashrrev_i32_e32 v3, 31, v8
795; SI-NEXT:    v_xor_b32_e32 v8, v13, v3
796; SI-NEXT:    v_ashrrev_i32_e32 v13, 31, v3
797; SI-NEXT:    v_xor_b32_e32 v11, v11, v13
798; SI-NEXT:    v_sub_i32_e64 v3, s[4:5], v8, v3
799; SI-NEXT:    s_bfe_u32 s12, s10, 0x80017
800; SI-NEXT:    s_and_b32 s7, s10, s7
801; SI-NEXT:    s_add_i32 s15, s12, s6
802; SI-NEXT:    s_sub_i32 s23, s19, s12
803; SI-NEXT:    s_add_i32 s25, s12, s20
804; SI-NEXT:    s_or_b32 s12, s7, s18
805; SI-NEXT:    v_cmp_lt_i32_e64 s[18:19], s21, 0
806; SI-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s[18:19]
807; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[2:3]
808; SI-NEXT:    v_subb_u32_e64 v8, s[4:5], v11, v13, s[4:5]
809; SI-NEXT:    v_cmp_gt_i32_e64 s[4:5], 0, v18
810; SI-NEXT:    v_cmp_lt_f32_e64 s[6:7], s9, v7
811; SI-NEXT:    v_cndmask_b32_e64 v2, v0, v2, s[6:7]
812; SI-NEXT:    v_cmp_lt_i32_e64 s[20:21], s22, 0
813; SI-NEXT:    v_cndmask_b32_e64 v0, v15, 0, s[20:21]
814; SI-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s[4:5]
815; SI-NEXT:    v_cmp_lt_f32_e64 s[8:9], s8, v7
816; SI-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[8:9]
817; SI-NEXT:    v_mov_b32_e32 v3, s16
818; SI-NEXT:    v_mov_b32_e32 v11, s14
819; SI-NEXT:    s_lshl_b64 s[16:17], s[12:13], s15
820; SI-NEXT:    s_lshr_b64 s[22:23], s[12:13], s23
821; SI-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
822; SI-NEXT:    v_mov_b32_e32 v3, s23
823; SI-NEXT:    v_mov_b32_e32 v13, s17
824; SI-NEXT:    v_cmp_gt_i32_e64 vcc, s25, 23
825; SI-NEXT:    v_cndmask_b32_e32 v13, v3, v13, vcc
826; SI-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
827; SI-NEXT:    s_mov_b32 s15, 0xf000
828; SI-NEXT:    s_mov_b32 s14, -1
829; SI-NEXT:    s_brev_b32 s17, 1
830; SI-NEXT:    s_ashr_i32 s0, s11, 31
831; SI-NEXT:    s_ashr_i32 s1, s10, 31
832; SI-NEXT:    s_ashr_i32 s23, s0, 31
833; SI-NEXT:    v_ashrrev_i32_e32 v9, 31, v9
834; SI-NEXT:    s_ashr_i32 s26, s1, 31
835; SI-NEXT:    v_ashrrev_i32_e32 v10, 31, v10
836; SI-NEXT:    v_cndmask_b32_e64 v3, v22, 0, s[18:19]
837; SI-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s[2:3]
838; SI-NEXT:    v_xor_b32_e32 v6, s17, v6
839; SI-NEXT:    v_cndmask_b32_e64 v3, v6, v3, s[6:7]
840; SI-NEXT:    v_mov_b32_e32 v6, s22
841; SI-NEXT:    v_mov_b32_e32 v15, s16
842; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v15, vcc
843; SI-NEXT:    v_mov_b32_e32 v15, s23
844; SI-NEXT:    v_xor_b32_e32 v18, s23, v21
845; SI-NEXT:    v_xor_b32_e32 v11, s0, v11
846; SI-NEXT:    v_subrev_i32_e32 v11, vcc, s0, v11
847; SI-NEXT:    v_subb_u32_e32 v15, vcc, v18, v15, vcc
848; SI-NEXT:    v_ashrrev_i32_e32 v18, 31, v9
849; SI-NEXT:    v_xor_b32_e32 v4, v4, v9
850; SI-NEXT:    v_xor_b32_e32 v5, v5, v18
851; SI-NEXT:    v_sub_i32_e32 v4, vcc, v4, v9
852; SI-NEXT:    v_mov_b32_e32 v9, s26
853; SI-NEXT:    v_subb_u32_e32 v5, vcc, v5, v18, vcc
854; SI-NEXT:    v_ashrrev_i32_e32 v18, 31, v10
855; SI-NEXT:    v_xor_b32_e32 v13, s26, v13
856; SI-NEXT:    v_cndmask_b32_e64 v17, v17, 0, s[20:21]
857; SI-NEXT:    v_cndmask_b32_e64 v8, v8, 0, s[4:5]
858; SI-NEXT:    v_xor_b32_e32 v6, s1, v6
859; SI-NEXT:    v_xor_b32_e32 v16, v16, v10
860; SI-NEXT:    v_xor_b32_e32 v1, v1, v18
861; SI-NEXT:    v_xor_b32_e32 v8, s17, v8
862; SI-NEXT:    v_cmp_lt_i32_e64 s[2:3], s24, 0
863; SI-NEXT:    v_cndmask_b32_e64 v11, v11, 0, s[2:3]
864; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v12
865; SI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
866; SI-NEXT:    v_subrev_i32_e64 v12, s[0:1], s1, v6
867; SI-NEXT:    v_subb_u32_e64 v9, s[0:1], v13, v9, s[0:1]
868; SI-NEXT:    v_sub_i32_e64 v10, s[0:1], v16, v10
869; SI-NEXT:    v_subb_u32_e64 v13, s[0:1], v1, v18, s[0:1]
870; SI-NEXT:    v_cndmask_b32_e64 v15, v15, 0, s[2:3]
871; SI-NEXT:    v_cndmask_b32_e64 v5, v5, 0, vcc
872; SI-NEXT:    v_cndmask_b32_e64 v1, v8, v17, s[8:9]
873; SI-NEXT:    v_cmp_lt_f32_e32 vcc, s11, v7
874; SI-NEXT:    v_cndmask_b32_e32 v6, v4, v11, vcc
875; SI-NEXT:    v_cmp_lt_i32_e64 s[2:3], s25, 0
876; SI-NEXT:    v_cndmask_b32_e64 v4, v12, 0, s[2:3]
877; SI-NEXT:    v_cmp_gt_i32_e64 s[0:1], 0, v14
878; SI-NEXT:    v_cndmask_b32_e64 v8, v10, 0, s[0:1]
879; SI-NEXT:    v_xor_b32_e32 v5, s17, v5
880; SI-NEXT:    v_cndmask_b32_e64 v9, v9, 0, s[2:3]
881; SI-NEXT:    v_cndmask_b32_e64 v10, v13, 0, s[0:1]
882; SI-NEXT:    v_cmp_lt_f32_e64 s[0:1], s10, v7
883; SI-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[0:1]
884; SI-NEXT:    v_cndmask_b32_e32 v7, v5, v15, vcc
885; SI-NEXT:    v_xor_b32_e32 v5, s17, v10
886; SI-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s[0:1]
887; SI-NEXT:    s_waitcnt lgkmcnt(0)
888; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[12:15], 0 offset:16
889; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
890; SI-NEXT:    s_endpgm
891;
892; VI-LABEL: fp_to_uint_v4f32_to_v4i64:
893; VI:       ; %bb.0:
894; VI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
895; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
896; VI-NEXT:    s_mov_b32 s21, 0x7fffff
897; VI-NEXT:    s_movk_i32 s20, 0xff6a
898; VI-NEXT:    s_mov_b32 s22, 0x800000
899; VI-NEXT:    s_movk_i32 s23, 0x96
900; VI-NEXT:    s_waitcnt lgkmcnt(0)
901; VI-NEXT:    s_bfe_u32 s14, s5, 0x80017
902; VI-NEXT:    s_and_b32 s1, s5, s21
903; VI-NEXT:    s_add_i32 s0, s14, s20
904; VI-NEXT:    s_or_b32 s12, s1, s22
905; VI-NEXT:    s_mov_b32 s13, 0
906; VI-NEXT:    s_sub_i32 s2, s23, s14
907; VI-NEXT:    s_movk_i32 s24, 0xff81
908; VI-NEXT:    s_lshl_b64 s[0:1], s[12:13], s0
909; VI-NEXT:    s_lshr_b64 s[2:3], s[12:13], s2
910; VI-NEXT:    s_add_i32 s14, s14, s24
911; VI-NEXT:    v_cmp_gt_i32_e64 vcc, s14, 23
912; VI-NEXT:    v_mov_b32_e32 v0, s3
913; VI-NEXT:    v_mov_b32_e32 v1, s1
914; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
915; VI-NEXT:    v_mov_b32_e32 v2, s0
916; VI-NEXT:    v_mov_b32_e32 v1, s2
917; VI-NEXT:    s_ashr_i32 s0, s5, 31
918; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
919; VI-NEXT:    v_mov_b32_e32 v10, 0x5f000000
920; VI-NEXT:    v_xor_b32_e32 v1, s0, v1
921; VI-NEXT:    s_ashr_i32 s1, s0, 31
922; VI-NEXT:    v_sub_f32_e32 v8, s5, v10
923; VI-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1
924; VI-NEXT:    v_cmp_lt_i32_e64 s[14:15], s14, 0
925; VI-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[14:15]
926; VI-NEXT:    v_and_b32_e32 v1, s21, v8
927; VI-NEXT:    v_xor_b32_e32 v0, s1, v0
928; VI-NEXT:    v_mov_b32_e32 v2, s1
929; VI-NEXT:    v_bfe_u32 v9, v8, 23, 8
930; VI-NEXT:    v_subb_u32_e32 v6, vcc, v0, v2, vcc
931; VI-NEXT:    v_add_u32_e32 v0, vcc, s20, v9
932; VI-NEXT:    v_or_b32_e32 v4, s22, v1
933; VI-NEXT:    v_mov_b32_e32 v5, 0
934; VI-NEXT:    v_sub_u32_e32 v2, vcc, s23, v9
935; VI-NEXT:    v_lshlrev_b64 v[0:1], v0, v[4:5]
936; VI-NEXT:    v_lshrrev_b64 v[2:3], v2, v[4:5]
937; VI-NEXT:    v_add_u32_e32 v4, vcc, s24, v9
938; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v4
939; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
940; VI-NEXT:    v_ashrrev_i32_e32 v2, 31, v8
941; VI-NEXT:    s_and_b32 s12, s4, s21
942; VI-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
943; VI-NEXT:    v_xor_b32_e32 v0, v0, v2
944; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
945; VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s5, v10
946; VI-NEXT:    s_bfe_u32 s5, s4, 0x80017
947; VI-NEXT:    v_xor_b32_e32 v1, v1, v3
948; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v2
949; VI-NEXT:    v_cmp_gt_i32_e64 s[0:1], 0, v4
950; VI-NEXT:    s_add_i32 s16, s5, s20
951; VI-NEXT:    s_or_b32 s12, s12, s22
952; VI-NEXT:    s_sub_i32 s18, s23, s5
953; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]
954; VI-NEXT:    v_subb_u32_e32 v8, vcc, v1, v3, vcc
955; VI-NEXT:    s_lshl_b64 s[16:17], s[12:13], s16
956; VI-NEXT:    s_lshr_b64 s[18:19], s[12:13], s18
957; VI-NEXT:    s_add_i32 s5, s5, s24
958; VI-NEXT:    v_cndmask_b32_e64 v2, v0, v7, s[2:3]
959; VI-NEXT:    v_mov_b32_e32 v0, s19
960; VI-NEXT:    v_mov_b32_e32 v1, s17
961; VI-NEXT:    v_cmp_gt_i32_e64 vcc, s5, 23
962; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
963; VI-NEXT:    v_mov_b32_e32 v1, s18
964; VI-NEXT:    v_mov_b32_e32 v3, s16
965; VI-NEXT:    s_ashr_i32 s12, s4, 31
966; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
967; VI-NEXT:    s_ashr_i32 s16, s12, 31
968; VI-NEXT:    v_xor_b32_e32 v1, s12, v1
969; VI-NEXT:    v_sub_f32_e32 v11, s4, v10
970; VI-NEXT:    v_xor_b32_e32 v0, s16, v0
971; VI-NEXT:    v_mov_b32_e32 v3, s16
972; VI-NEXT:    v_subrev_u32_e32 v1, vcc, s12, v1
973; VI-NEXT:    v_cmp_lt_i32_e64 s[16:17], s5, 0
974; VI-NEXT:    v_cndmask_b32_e64 v9, v1, 0, s[16:17]
975; VI-NEXT:    v_and_b32_e32 v1, s21, v11
976; VI-NEXT:    v_bfe_u32 v12, v11, 23, 8
977; VI-NEXT:    v_subb_u32_e32 v7, vcc, v0, v3, vcc
978; VI-NEXT:    v_add_u32_e32 v0, vcc, s20, v12
979; VI-NEXT:    v_or_b32_e32 v4, s22, v1
980; VI-NEXT:    v_sub_u32_e32 v3, vcc, s23, v12
981; VI-NEXT:    v_add_u32_e32 v12, vcc, s24, v12
982; VI-NEXT:    v_lshlrev_b64 v[0:1], v0, v[4:5]
983; VI-NEXT:    v_lshrrev_b64 v[3:4], v3, v[4:5]
984; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v12
985; VI-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
986; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v11
987; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
988; VI-NEXT:    v_xor_b32_e32 v0, v0, v3
989; VI-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
990; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v3
991; VI-NEXT:    v_xor_b32_e32 v1, v1, v4
992; VI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
993; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v12
994; VI-NEXT:    v_cndmask_b32_e64 v4, v8, 0, s[0:1]
995; VI-NEXT:    s_brev_b32 s18, 1
996; VI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
997; VI-NEXT:    v_cndmask_b32_e64 v3, v6, 0, s[14:15]
998; VI-NEXT:    v_xor_b32_e32 v4, s18, v4
999; VI-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[2:3]
1000; VI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
1001; VI-NEXT:    v_cmp_lt_f32_e64 s[4:5], s4, v10
1002; VI-NEXT:    v_cndmask_b32_e64 v4, v7, 0, s[16:17]
1003; VI-NEXT:    v_xor_b32_e32 v1, s18, v1
1004; VI-NEXT:    s_and_b32 s1, s7, s21
1005; VI-NEXT:    v_cndmask_b32_e64 v0, v0, v9, s[4:5]
1006; VI-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[4:5]
1007; VI-NEXT:    s_bfe_u32 s4, s7, 0x80017
1008; VI-NEXT:    s_add_i32 s0, s4, s20
1009; VI-NEXT:    s_or_b32 s12, s1, s22
1010; VI-NEXT:    s_sub_i32 s2, s23, s4
1011; VI-NEXT:    s_lshl_b64 s[0:1], s[12:13], s0
1012; VI-NEXT:    s_add_i32 s4, s4, s24
1013; VI-NEXT:    s_lshr_b64 s[2:3], s[12:13], s2
1014; VI-NEXT:    v_mov_b32_e32 v4, s3
1015; VI-NEXT:    v_mov_b32_e32 v6, s1
1016; VI-NEXT:    v_cmp_gt_i32_e64 vcc, s4, 23
1017; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
1018; VI-NEXT:    v_mov_b32_e32 v6, s2
1019; VI-NEXT:    v_mov_b32_e32 v7, s0
1020; VI-NEXT:    s_ashr_i32 s0, s7, 31
1021; VI-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
1022; VI-NEXT:    s_ashr_i32 s1, s0, 31
1023; VI-NEXT:    v_xor_b32_e32 v6, s0, v6
1024; VI-NEXT:    v_sub_f32_e32 v13, s7, v10
1025; VI-NEXT:    v_xor_b32_e32 v4, s1, v4
1026; VI-NEXT:    v_mov_b32_e32 v7, s1
1027; VI-NEXT:    v_subrev_u32_e32 v6, vcc, s0, v6
1028; VI-NEXT:    v_subb_u32_e32 v11, vcc, v4, v7, vcc
1029; VI-NEXT:    v_and_b32_e32 v4, s21, v13
1030; VI-NEXT:    v_cmp_lt_i32_e64 s[14:15], s4, 0
1031; VI-NEXT:    v_bfe_u32 v14, v13, 23, 8
1032; VI-NEXT:    v_cndmask_b32_e64 v12, v6, 0, s[14:15]
1033; VI-NEXT:    v_add_u32_e32 v6, vcc, s20, v14
1034; VI-NEXT:    v_or_b32_e32 v4, s22, v4
1035; VI-NEXT:    v_sub_u32_e32 v8, vcc, s23, v14
1036; VI-NEXT:    v_lshlrev_b64 v[6:7], v6, v[4:5]
1037; VI-NEXT:    v_lshrrev_b64 v[8:9], v8, v[4:5]
1038; VI-NEXT:    v_add_u32_e32 v4, vcc, s24, v14
1039; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v4
1040; VI-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
1041; VI-NEXT:    v_ashrrev_i32_e32 v8, 31, v13
1042; VI-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc
1043; VI-NEXT:    v_xor_b32_e32 v6, v6, v8
1044; VI-NEXT:    v_ashrrev_i32_e32 v9, 31, v8
1045; VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s7, v10
1046; VI-NEXT:    s_bfe_u32 s7, s6, 0x80017
1047; VI-NEXT:    s_and_b32 s5, s6, s21
1048; VI-NEXT:    v_xor_b32_e32 v7, v7, v9
1049; VI-NEXT:    v_sub_u32_e32 v6, vcc, v6, v8
1050; VI-NEXT:    v_cmp_gt_i32_e64 s[0:1], 0, v4
1051; VI-NEXT:    s_add_i32 s4, s7, s20
1052; VI-NEXT:    s_or_b32 s12, s5, s22
1053; VI-NEXT:    s_sub_i32 s16, s23, s7
1054; VI-NEXT:    v_cndmask_b32_e64 v4, v6, 0, s[0:1]
1055; VI-NEXT:    s_lshl_b64 s[4:5], s[12:13], s4
1056; VI-NEXT:    v_subb_u32_e32 v9, vcc, v7, v9, vcc
1057; VI-NEXT:    s_add_i32 s7, s7, s24
1058; VI-NEXT:    s_lshr_b64 s[12:13], s[12:13], s16
1059; VI-NEXT:    v_cndmask_b32_e64 v6, v4, v12, s[2:3]
1060; VI-NEXT:    v_mov_b32_e32 v4, s13
1061; VI-NEXT:    v_mov_b32_e32 v7, s5
1062; VI-NEXT:    v_cmp_gt_i32_e64 vcc, s7, 23
1063; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
1064; VI-NEXT:    v_mov_b32_e32 v7, s12
1065; VI-NEXT:    v_mov_b32_e32 v8, s4
1066; VI-NEXT:    s_ashr_i32 s4, s6, 31
1067; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
1068; VI-NEXT:    s_ashr_i32 s5, s4, 31
1069; VI-NEXT:    v_xor_b32_e32 v7, s4, v7
1070; VI-NEXT:    v_sub_f32_e32 v14, s6, v10
1071; VI-NEXT:    v_xor_b32_e32 v4, s5, v4
1072; VI-NEXT:    v_mov_b32_e32 v8, s5
1073; VI-NEXT:    v_subrev_u32_e32 v7, vcc, s4, v7
1074; VI-NEXT:    v_subb_u32_e32 v12, vcc, v4, v8, vcc
1075; VI-NEXT:    v_and_b32_e32 v4, s21, v14
1076; VI-NEXT:    v_cmp_lt_i32_e64 s[12:13], s7, 0
1077; VI-NEXT:    v_bfe_u32 v15, v14, 23, 8
1078; VI-NEXT:    v_cndmask_b32_e64 v13, v7, 0, s[12:13]
1079; VI-NEXT:    v_add_u32_e32 v7, vcc, s20, v15
1080; VI-NEXT:    v_or_b32_e32 v4, s22, v4
1081; VI-NEXT:    v_sub_u32_e32 v16, vcc, s23, v15
1082; VI-NEXT:    v_add_u32_e32 v15, vcc, s24, v15
1083; VI-NEXT:    v_lshlrev_b64 v[7:8], v7, v[4:5]
1084; VI-NEXT:    v_lshrrev_b64 v[4:5], v16, v[4:5]
1085; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 23, v15
1086; VI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
1087; VI-NEXT:    v_ashrrev_i32_e32 v7, 31, v14
1088; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
1089; VI-NEXT:    v_xor_b32_e32 v4, v4, v7
1090; VI-NEXT:    v_ashrrev_i32_e32 v8, 31, v7
1091; VI-NEXT:    v_sub_u32_e32 v4, vcc, v4, v7
1092; VI-NEXT:    v_xor_b32_e32 v5, v5, v8
1093; VI-NEXT:    v_subb_u32_e32 v5, vcc, v5, v8, vcc
1094; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v15
1095; VI-NEXT:    v_cndmask_b32_e64 v8, v9, 0, s[0:1]
1096; VI-NEXT:    v_cndmask_b32_e64 v5, v5, 0, vcc
1097; VI-NEXT:    v_cndmask_b32_e64 v7, v11, 0, s[14:15]
1098; VI-NEXT:    v_xor_b32_e32 v8, s18, v8
1099; VI-NEXT:    v_cndmask_b32_e64 v7, v8, v7, s[2:3]
1100; VI-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
1101; VI-NEXT:    v_cmp_lt_f32_e64 s[4:5], s6, v10
1102; VI-NEXT:    v_cndmask_b32_e64 v8, v12, 0, s[12:13]
1103; VI-NEXT:    v_xor_b32_e32 v5, s18, v5
1104; VI-NEXT:    s_mov_b32 s11, 0xf000
1105; VI-NEXT:    s_mov_b32 s10, -1
1106; VI-NEXT:    v_cndmask_b32_e64 v4, v4, v13, s[4:5]
1107; VI-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1108; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
1109; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
1110; VI-NEXT:    s_endpgm
1111;
1112; EG-LABEL: fp_to_uint_v4f32_to_v4i64:
1113; EG:       ; %bb.0:
1114; EG-NEXT:    ALU 101, @6, KC0[CB0:0-32], KC1[]
1115; EG-NEXT:    ALU 58, @108, KC0[CB0:0-32], KC1[]
1116; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
1117; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
1118; EG-NEXT:    CF_END
1119; EG-NEXT:    PAD
1120; EG-NEXT:    ALU clause starting at 6:
1121; EG-NEXT:     MOV * T0.W, literal.x,
1122; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
1123; EG-NEXT:     BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
1124; EG-NEXT:     AND_INT * T2.W, KC0[4].X, literal.y,
1125; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
1126; EG-NEXT:     OR_INT T0.Z, PS, literal.x,
1127; EG-NEXT:     BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
1128; EG-NEXT:     ADD_INT * T3.W, PV.W, literal.z,
1129; EG-NEXT:    8388608(1.175494e-38), 23(3.222986e-44)
1130; EG-NEXT:    -150(nan), 0(0.000000e+00)
1131; EG-NEXT:     ADD_INT T0.Y, PV.W, literal.x,
1132; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
1133; EG-NEXT:     NOT_INT T4.W, PS,
1134; EG-NEXT:     LSHR * T5.W, PV.Z, 1,
1135; EG-NEXT:    -127(nan), 31(4.344025e-44)
1136; EG-NEXT:     ADD_INT T0.X, T1.W, literal.x,
1137; EG-NEXT:     BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
1138; EG-NEXT:     AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
1139; EG-NEXT:     LSHL T3.W, T0.Z, PV.Z,
1140; EG-NEXT:     SUB_INT * T1.W, literal.z, T1.W,
1141; EG-NEXT:    -127(nan), 32(4.484155e-44)
1142; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
1143; EG-NEXT:     AND_INT T1.X, PS, literal.x,
1144; EG-NEXT:     BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
1145; EG-NEXT:     AND_INT T0.Z, KC0[3].Z, literal.y,
1146; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
1147; EG-NEXT:     SETGT_INT * T4.W, PV.X, literal.z,
1148; EG-NEXT:    32(4.484155e-44), 8388607(1.175494e-38)
1149; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
1150; EG-NEXT:     CNDE_INT T2.X, PS, 0.0, PV.W,
1151; EG-NEXT:     OR_INT T1.Y, PV.Z, literal.x,
1152; EG-NEXT:     ADD_INT T0.Z, T2.W, literal.y,
1153; EG-NEXT:     CNDE_INT T1.W, PV.X, PV.Y, 0.0,
1154; EG-NEXT:     CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
1155; EG-NEXT:    8388608(1.175494e-38), -150(nan)
1156; EG-NEXT:     CNDE_INT T1.X, T4.W, PV.W, PS,
1157; EG-NEXT:     ASHR T2.Y, KC0[4].X, literal.x,
1158; EG-NEXT:     AND_INT T1.Z, PV.Z, literal.x,
1159; EG-NEXT:     NOT_INT T1.W, PV.Z,
1160; EG-NEXT:     LSHR * T3.W, PV.Y, 1,
1161; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
1162; EG-NEXT:     BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
1163; EG-NEXT:     LSHL T3.Y, T1.Y, PV.Z,
1164; EG-NEXT:     XOR_INT T1.Z, PV.X, PV.Y,
1165; EG-NEXT:     XOR_INT T1.W, T2.X, PV.Y,
1166; EG-NEXT:     SUB_INT * T2.W, literal.x, T2.W,
1167; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
1168; EG-NEXT:     AND_INT T1.X, T0.Z, literal.x,
1169; EG-NEXT:     AND_INT T4.Y, PS, literal.x,
1170; EG-NEXT:     BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
1171; EG-NEXT:     SUB_INT T1.W, PV.W, T2.Y,
1172; EG-NEXT:     SUBB_UINT * T2.W, PV.Z, T2.Y,
1173; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
1174; EG-NEXT:     SUB_INT T2.X, PV.W, PS,
1175; EG-NEXT:     CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
1176; EG-NEXT:     CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
1177; EG-NEXT:     CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
1178; EG-NEXT:     SETGT_INT * T2.W, T0.Y, literal.x,
1179; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
1180; EG-NEXT:     BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
1181; EG-NEXT:     AND_INT T3.Y, KC0[3].W, literal.y,
1182; EG-NEXT:     CNDE_INT T2.Z, PS, 0.0, PV.W,
1183; EG-NEXT:     CNDE_INT T1.W, PS, PV.Y, PV.Z,
1184; EG-NEXT:     ASHR * T2.W, KC0[3].Z, literal.z,
1185; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
1186; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
1187; EG-NEXT:     BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
1188; EG-NEXT:     XOR_INT T1.Y, PV.W, PS,
1189; EG-NEXT:     XOR_INT T0.Z, PV.Z, PS,
1190; EG-NEXT:     OR_INT T0.W, PV.Y, literal.y,
1191; EG-NEXT:     SUB_INT * T1.W, literal.z, PV.X,
1192; EG-NEXT:    23(3.222986e-44), 8388608(1.175494e-38)
1193; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
1194; EG-NEXT:     AND_INT T4.X, KC0[3].Y, literal.x,
1195; EG-NEXT:     AND_INT T3.Y, PS, literal.y,
1196; EG-NEXT:     BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
1197; EG-NEXT:     SUB_INT T1.W, PV.Z, T2.W,
1198; EG-NEXT:     SUBB_UINT * T3.W, PV.Y, T2.W,
1199; EG-NEXT:    8388607(1.175494e-38), 32(4.484155e-44)
1200; EG-NEXT:     SUB_INT T5.X, PV.W, PS,
1201; EG-NEXT:     SETGT_INT T0.Y, T0.Y, literal.x,
1202; EG-NEXT:     CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
1203; EG-NEXT:     OR_INT T1.W, PV.X, literal.y,
1204; EG-NEXT:     ADD_INT * T3.W, T3.X, literal.z,
1205; EG-NEXT:    -1(nan), 8388608(1.175494e-38)
1206; EG-NEXT:    -150(nan), 0(0.000000e+00)
1207; EG-NEXT:     ADD_INT T4.X, T3.X, literal.x,
1208; EG-NEXT:     SUB_INT T3.Y, literal.y, T3.X,
1209; EG-NEXT:     AND_INT T2.Z, PS, literal.z,
1210; EG-NEXT:     NOT_INT T4.W, PS,
1211; EG-NEXT:     LSHR * T5.W, PV.W, 1,
1212; EG-NEXT:    -127(nan), 150(2.101948e-43)
1213; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
1214; EG-NEXT:     BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
1215; EG-NEXT:     LSHL T4.Y, T1.W, PV.Z,
1216; EG-NEXT:     AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
1217; EG-NEXT:     BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
1218; EG-NEXT:     AND_INT * T3.W, PV.Y, literal.x,
1219; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
1220; EG-NEXT:     ADD_INT T6.X, T1.X, literal.x,
1221; EG-NEXT:     CNDE_INT * T3.Y, PS, PV.W, 0.0,
1222; EG-NEXT:    -150(nan), 0(0.000000e+00)
1223; EG-NEXT:    ALU clause starting at 108:
1224; EG-NEXT:     CNDE_INT T3.Z, T2.Z, T4.Y, 0.0,
1225; EG-NEXT:     CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
1226; EG-NEXT:     SETGT_INT * T3.W, T4.X, literal.x,
1227; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
1228; EG-NEXT:     CNDE_INT T3.X, PS, 0.0, PV.W,
1229; EG-NEXT:     CNDE_INT T3.Y, PS, T3.Y, PV.Z,
1230; EG-NEXT:     AND_INT T2.Z, T6.X, literal.x,
1231; EG-NEXT:     NOT_INT T1.W, T6.X,
1232; EG-NEXT:     LSHR * T3.W, T0.W, 1,
1233; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
1234; EG-NEXT:     ASHR T7.X, KC0[3].Y, literal.x,
1235; EG-NEXT:     ADD_INT T4.Y, T1.X, literal.y,
1236; EG-NEXT:     BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
1237; EG-NEXT:     LSHL T0.W, T0.W, PV.Z,
1238; EG-NEXT:     AND_INT * T1.W, T6.X, literal.z,
1239; EG-NEXT:    31(4.344025e-44), -127(nan)
1240; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
1241; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
1242; EG-NEXT:     CNDE_INT T5.Y, PS, PV.Z, PV.W,
1243; EG-NEXT:     SETGT_INT T2.Z, PV.Y, literal.x,
1244; EG-NEXT:     XOR_INT T0.W, T3.Y, PV.X,
1245; EG-NEXT:     XOR_INT * T1.W, T3.X, PV.X,
1246; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
1247; EG-NEXT:     SUB_INT T3.X, PS, T7.X,
1248; EG-NEXT:     SUBB_UINT T3.Y, PV.W, T7.X,
1249; EG-NEXT:     CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
1250; EG-NEXT:     CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
1251; EG-NEXT:     ASHR * T3.W, KC0[3].W, literal.x,
1252; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
1253; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
1254; EG-NEXT:     XOR_INT T5.Y, PV.Z, PS,
1255; EG-NEXT:     SUB_INT T0.Z, PV.X, PV.Y,
1256; EG-NEXT:     SETGT_INT T1.W, T4.X, literal.x,
1257; EG-NEXT:     CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122
1258; EG-NEXT:    -1(nan), 0(0.000000e+00)
1259; EG-NEXT:     SETGT_INT T0.X, T0.X, literal.x,
1260; EG-NEXT:     CNDE_INT T6.Y, PV.W, 0.0, PV.Z,
1261; EG-NEXT:     SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
1262; EG-NEXT:     SUB_INT T2.W, PV.Y, T3.W,
1263; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T3.W,
1264; EG-NEXT:    -1(nan), 0(0.000000e+00)
1265; EG-NEXT:     SUB_INT T3.X, PV.W, PS,
1266; EG-NEXT:     SETGT_INT T1.Y, T4.Y, literal.x,
1267; EG-NEXT:     CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212
1268; EG-NEXT:     SUB_INT T0.W, T0.W, T7.X,
1269; EG-NEXT:     CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122
1270; EG-NEXT:    -1(nan), 0(0.000000e+00)
1271; EG-NEXT:     CNDE_INT T6.X, T1.W, 0.0, PV.W,
1272; EG-NEXT:     CNDE_INT T4.Y, PV.Y, 0.0, PV.X,
1273; EG-NEXT:     SUB_INT T0.W, T1.Z, T2.Y,
1274; EG-NEXT:     LSHR * T2.X, KC0[2].Y, literal.x,
1275; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1276; EG-NEXT:     CNDE_INT T4.Z, T0.X, 0.0, PV.W,
1277; EG-NEXT:     SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
1278; EG-NEXT:     CNDE_INT T4.X, T1.Y, 0.0, PV.W,
1279; EG-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
1280; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
1281; EG-NEXT:     LSHR * T0.X, PV.W, literal.x,
1282; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1283  %conv = fptoui <4 x float> %x to <4 x i64>
1284  store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
1285  ret void
1286}
1287
1288define amdgpu_kernel void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
1289; SI-LABEL: fp_to_uint_f32_to_i1:
1290; SI:       ; %bb.0:
1291; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
1292; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1293; SI-NEXT:    s_mov_b32 s3, 0xf000
1294; SI-NEXT:    s_mov_b32 s2, -1
1295; SI-NEXT:    s_waitcnt lgkmcnt(0)
1296; SI-NEXT:    v_cmp_eq_f32_e64 s[4:5], 1.0, s4
1297; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1298; SI-NEXT:    buffer_store_byte v0, off, s[0:3], 0
1299; SI-NEXT:    s_endpgm
1300;
1301; VI-LABEL: fp_to_uint_f32_to_i1:
1302; VI:       ; %bb.0:
1303; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
1304; VI-NEXT:    s_load_dword s0, s[0:1], 0x2c
1305; VI-NEXT:    s_mov_b32 s7, 0xf000
1306; VI-NEXT:    s_mov_b32 s6, -1
1307; VI-NEXT:    s_waitcnt lgkmcnt(0)
1308; VI-NEXT:    v_cmp_eq_f32_e64 s[0:1], 1.0, s0
1309; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
1310; VI-NEXT:    buffer_store_byte v0, off, s[4:7], 0
1311; VI-NEXT:    s_endpgm
1312;
1313; EG-LABEL: fp_to_uint_f32_to_i1:
1314; EG:       ; %bb.0:
1315; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
1316; EG-NEXT:    MEM_RAT MSKOR T0.XW, T1.X
1317; EG-NEXT:    CF_END
1318; EG-NEXT:    PAD
1319; EG-NEXT:    ALU clause starting at 4:
1320; EG-NEXT:     AND_INT T0.W, KC0[2].Y, literal.x,
1321; EG-NEXT:     SETE_DX10 * T1.W, KC0[2].Z, 1.0,
1322; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
1323; EG-NEXT:     AND_INT T1.W, PS, 1,
1324; EG-NEXT:     LSHL * T0.W, PV.W, literal.x,
1325; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
1326; EG-NEXT:     LSHL T0.X, PV.W, PS,
1327; EG-NEXT:     LSHL * T0.W, literal.x, PS,
1328; EG-NEXT:    255(3.573311e-43), 0(0.000000e+00)
1329; EG-NEXT:     MOV T0.Y, 0.0,
1330; EG-NEXT:     MOV * T0.Z, 0.0,
1331; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
1332; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1333  %conv = fptoui float %in to i1
1334  store i1 %conv, i1 addrspace(1)* %out
1335  ret void
1336}
1337
1338define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
1339; SI-LABEL: fp_to_uint_fabs_f32_to_i1:
1340; SI:       ; %bb.0:
1341; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
1342; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1343; SI-NEXT:    s_mov_b32 s3, 0xf000
1344; SI-NEXT:    s_mov_b32 s2, -1
1345; SI-NEXT:    s_waitcnt lgkmcnt(0)
1346; SI-NEXT:    v_cmp_eq_f32_e64 s[4:5], 1.0, |s4|
1347; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1348; SI-NEXT:    buffer_store_byte v0, off, s[0:3], 0
1349; SI-NEXT:    s_endpgm
1350;
1351; VI-LABEL: fp_to_uint_fabs_f32_to_i1:
1352; VI:       ; %bb.0:
1353; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
1354; VI-NEXT:    s_load_dword s0, s[0:1], 0x2c
1355; VI-NEXT:    s_mov_b32 s7, 0xf000
1356; VI-NEXT:    s_mov_b32 s6, -1
1357; VI-NEXT:    s_waitcnt lgkmcnt(0)
1358; VI-NEXT:    v_cmp_eq_f32_e64 s[0:1], 1.0, |s0|
1359; VI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
1360; VI-NEXT:    buffer_store_byte v0, off, s[4:7], 0
1361; VI-NEXT:    s_endpgm
1362;
1363; EG-LABEL: fp_to_uint_fabs_f32_to_i1:
1364; EG:       ; %bb.0:
1365; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
1366; EG-NEXT:    MEM_RAT MSKOR T0.XW, T1.X
1367; EG-NEXT:    CF_END
1368; EG-NEXT:    PAD
1369; EG-NEXT:    ALU clause starting at 4:
1370; EG-NEXT:     AND_INT T0.W, KC0[2].Y, literal.x,
1371; EG-NEXT:     SETE_DX10 * T1.W, |KC0[2].Z|, 1.0,
1372; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
1373; EG-NEXT:     AND_INT T1.W, PS, 1,
1374; EG-NEXT:     LSHL * T0.W, PV.W, literal.x,
1375; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
1376; EG-NEXT:     LSHL T0.X, PV.W, PS,
1377; EG-NEXT:     LSHL * T0.W, literal.x, PS,
1378; EG-NEXT:    255(3.573311e-43), 0(0.000000e+00)
1379; EG-NEXT:     MOV T0.Y, 0.0,
1380; EG-NEXT:     MOV * T0.Z, 0.0,
1381; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
1382; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1383  %in.fabs = call float @llvm.fabs.f32(float %in)
1384  %conv = fptoui float %in.fabs to i1
1385  store i1 %conv, i1 addrspace(1)* %out
1386  ret void
1387}
1388
1389define amdgpu_kernel void @fp_to_uint_f32_to_i16(i16 addrspace(1)* %out, float %in) #0 {
1390; SI-LABEL: fp_to_uint_f32_to_i16:
1391; SI:       ; %bb.0:
1392; SI-NEXT:    s_load_dword s4, s[0:1], 0xb
1393; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1394; SI-NEXT:    s_mov_b32 s3, 0xf000
1395; SI-NEXT:    s_mov_b32 s2, -1
1396; SI-NEXT:    s_waitcnt lgkmcnt(0)
1397; SI-NEXT:    v_cvt_u32_f32_e32 v0, s4
1398; SI-NEXT:    buffer_store_short v0, off, s[0:3], 0
1399; SI-NEXT:    s_endpgm
1400;
1401; VI-LABEL: fp_to_uint_f32_to_i16:
1402; VI:       ; %bb.0:
1403; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
1404; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
1405; VI-NEXT:    s_mov_b32 s3, 0xf000
1406; VI-NEXT:    s_waitcnt lgkmcnt(0)
1407; VI-NEXT:    v_cvt_u32_f32_e32 v0, s2
1408; VI-NEXT:    s_mov_b32 s2, -1
1409; VI-NEXT:    buffer_store_short v0, off, s[0:3], 0
1410; VI-NEXT:    s_endpgm
1411;
1412; EG-LABEL: fp_to_uint_f32_to_i16:
1413; EG:       ; %bb.0:
1414; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
1415; EG-NEXT:    MEM_RAT MSKOR T0.XW, T1.X
1416; EG-NEXT:    CF_END
1417; EG-NEXT:    PAD
1418; EG-NEXT:    ALU clause starting at 4:
1419; EG-NEXT:     TRUNC T0.W, KC0[2].Z,
1420; EG-NEXT:     AND_INT * T1.W, KC0[2].Y, literal.x,
1421; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
1422; EG-NEXT:     LSHL T1.W, PS, literal.x,
1423; EG-NEXT:     FLT_TO_UINT * T0.X, PV.W,
1424; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
1425; EG-NEXT:     LSHL T0.X, PS, PV.W,
1426; EG-NEXT:     LSHL * T0.W, literal.x, PV.W,
1427; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
1428; EG-NEXT:     MOV T0.Y, 0.0,
1429; EG-NEXT:     MOV * T0.Z, 0.0,
1430; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
1431; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
1432  %uint = fptoui float %in to i16
1433  store i16 %uint, i16 addrspace(1)* %out
1434  ret void
1435}
1436
1437attributes #0 = { nounwind }
1438attributes #1 = { nounwind readnone }
1439