1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=kaveri -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI,GFX89 %s 3; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx901 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s 4 5; FIXME: Should be able to do scalar op 6; GCN-LABEL: {{^}}s_fneg_f16: 7define amdgpu_kernel void @s_fneg_f16(half addrspace(1)* %out, half %in) #0 { 8 %fneg = fsub half -0.0, %in 9 store half %fneg, half addrspace(1)* %out 10 ret void 11} 12 13; FIXME: Should be able to use bit operations when illegal type as 14; well. 15 16; GCN-LABEL: {{^}}v_fneg_f16: 17; GCN: {{flat|global}}_load_ushort [[VAL:v[0-9]+]], 18; GCN: v_xor_b32_e32 [[XOR:v[0-9]+]], 0x8000, [[VAL]] 19; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[XOR]] 20; SI: buffer_store_short [[XOR]] 21define amdgpu_kernel void @v_fneg_f16(half addrspace(1)* %out, half addrspace(1)* %in) #0 { 22 %tid = call i32 @llvm.amdgcn.workitem.id.x() 23 %gep.in = getelementptr inbounds half, half addrspace(1)* %in, i32 %tid 24 %gep.out = getelementptr inbounds half, half addrspace(1)* %in, i32 %tid 25 %val = load half, half addrspace(1)* %gep.in, align 2 26 %fneg = fsub half -0.0, %val 27 store half %fneg, half addrspace(1)* %gep.out 28 ret void 29} 30 31; GCN-LABEL: {{^}}fneg_free_f16: 32; GCN: {{flat|global}}_load_ushort [[NEG_VALUE:v[0-9]+]], 33 34; XCI: s_xor_b32 [[XOR:s[0-9]+]], [[NEG_VALUE]], 0x8000{{$}} 35; CI: v_xor_b32_e32 [[XOR:v[0-9]+]], 0x8000, [[NEG_VALUE]] 36; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[XOR]] 37define amdgpu_kernel void @fneg_free_f16(half addrspace(1)* %out, i16 %in) #0 { 38 %bc = bitcast i16 %in to half 39 %fsub = fsub half -0.0, %bc 40 store half %fsub, half addrspace(1)* %out 41 ret void 42} 43 44; GCN-LABEL: {{^}}v_fneg_fold_f16: 45; GCN: {{flat|global}}_load_ushort [[NEG_VALUE:v[0-9]+]] 46 47; CI-DAG: v_cvt_f32_f16_e32 [[CVT_VAL:v[0-9]+]], [[NEG_VALUE]] 48; CI-DAG: v_cvt_f32_f16_e64 [[NEG_CVT0:v[0-9]+]], -[[NEG_VALUE]] 49; CI: v_mul_f32_e32 [[MUL:v[0-9]+]], [[NEG_CVT0]], [[CVT_VAL]] 50; CI: v_cvt_f16_f32_e32 [[CVT1:v[0-9]+]], [[MUL]] 51; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[CVT1]] 52 53; VI-NOT: [[NEG_VALUE]] 54; VI: v_mul_f16_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]] 55define amdgpu_kernel void @v_fneg_fold_f16(half addrspace(1)* %out, half addrspace(1)* %in) #0 { 56 %val = load half, half addrspace(1)* %in 57 %fsub = fsub half -0.0, %val 58 %fmul = fmul half %fsub, %val 59 store half %fmul, half addrspace(1)* %out 60 ret void 61} 62 63; FIXME: Terrible code with VI and even worse with SI/CI 64; GCN-LABEL: {{^}}s_fneg_v2f16: 65; CI: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}} 66; CI: v_xor_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} 67; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} 68; CI: v_xor_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} 69; CI: v_or_b32_e32 70 71; VI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x8000{{$}} 72; VI-DAG: v_xor_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[MASK]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD 73; VI-DAG: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[MASK]] 74 75; GFX9: v_xor_b32_e32 v{{[0-9]+}}, 0x80008000, v{{[0-9]+}} 76 77define amdgpu_kernel void @s_fneg_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) #0 { 78 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in 79 store <2 x half> %fneg, <2 x half> addrspace(1)* %out 80 ret void 81} 82 83; GCN-LABEL: {{^}}v_fneg_v2f16: 84; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]] 85; GCN: v_xor_b32_e32 v{{[0-9]+}}, 0x80008000, [[VAL]] 86define amdgpu_kernel void @v_fneg_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 87 %tid = call i32 @llvm.amdgcn.workitem.id.x() 88 %gep.in = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid 89 %gep.out = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid 90 %val = load <2 x half>, <2 x half> addrspace(1)* %gep.in, align 2 91 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val 92 store <2 x half> %fneg, <2 x half> addrspace(1)* %gep.out 93 ret void 94} 95 96; GCN-LABEL: {{^}}fneg_free_v2f16: 97; GCN: s_load_dword [[VAL:s[0-9]+]] 98; CIVI: s_xor_b32 s{{[0-9]+}}, [[VAL]], 0x80008000 99 100; GFX9: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] 101; GFX9: v_xor_b32_e32 v{{[0-9]+}}, 0x80008000, [[VVAL]] 102define amdgpu_kernel void @fneg_free_v2f16(<2 x half> addrspace(1)* %out, i32 %in) #0 { 103 %bc = bitcast i32 %in to <2 x half> 104 %fsub = fsub <2 x half> <half -0.0, half -0.0>, %bc 105 store <2 x half> %fsub, <2 x half> addrspace(1)* %out 106 ret void 107} 108 109; GCN-LABEL: {{^}}v_fneg_fold_v2f16: 110; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]] 111 112; CI: v_cvt_f32_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}} 113; CI: v_cvt_f32_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}} 114; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 115; CI: v_cvt_f16_f32 116; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 117; CI: v_cvt_f16_f32 118 119; VI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, 120; VI: v_mul_f16_sdwa v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 121; VI: v_mul_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} 122 123; GFX9: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,0] neg_hi:[1,0]{{$}} 124define amdgpu_kernel void @v_fneg_fold_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 125 %val = load <2 x half>, <2 x half> addrspace(1)* %in 126 %fsub = fsub <2 x half> <half -0.0, half -0.0>, %val 127 %fmul = fmul <2 x half> %fsub, %val 128 store <2 x half> %fmul, <2 x half> addrspace(1)* %out 129 ret void 130} 131 132; GCN-LABEL: {{^}}v_extract_fneg_fold_v2f16: 133; GCN-DAG: {{flat|global}}_load_dword [[VAL:v[0-9]+]] 134; CI-DAG: v_mul_f32_e32 v{{[0-9]+}}, -4.0, v{{[0-9]+}} 135; CI-DAG: v_sub_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} 136 137; GFX89-DAG: v_mul_f16_e32 v{{[0-9]+}}, -4.0, [[VAL]] 138; GFX89-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 0x4000 139; GFX89-DAG: v_sub_f16_sdwa v{{[0-9]+}}, [[CONST2]], [[VAL]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 140 141define amdgpu_kernel void @v_extract_fneg_fold_v2f16(<2 x half> addrspace(1)* %in) #0 { 142 %val = load <2 x half>, <2 x half> addrspace(1)* %in 143 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val 144 %elt0 = extractelement <2 x half> %fneg, i32 0 145 %elt1 = extractelement <2 x half> %fneg, i32 1 146 147 %fmul0 = fmul half %elt0, 4.0 148 %fadd1 = fadd half %elt1, 2.0 149 store volatile half %fmul0, half addrspace(1)* undef 150 store volatile half %fadd1, half addrspace(1)* undef 151 ret void 152} 153 154; GCN-LABEL: {{^}}v_extract_fneg_no_fold_v2f16: 155; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]] 156; GCN: v_xor_b32_e32 [[NEG:v[0-9]+]], 0x80008000, [[VAL]] 157; CIVI: v_lshrrev_b32_e32 [[ELT1:v[0-9]+]], 16, [[NEG]] 158; GFX9: global_store_short_d16_hi v{{\[[0-9]+:[0-9]+\]}}, [[NEG]], off 159define amdgpu_kernel void @v_extract_fneg_no_fold_v2f16(<2 x half> addrspace(1)* %in) #0 { 160 %val = load <2 x half>, <2 x half> addrspace(1)* %in 161 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val 162 %elt0 = extractelement <2 x half> %fneg, i32 0 163 %elt1 = extractelement <2 x half> %fneg, i32 1 164 store volatile half %elt0, half addrspace(1)* undef 165 store volatile half %elt1, half addrspace(1)* undef 166 ret void 167} 168 169declare i32 @llvm.amdgcn.workitem.id.x() #1 170 171attributes #0 = { nounwind } 172attributes #1 = { nounwind readnone } 173