1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s 2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s 3 4; GCN-LABEL: {{^}}fneg_fabs_fadd_f16: 5; CI: v_cvt_f32_f16_e32 6; CI: v_cvt_f32_f16_e32 7; CI: v_sub_f32_e64 v{{[0-9]+}}, v{{[0-9]+}}, |v{{[0-9]+}}| 8 9; VI-NOT: and 10; VI: v_sub_f16_e64 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}| 11define void @fneg_fabs_fadd_f16(half addrspace(1)* %out, half %x, half %y) { 12 %fabs = call half @llvm.fabs.f16(half %x) 13 %fsub = fsub half -0.000000e+00, %fabs 14 %fadd = fadd half %y, %fsub 15 store half %fadd, half addrspace(1)* %out, align 2 16 ret void 17} 18 19; GCN-LABEL: {{^}}fneg_fabs_fmul_f16: 20; CI: v_cvt_f32_f16_e32 21; CI: v_cvt_f32_f16_e32 22; CI: v_mul_f32_e64 {{v[0-9]+}}, {{v[0-9]+}}, -|{{v[0-9]+}}| 23; CI: v_cvt_f16_f32_e32 24 25; VI-NOT: and 26; VI: v_mul_f16_e64 {{v[0-9]+}}, {{v[0-9]+}}, -|{{v[0-9]+}}| 27; VI-NOT: and 28define void @fneg_fabs_fmul_f16(half addrspace(1)* %out, half %x, half %y) { 29 %fabs = call half @llvm.fabs.f16(half %x) 30 %fsub = fsub half -0.000000e+00, %fabs 31 %fmul = fmul half %y, %fsub 32 store half %fmul, half addrspace(1)* %out, align 2 33 ret void 34} 35 36; DAGCombiner will transform: 37; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF)) 38; unless isFabsFree returns true 39 40; GCN-LABEL: {{^}}fneg_fabs_free_f16: 41; GCN: v_or_b32_e32 v{{[0-9]+}}, 0x8000, v{{[0-9]+}} 42define void @fneg_fabs_free_f16(half addrspace(1)* %out, i16 %in) { 43 %bc = bitcast i16 %in to half 44 %fabs = call half @llvm.fabs.f16(half %bc) 45 %fsub = fsub half -0.000000e+00, %fabs 46 store half %fsub, half addrspace(1)* %out 47 ret void 48} 49 50; FIXME: Should use or 51; GCN-LABEL: {{^}}fneg_fabs_f16: 52; CI: v_cvt_f32_f16_e32 v{{[0-9]+}}, 53; CI: v_cvt_f16_f32_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| 54 55; VI: v_or_b32_e32 v{{[0-9]+}}, 0x8000, v{{[0-9]+}} 56define void @fneg_fabs_f16(half addrspace(1)* %out, half %in) { 57 %fabs = call half @llvm.fabs.f16(half %in) 58 %fsub = fsub half -0.000000e+00, %fabs 59 store half %fsub, half addrspace(1)* %out, align 2 60 ret void 61} 62 63; GCN-LABEL: {{^}}v_fneg_fabs_f16: 64; CI: v_cvt_f32_f16_e32 v{{[0-9]+}}, 65; CI: v_cvt_f16_f32_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| 66 67; VI: v_or_b32_e32 v{{[0-9]+}}, 0x8000, v{{[0-9]+}} 68define void @v_fneg_fabs_f16(half addrspace(1)* %out, half addrspace(1)* %in) { 69 %val = load half, half addrspace(1)* %in, align 2 70 %fabs = call half @llvm.fabs.f16(half %val) 71 %fsub = fsub half -0.000000e+00, %fabs 72 store half %fsub, half addrspace(1)* %out, align 2 73 ret void 74} 75 76; FIXME: single bit op 77; GCN-LABEL: {{^}}fneg_fabs_v2f16: 78; CI: v_cvt_f16_f32_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| 79; CI: v_cvt_f16_f32_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| 80 81; VI: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}} 82; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], 83; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], 84; VI: flat_store_dword 85define void @fneg_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) { 86 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) 87 %fsub = fsub <2 x half> <half -0.000000e+00, half -0.000000e+00>, %fabs 88 store <2 x half> %fsub, <2 x half> addrspace(1)* %out 89 ret void 90} 91 92; GCN-LABEL: {{^}}fneg_fabs_v4f16: 93; CI: v_cvt_f16_f32_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| 94; CI: v_cvt_f16_f32_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| 95; CI: v_cvt_f16_f32_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| 96; CI: v_cvt_f16_f32_e64 v{{[0-9]+}}, -|v{{[0-9]+}}| 97 98; VI: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}} 99; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], 100; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], 101; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], 102; VI: v_or_b32_e32 v{{[0-9]+}}, [[MASK]], 103; VI: flat_store_dwordx2 104define void @fneg_fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) { 105 %fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in) 106 %fsub = fsub <4 x half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00>, %fabs 107 store <4 x half> %fsub, <4 x half> addrspace(1)* %out 108 ret void 109} 110 111declare half @llvm.fabs.f16(half) readnone 112declare <2 x half> @llvm.fabs.v2f16(<2 x half>) readnone 113declare <4 x half> @llvm.fabs.v4f16(<4 x half>) readnone 114