1; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3
4declare double @llvm.minnum.f64(double, double) #0
5declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>) #0
6declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>) #0
7declare <8 x double> @llvm.minnum.v8f64(<8 x double>, <8 x double>) #0
8declare <16 x double> @llvm.minnum.v16f64(<16 x double>, <16 x double>) #0
9
10; FUNC-LABEL: {{^}}test_fmin_f64_ieee:
11; SI: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]]
12; SI: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]]
13; SI-DAG: v_max_f64 [[QUIETA:v\[[0-9]+:[0-9]+\]]], [[A]], [[A]]
14; SI-DAG: v_max_f64 [[QUIETB:v\[[0-9]+:[0-9]+\]]], [[B]], [[B]]
15; SI: v_min_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[QUIETA]], [[QUIETB]]
16define amdgpu_kernel void @test_fmin_f64_ieee([8 x i32], double %a, [8 x i32], double %b) nounwind {
17  %val = call double @llvm.minnum.f64(double %a, double %b) #0
18  store double %val, double addrspace(1)* undef, align 8
19  ret void
20}
21
22; FUNC-LABEL: {{^}}test_fmin_f64_no_ieee:
23; SI: ds_read_b64 [[VAL0:v\[[0-9]+:[0-9]+\]]]
24; SI: ds_read_b64 [[VAL1:v\[[0-9]+:[0-9]+\]]]
25; SI-NOT: [[VAL0]]
26; SI-NOT: [[VAL1]]
27; SI: v_min_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VAL0]], [[VAL1]]
28; SI-NOT: [[RESULT]]
29; SI: ds_write_b64 v{{[0-9]+}}, [[RESULT]]
30define amdgpu_ps void @test_fmin_f64_no_ieee() nounwind {
31  %a = load volatile double, double addrspace(3)* undef
32  %b = load volatile double, double addrspace(3)* undef
33  %val = call double @llvm.minnum.f64(double %a, double %b) #0
34  store volatile double %val, double addrspace(3)* undef
35  ret void
36}
37
38; FUNC-LABEL: {{^}}test_fmin_v2f64:
39; SI: v_min_f64
40; SI: v_min_f64
41define amdgpu_kernel void @test_fmin_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind {
42  %val = call <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b) #0
43  store <2 x double> %val, <2 x double> addrspace(1)* %out, align 16
44  ret void
45}
46
47; FUNC-LABEL: {{^}}test_fmin_v4f64:
48; SI: v_min_f64
49; SI: v_min_f64
50; SI: v_min_f64
51; SI: v_min_f64
52define amdgpu_kernel void @test_fmin_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind {
53  %val = call <4 x double> @llvm.minnum.v4f64(<4 x double> %a, <4 x double> %b) #0
54  store <4 x double> %val, <4 x double> addrspace(1)* %out, align 32
55  ret void
56}
57
58; FUNC-LABEL: {{^}}test_fmin_v8f64:
59; SI: v_min_f64
60; SI: v_min_f64
61; SI: v_min_f64
62; SI: v_min_f64
63; SI: v_min_f64
64; SI: v_min_f64
65; SI: v_min_f64
66; SI: v_min_f64
67define amdgpu_kernel void @test_fmin_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind {
68  %val = call <8 x double> @llvm.minnum.v8f64(<8 x double> %a, <8 x double> %b) #0
69  store <8 x double> %val, <8 x double> addrspace(1)* %out, align 64
70  ret void
71}
72
73; FUNC-LABEL: {{^}}test_fmin_v16f64:
74; SI: v_min_f64
75; SI: v_min_f64
76; SI: v_min_f64
77; SI: v_min_f64
78; SI: v_min_f64
79; SI: v_min_f64
80; SI: v_min_f64
81; SI: v_min_f64
82; SI: v_min_f64
83; SI: v_min_f64
84; SI: v_min_f64
85; SI: v_min_f64
86; SI: v_min_f64
87; SI: v_min_f64
88; SI: v_min_f64
89; SI: v_min_f64
90define amdgpu_kernel void @test_fmin_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind {
91  %val = call <16 x double> @llvm.minnum.v16f64(<16 x double> %a, <16 x double> %b) #0
92  store <16 x double> %val, <16 x double> addrspace(1)* %out, align 128
93  ret void
94}
95
96attributes #0 = { nounwind readnone }
97