1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
3; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
4
5; GCN-LABEL: {{^}}test_fmin3_olt_0_f32:
6; GCN: buffer_load_dword [[REGC:v[0-9]+]]
7; GCN: buffer_load_dword [[REGB:v[0-9]+]]
8; GCN: buffer_load_dword [[REGA:v[0-9]+]]
9; GCN: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
10; GCN: buffer_store_dword [[RESULT]],
11define amdgpu_kernel void @test_fmin3_olt_0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
12  %a = load volatile float, float addrspace(1)* %aptr, align 4
13  %b = load volatile float, float addrspace(1)* %bptr, align 4
14  %c = load volatile float, float addrspace(1)* %cptr, align 4
15  %f0 = call float @llvm.minnum.f32(float %a, float %b)
16  %f1 = call float @llvm.minnum.f32(float %f0, float %c)
17  store float %f1, float addrspace(1)* %out, align 4
18  ret void
19}
20
21; Commute operand of second fmin
22; GCN-LABEL: {{^}}test_fmin3_olt_1_f32:
23; GCN: buffer_load_dword [[REGB:v[0-9]+]]
24; GCN: buffer_load_dword [[REGA:v[0-9]+]]
25; GCN: buffer_load_dword [[REGC:v[0-9]+]]
26; GCN: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
27; GCN: buffer_store_dword [[RESULT]],
28define amdgpu_kernel void @test_fmin3_olt_1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
29  %a = load volatile float, float addrspace(1)* %aptr, align 4
30  %b = load volatile float, float addrspace(1)* %bptr, align 4
31  %c = load volatile float, float addrspace(1)* %cptr, align 4
32  %f0 = call float @llvm.minnum.f32(float %a, float %b)
33  %f1 = call float @llvm.minnum.f32(float %c, float %f0)
34  store float %f1, float addrspace(1)* %out, align 4
35  ret void
36}
37
38; GCN-LABEL: {{^}}test_fmin3_olt_0_f16:
39; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
40; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
41; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
42
43; SI: v_min3_f32 [[RESULT_F32:v[0-9]+]],
44; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
45
46; VI: v_min_f16_e32
47; VI: v_min_f16_e32 [[RESULT:v[0-9]+]],
48
49; GFX9: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
50; GCN: buffer_store_short [[RESULT]],
51define amdgpu_kernel void @test_fmin3_olt_0_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
52  %a = load volatile half, half addrspace(1)* %aptr, align 2
53  %b = load volatile half, half addrspace(1)* %bptr, align 2
54  %c = load volatile half, half addrspace(1)* %cptr, align 2
55  %f0 = call half @llvm.minnum.f16(half %a, half %b)
56  %f1 = call half @llvm.minnum.f16(half %f0, half %c)
57  store half %f1, half addrspace(1)* %out, align 2
58  ret void
59}
60
61; Commute operand of second fmin
62; GCN-LABEL: {{^}}test_fmin3_olt_1_f16:
63; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
64; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
65; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
66
67; SI: v_min3_f32 [[RESULT_F32:v[0-9]+]],
68; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
69
70; VI: v_min_f16_e32
71; VI: v_min_f16_e32 [[RESULT:v[0-9]+]],
72
73; GFX9: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
74; GCN: buffer_store_short [[RESULT]],
75define amdgpu_kernel void @test_fmin3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
76  %a = load volatile half, half addrspace(1)* %aptr, align 2
77  %b = load volatile half, half addrspace(1)* %bptr, align 2
78  %c = load volatile half, half addrspace(1)* %cptr, align 2
79  %f0 = call half @llvm.minnum.f16(half %a, half %b)
80  %f1 = call half @llvm.minnum.f16(half %c, half %f0)
81  store half %f1, half addrspace(1)* %out, align 2
82  ret void
83}
84
85declare i32 @llvm.amdgcn.workitem.id.x() #1
86declare float @llvm.minnum.f32(float, float) #1
87declare half @llvm.minnum.f16(half, half) #1
88
89attributes #0 = { nounwind }
90attributes #1 = { nounwind readnone speculatable }
91