1; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
3; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=cedar -verify-machineinstrs < %s
4; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=juniper -verify-machineinstrs < %s
5; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=redwood -verify-machineinstrs < %s
6; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=sumo -verify-machineinstrs < %s
7; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=barts -verify-machineinstrs < %s
8; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=caicos -verify-machineinstrs < %s
9; RUN:  not llc -amdgpu-scalarize-global-loads=false  -march=r600 -mcpu=turks -verify-machineinstrs < %s
10
11declare float @llvm.fma.f32(float, float, float) nounwind readnone
12declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
13declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
14
15declare i32 @llvm.r600.read.tidig.x() nounwind readnone
16
17; FUNC-LABEL: {{^}}fma_f32:
18; SI: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
19
20; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}},
21; EG: FMA {{\*? *}}[[RES]]
22define amdgpu_kernel void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
23                     float addrspace(1)* %in2, float addrspace(1)* %in3) {
24  %r0 = load float, float addrspace(1)* %in1
25  %r1 = load float, float addrspace(1)* %in2
26  %r2 = load float, float addrspace(1)* %in3
27  %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
28  store float %r3, float addrspace(1)* %out
29  ret void
30}
31
32; FUNC-LABEL: {{^}}fma_v2f32:
33; SI: v_fma_f32
34; SI: v_fma_f32
35
36; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].[[CHLO:[XYZW]]][[CHHI:[XYZW]]], {{T[0-9]\.[XYZW]}},
37; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]]
38; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]]
39define amdgpu_kernel void @fma_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in1,
40                       <2 x float> addrspace(1)* %in2, <2 x float> addrspace(1)* %in3) {
41  %r0 = load <2 x float>, <2 x float> addrspace(1)* %in1
42  %r1 = load <2 x float>, <2 x float> addrspace(1)* %in2
43  %r2 = load <2 x float>, <2 x float> addrspace(1)* %in3
44  %r3 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %r0, <2 x float> %r1, <2 x float> %r2)
45  store <2 x float> %r3, <2 x float> addrspace(1)* %out
46  ret void
47}
48
49; FUNC-LABEL: {{^}}fma_v4f32:
50; SI: v_fma_f32
51; SI: v_fma_f32
52; SI: v_fma_f32
53; SI: v_fma_f32
54
55; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].{{[XYZW][XYZW][XYZW][XYZW]}}, {{T[0-9]\.[XYZW]}},
56; EG-DAG: FMA {{\*? *}}[[RES]].X
57; EG-DAG: FMA {{\*? *}}[[RES]].Y
58; EG-DAG: FMA {{\*? *}}[[RES]].Z
59; EG-DAG: FMA {{\*? *}}[[RES]].W
60define amdgpu_kernel void @fma_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in1,
61                       <4 x float> addrspace(1)* %in2, <4 x float> addrspace(1)* %in3) {
62  %r0 = load <4 x float>, <4 x float> addrspace(1)* %in1
63  %r1 = load <4 x float>, <4 x float> addrspace(1)* %in2
64  %r2 = load <4 x float>, <4 x float> addrspace(1)* %in3
65  %r3 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %r0, <4 x float> %r1, <4 x float> %r2)
66  store <4 x float> %r3, <4 x float> addrspace(1)* %out
67  ret void
68}
69
70; FUNC-LABEL: @fma_commute_mul_inline_imm_f32
71; SI: v_fma_f32 {{v[0-9]+}}, {{v[0-9]+}}, 2.0, {{v[0-9]+}}
72define amdgpu_kernel void @fma_commute_mul_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
73  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
74  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
75  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
76  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
77
78  %a = load float, float addrspace(1)* %in.a.gep, align 4
79  %b = load float, float addrspace(1)* %in.b.gep, align 4
80
81  %fma = call float @llvm.fma.f32(float %a, float 2.0, float %b)
82  store float %fma, float addrspace(1)* %out.gep, align 4
83  ret void
84}
85
86; FUNC-LABEL: @fma_commute_mul_s_f32
87define amdgpu_kernel void @fma_commute_mul_s_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b, float %b) nounwind {
88  %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
89  %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid
90  %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid
91  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
92
93  %a = load float, float addrspace(1)* %in.a.gep, align 4
94  %c = load float, float addrspace(1)* %in.b.gep, align 4
95
96  %fma = call float @llvm.fma.f32(float %a, float %b, float %c)
97  store float %fma, float addrspace(1)* %out.gep, align 4
98  ret void
99}
100