1; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s 2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s 4 5; DAGCombiner will transform: 6; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF)) 7; unless isFabsFree returns true 8 9; GCN-LABEL: {{^}}s_fabs_free_f16: 10; GCN: flat_load_ushort [[VAL:v[0-9]+]], 11; GCN: v_and_b32_e32 [[RESULT:v[0-9]+]], 0x7fff, [[VAL]] 12; GCN: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 13 14define void @s_fabs_free_f16(half addrspace(1)* %out, i16 %in) { 15 %bc= bitcast i16 %in to half 16 %fabs = call half @llvm.fabs.f16(half %bc) 17 store half %fabs, half addrspace(1)* %out 18 ret void 19} 20 21; GCN-LABEL: {{^}}s_fabs_f16: 22; CI: flat_load_ushort [[VAL:v[0-9]+]], 23; CI: v_and_b32_e32 [[CVT0:v[0-9]+]], 0x7fff, [[VAL]] 24; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 25define void @s_fabs_f16(half addrspace(1)* %out, half %in) { 26 %fabs = call half @llvm.fabs.f16(half %in) 27 store half %fabs, half addrspace(1)* %out 28 ret void 29} 30 31; FIXME: Should be able to use single and 32; GCN-LABEL: {{^}}s_fabs_v2f16: 33; CI: s_movk_i32 [[MASK:s[0-9]+]], 0x7fff 34; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]] 35; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, 36; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]] 37; CI: v_or_b32_e32 38 39; VI: flat_load_ushort [[LO:v[0-9]+]] 40; VI: flat_load_ushort [[HI:v[0-9]+]] 41; VI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7fff{{$}} 42; VI-DAG: v_and_b32_e32 [[FABS_LO:v[0-9]+]], [[MASK]], [[LO]] 43; VI-DAG: v_and_b32_e32 [[FABS_LO:v[0-9]+]], [[MASK]], [[HI]] 44; VI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, 45; VI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffff, 46; VI: v_or_b32 47; VI: flat_store_dword 48 49; GFX9: s_load_dword [[VAL:s[0-9]+]] 50; GFX9: s_and_b32 s{{[0-9]+}}, [[VAL]], 0x7fff7fff 51define void @s_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) { 52 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) 53 store <2 x half> %fabs, <2 x half> addrspace(1)* %out 54 ret void 55} 56 57; GCN-LABEL: {{^}}s_fabs_v4f16: 58; CI: s_movk_i32 [[MASK:s[0-9]+]], 0x7fff 59; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]] 60; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]] 61; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]] 62; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]] 63 64; VI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7fff{{$}} 65; VI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} 66; VI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} 67; VI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} 68; VI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}} 69 70; GCN: flat_store_dwordx2 71define void @s_fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) { 72 %fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in) 73 store <4 x half> %fabs, <4 x half> addrspace(1)* %out 74 ret void 75} 76 77; GCN-LABEL: {{^}}fabs_fold_f16: 78; GCN: flat_load_ushort [[IN0:v[0-9]+]] 79; GCN: flat_load_ushort [[IN1:v[0-9]+]] 80 81; CI-DAG: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], [[IN0]] 82; CI-DAG: v_cvt_f32_f16_e64 [[ABS_CVT1:v[0-9]+]], |[[IN1]]| 83; CI: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[CVT0]], [[ABS_CVT1]] 84; CI: v_cvt_f16_f32_e32 [[CVTRESULT:v[0-9]+]], [[RESULT]] 85; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[CVTRESULT]] 86 87; VI-NOT: and 88; VI: v_mul_f16_e64 [[RESULT:v[0-9]+]], |[[IN1]]|, [[IN0]] 89; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] 90define void @fabs_fold_f16(half addrspace(1)* %out, half %in0, half %in1) { 91 %fabs = call half @llvm.fabs.f16(half %in0) 92 %fmul = fmul half %fabs, %in1 93 store half %fmul, half addrspace(1)* %out 94 ret void 95} 96 97; GCN-LABEL: {{^}}v_fabs_v2f16: 98; GCN: flat_load_dword [[VAL:v[0-9]+]] 99; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7fff7fff, [[VAL]] 100define void @v_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 101 %tid = call i32 @llvm.amdgcn.workitem.id.x() 102 %gep.in = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid 103 %gep.out = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid 104 %val = load <2 x half>, <2 x half> addrspace(1)* %gep.in, align 2 105 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val) 106 store <2 x half> %fabs, <2 x half> addrspace(1)* %gep.out 107 ret void 108} 109 110; GCN-LABEL: {{^}}fabs_free_v2f16: 111; GCN: s_load_dword [[VAL:s[0-9]+]] 112; GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0x7fff7fff 113define void @fabs_free_v2f16(<2 x half> addrspace(1)* %out, i32 %in) #0 { 114 %bc = bitcast i32 %in to <2 x half> 115 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %bc) 116 store <2 x half> %fabs, <2 x half> addrspace(1)* %out 117 ret void 118} 119 120; GCN-LABEL: {{^}}v_fabs_fold_v2f16: 121; GCN: flat_load_dword [[VAL:v[0-9]+]] 122 123; CI: v_cvt_f32_f16_e32 124; CI: v_cvt_f32_f16_e32 125; CI: v_mul_f32_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} 126; CI: v_mul_f32_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} 127; CI: v_cvt_f16_f32 128; CI: v_cvt_f16_f32 129 130; VI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, 131; VI: v_mul_f16_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} 132; VI: v_mul_f16_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} 133 134; GFX9: v_and_b32_e32 [[FABS:v[0-9]+]], 0x7fff7fff, [[VAL]] 135; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[FABS]], v{{[0-9]+$}} 136define void @v_fabs_fold_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { 137 %val = load <2 x half>, <2 x half> addrspace(1)* %in 138 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val) 139 %fmul = fmul <2 x half> %fabs, %val 140 store <2 x half> %fmul, <2 x half> addrspace(1)* %out 141 ret void 142} 143 144declare half @llvm.fabs.f16(half) #1 145declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #1 146declare <4 x half> @llvm.fabs.v4f16(<4 x half>) #1 147declare i32 @llvm.amdgcn.workitem.id.x() #1 148 149attributes #0 = { nounwind } 150attributes #1 = { nounwind readnone } 151