1; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s 2 3; GCN-LABEL: {{^}}float4_extelt: 4; GCN-NOT: buffer_ 5; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 6; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 7; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 8; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1.0, [[C1]] 9; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], 2.0, [[V1]], [[C2]] 10; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], 4.0, [[V2]], [[C3]] 11; GCN: store_dword v[{{[0-9:]+}}], [[V3]] 12define amdgpu_kernel void @float4_extelt(float addrspace(1)* %out, i32 %sel) { 13entry: 14 %ext = extractelement <4 x float> <float 0.0, float 1.0, float 2.0, float 4.0>, i32 %sel 15 store float %ext, float addrspace(1)* %out 16 ret void 17} 18 19; GCN-LABEL: {{^}}int4_extelt: 20; GCN-NOT: buffer_ 21; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 22; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 23; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 24; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1, [[C1]] 25; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], 2, [[V1]], [[C2]] 26; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], 4, [[V2]], [[C3]] 27; GCN: store_dword v[{{[0-9:]+}}], [[V3]] 28define amdgpu_kernel void @int4_extelt(i32 addrspace(1)* %out, i32 %sel) { 29entry: 30 %ext = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 4>, i32 %sel 31 store i32 %ext, i32 addrspace(1)* %out 32 ret void 33} 34 35; GCN-LABEL: {{^}}double4_extelt: 36; GCN-NOT: buffer_ 37; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 38; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2 39; GCN-DAG: v_cmp_eq_u32_e64 [[C3:[^,]+]], [[IDX]], 3 40; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] 41; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]] 42; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]] 43; GCN: store_dwordx2 v[{{[0-9:]+}}] 44define amdgpu_kernel void @double4_extelt(double addrspace(1)* %out, i32 %sel) { 45entry: 46 %ext = extractelement <4 x double> <double 0.01, double 1.01, double 2.01, double 4.01>, i32 %sel 47 store double %ext, double addrspace(1)* %out 48 ret void 49} 50 51; GCN-LABEL: {{^}}double5_extelt: 52; GCN-NOT: buffer_ 53; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 54; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2 55; GCN-DAG: v_cmp_eq_u32_e64 [[C3:[^,]+]], [[IDX]], 3 56; GCN-DAG: v_cmp_eq_u32_e64 [[C4:[^,]+]], [[IDX]], 4 57; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] 58; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]] 59; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]] 60; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C4]] 61; GCN: store_dwordx2 v[{{[0-9:]+}}] 62define amdgpu_kernel void @double5_extelt(double addrspace(1)* %out, i32 %sel) { 63entry: 64 %ext = extractelement <5 x double> <double 0.01, double 1.01, double 2.01, double 4.01, double 5.01>, i32 %sel 65 store double %ext, double addrspace(1)* %out 66 ret void 67} 68 69; GCN-LABEL: {{^}}half4_extelt: 70; GCN-NOT: buffer_ 71; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c00 72; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x44004200 73; GCN-DAG: s_lshl_b32 [[SEL:s[0-p]+]], s{{[0-9]+}}, 4 74; GCN: s_lshr_b64 s{{\[}}[[RL:[0-9]+]]:{{[0-9]+}}], s{{\[}}[[SL]]:[[SH]]], [[SEL]] 75; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]] 76; GCN: store_short v[{{[0-9:]+}}], v[[VRL]] 77define amdgpu_kernel void @half4_extelt(half addrspace(1)* %out, i32 %sel) { 78entry: 79 %ext = extractelement <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, i32 %sel 80 store half %ext, half addrspace(1)* %out 81 ret void 82} 83 84; GCN-LABEL: {{^}}float2_extelt: 85; GCN-NOT: buffer_ 86; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 87; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1.0, [[C1]] 88; GCN: store_dword v[{{[0-9:]+}}], [[V1]] 89define amdgpu_kernel void @float2_extelt(float addrspace(1)* %out, i32 %sel) { 90entry: 91 %ext = extractelement <2 x float> <float 0.0, float 1.0>, i32 %sel 92 store float %ext, float addrspace(1)* %out 93 ret void 94} 95 96; GCN-LABEL: {{^}}double2_extelt: 97; GCN-NOT: buffer_ 98; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 99; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] 100; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]] 101; GCN: store_dwordx2 v[{{[0-9:]+}}] 102define amdgpu_kernel void @double2_extelt(double addrspace(1)* %out, i32 %sel) { 103entry: 104 %ext = extractelement <2 x double> <double 0.01, double 1.01>, i32 %sel 105 store double %ext, double addrspace(1)* %out 106 ret void 107} 108 109; GCN-LABEL: {{^}}half8_extelt: 110; GCN-NOT: buffer_ 111; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 112; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 113; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 114; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4 115; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5 116; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6 117; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7 118; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]] 119; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]] 120; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]] 121; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]] 122; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]] 123; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]] 124; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]] 125; GCN: store_short v[{{[0-9:]+}}], [[V7]] 126define amdgpu_kernel void @half8_extelt(half addrspace(1)* %out, i32 %sel) { 127entry: 128 %ext = extractelement <8 x half> <half 1.0, half 2.0, half 3.0, half 4.0, half 5.0, half 6.0, half 7.0, half 8.0>, i32 %sel 129 store half %ext, half addrspace(1)* %out 130 ret void 131} 132 133; GCN-LABEL: {{^}}short8_extelt: 134; GCN-NOT: buffer_ 135; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 136; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 137; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 138; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4 139; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5 140; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6 141; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7 142; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]] 143; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]] 144; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]] 145; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]] 146; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]] 147; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]] 148; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]] 149; GCN: store_short v[{{[0-9:]+}}], [[V7]] 150define amdgpu_kernel void @short8_extelt(i16 addrspace(1)* %out, i32 %sel) { 151entry: 152 %ext = extractelement <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i32 %sel 153 store i16 %ext, i16 addrspace(1)* %out 154 ret void 155} 156 157; GCN-LABEL: {{^}}float8_extelt: 158; GCN-NOT: buffer_ 159; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 160; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 161; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 162; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4 163; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5 164; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6 165; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7 166; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]] 167; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]] 168; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]] 169; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]] 170; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]] 171; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]] 172; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]] 173; GCN: store_dword v[{{[0-9:]+}}], [[V7]] 174define amdgpu_kernel void @float8_extelt(float addrspace(1)* %out, i32 %sel) { 175entry: 176 %ext = extractelement <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, i32 %sel 177 store float %ext, float addrspace(1)* %out 178 ret void 179} 180 181; GCN-LABEL: {{^}}double8_extelt: 182; GCN-NOT: buffer_ 183; GCN-NOT: s_or_b32 184; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0 185; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]] 186; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]] 187; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]] 188; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]] 189; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]] 190define amdgpu_kernel void @double8_extelt(double addrspace(1)* %out, i32 %sel) { 191entry: 192 %ext = extractelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, i32 %sel 193 store double %ext, double addrspace(1)* %out 194 ret void 195} 196 197; GCN-LABEL: {{^}}double7_extelt: 198; GCN-NOT: buffer_ 199; GCN-NOT: s_or_b32 200; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0 201; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]] 202; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]] 203; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]] 204; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]] 205; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]] 206define amdgpu_kernel void @double7_extelt(double addrspace(1)* %out, i32 %sel) { 207entry: 208 %ext = extractelement <7 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0>, i32 %sel 209 store double %ext, double addrspace(1)* %out 210 ret void 211} 212 213; GCN-LABEL: {{^}}float16_extelt: 214; GCN-NOT: buffer_ 215; GCN-DAG: s_mov_b32 m0, 216; GCN-DAG: v_mov_b32_e32 [[VLO:v[0-9]+]], 1.0 217; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0 218; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000 219; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0 220; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40a00000 221; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40c00000 222; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40e00000 223; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41000000 224; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41100000 225; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41200000 226; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41300000 227; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41400000 228; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41500000 229; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41600000 230; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41700000 231; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41800000 232; GCN-DAG: v_movrels_b32_e32 [[RES:v[0-9]+]], [[VLO]] 233; GCN: store_dword v[{{[0-9:]+}}], [[RES]] 234define amdgpu_kernel void @float16_extelt(float addrspace(1)* %out, i32 %sel) { 235entry: 236 %ext = extractelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, i32 %sel 237 store float %ext, float addrspace(1)* %out 238 ret void 239} 240 241; GCN-LABEL: {{^}}double15_extelt: 242; GCN-NOT: buffer_ 243; GCN-NOT: s_or_b32 244; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0 245; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]] 246; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]] 247; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]] 248; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]] 249; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]] 250define amdgpu_kernel void @double15_extelt(double addrspace(1)* %out, i32 %sel) { 251entry: 252 %ext = extractelement <15 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0>, i32 %sel 253 store double %ext, double addrspace(1)* %out 254 ret void 255} 256 257; GCN-LABEL: {{^}}double16_extelt: 258; GCN-NOT: buffer_ 259; GCN-NOT: s_or_b32 260; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0 261; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]] 262; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]] 263; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]] 264; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]] 265; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]] 266define amdgpu_kernel void @double16_extelt(double addrspace(1)* %out, i32 %sel) { 267entry: 268 %ext = extractelement <16 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0, double 16.0>, i32 %sel 269 store double %ext, double addrspace(1)* %out 270 ret void 271} 272 273; GCN-LABEL: {{^}}float32_extelt: 274; GCN-NOT: buffer_ 275; GCN-DAG: s_mov_b32 m0, 276; GCN-DAG: v_mov_b32_e32 [[VLO:v[0-9]+]], 1.0 277; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0 278; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000 279; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0 280; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40a00000 281; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40c00000 282; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40e00000 283; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41000000 284; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41100000 285; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41200000 286; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41300000 287; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41400000 288; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41500000 289; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41600000 290; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41700000 291; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41800000 292; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41880000 293; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41900000 294; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41980000 295; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a00000 296; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a80000 297; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41b00000 298; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41b80000 299; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41c00000 300; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41c80000 301; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41d00000 302; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41d80000 303; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41e00000 304; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41e80000 305; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41f00000 306; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41f80000 307; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x42000000 308; GCN-DAG: v_movrels_b32_e32 [[RES:v[0-9]+]], [[VLO]] 309; GCN: store_dword v[{{[0-9:]+}}], [[RES]] 310define amdgpu_kernel void @float32_extelt(float addrspace(1)* %out, i32 %sel) { 311entry: 312 %ext = extractelement <32 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0, float 17.0, float 18.0, float 19.0, float 20.0, float 21.0, float 22.0, float 23.0, float 24.0, float 25.0, float 26.0, float 27.0, float 28.0, float 29.0, float 30.0, float 31.0, float 32.0>, i32 %sel 313 store float %ext, float addrspace(1)* %out 314 ret void 315} 316 317; GCN-LABEL: {{^}}byte8_extelt: 318; GCN-NOT: buffer_ 319; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x4030201 320; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x8070605 321; GCN-DAG: s_lshl_b32 [[SEL:s[0-p]+]], s{{[0-9]+}}, 3 322; GCN: s_lshr_b64 s{{\[}}[[RL:[0-9]+]]:{{[0-9]+}}], s{{\[}}[[SL]]:[[SH]]], [[SEL]] 323; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]] 324; GCN: store_byte v[{{[0-9:]+}}], v[[VRL]] 325define amdgpu_kernel void @byte8_extelt(i8 addrspace(1)* %out, i32 %sel) { 326entry: 327 %ext = extractelement <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i32 %sel 328 store i8 %ext, i8 addrspace(1)* %out 329 ret void 330} 331 332; GCN-LABEL: {{^}}byte16_extelt: 333; GCN-NOT: buffer_ 334; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1 335; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2 336; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3 337; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4 338; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5 339; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6 340; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7 341; GCN-DAG: v_cmp_ne_u32_e64 [[C8:[^,]+]], [[IDX]], 8 342; GCN-DAG: v_cmp_ne_u32_e64 [[C9:[^,]+]], [[IDX]], 9 343; GCN-DAG: v_cmp_ne_u32_e64 [[C10:[^,]+]], [[IDX]], 10 344; GCN-DAG: v_cmp_ne_u32_e64 [[C11:[^,]+]], [[IDX]], 11 345; GCN-DAG: v_cmp_ne_u32_e64 [[C12:[^,]+]], [[IDX]], 12 346; GCN-DAG: v_cmp_ne_u32_e64 [[C13:[^,]+]], [[IDX]], 13 347; GCN-DAG: v_cmp_ne_u32_e64 [[C14:[^,]+]], [[IDX]], 14 348; GCN-DAG: v_cmp_ne_u32_e64 [[C15:[^,]+]], [[IDX]], 15 349; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]] 350; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]] 351; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]] 352; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]] 353; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]] 354; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]] 355; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]] 356; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V8:v[0-9]+]], {{[^,]+}}, [[V7]], [[C8]] 357; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V9:v[0-9]+]], {{[^,]+}}, [[V8]], [[C8]] 358; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V10:v[0-9]+]], {{[^,]+}}, [[V9]], [[C10]] 359; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V11:v[0-9]+]], {{[^,]+}}, [[V10]], [[C11]] 360; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V12:v[0-9]+]], {{[^,]+}}, [[V11]], [[C12]] 361; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V13:v[0-9]+]], {{[^,]+}}, [[V12]], [[C13]] 362; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V14:v[0-9]+]], {{[^,]+}}, [[V13]], [[C14]] 363; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V15:v[0-9]+]], {{[^,]+}}, [[V14]], [[C15]] 364; GCN: store_byte v[{{[0-9:]+}}], [[V15]] 365define amdgpu_kernel void @byte16_extelt(i8 addrspace(1)* %out, i32 %sel) { 366entry: 367 %ext = extractelement <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, i32 %sel 368 store i8 %ext, i8 addrspace(1)* %out 369 ret void 370} 371 372; GCN-LABEL: {{^}}bit4_extelt: 373; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 374; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 375; GCN-DAG: buffer_store_byte [[ZERO]], 376; GCN-DAG: buffer_store_byte [[ONE]], 377; GCN-DAG: buffer_store_byte [[ZERO]], 378; GCN-DAG: buffer_store_byte [[ONE]], 379; GCN: buffer_load_ubyte [[LOAD:v[0-9]+]], 380; GCN: v_and_b32_e32 [[RES:v[0-9]+]], 1, [[LOAD]] 381; GCN: flat_store_dword v[{{[0-9:]+}}], [[RES]] 382define amdgpu_kernel void @bit4_extelt(i32 addrspace(1)* %out, i32 %sel) { 383entry: 384 %ext = extractelement <4 x i1> <i1 0, i1 1, i1 0, i1 1>, i32 %sel 385 %zext = zext i1 %ext to i32 386 store i32 %zext, i32 addrspace(1)* %out 387 ret void 388} 389 390; GCN-LABEL: {{^}}bit128_extelt: 391; GCN-NOT: buffer_ 392; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1 393; GCN-DAG: v_mov_b32_e32 [[LASTIDX:v[0-9]+]], 0x7f 394; GCN-DAG: v_cmp_ne_u32_e32 [[CL:[^,]+]], s{{[0-9]+}}, [[LASTIDX]] 395; GCN-DAG: v_cndmask_b32_e{{32|64}} [[VL:v[0-9]+]], 0, [[V1]], [[CL]] 396; GCN: v_and_b32_e32 [[RES:v[0-9]+]], 1, [[VL]] 397; GCN: store_dword v[{{[0-9:]+}}], [[RES]] 398define amdgpu_kernel void @bit128_extelt(i32 addrspace(1)* %out, i32 %sel) { 399entry: 400 %ext = extractelement <128 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0>, i32 %sel 401 %zext = zext i1 %ext to i32 402 store i32 %zext, i32 addrspace(1)* %out 403 ret void 404} 405 406; GCN-LABEL: {{^}}float32_extelt_vec: 407; GCN-NOT: buffer_ 408; GCN-DAG: v_cmp_eq_u32_e{{32|64}} [[CC1:[^,]+]], 1, v0 409; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 1.0, 2.0, [[CC1]] 410; GCN-DAG: v_mov_b32_e32 [[LASTVAL:v[0-9]+]], 0x42000000 411; GCN-DAG: v_cmp_ne_u32_e32 [[LASTCC:[^,]+]], 31, v0 412; GCN-DAG: v_cndmask_b32_e{{32|64}} v0, [[LASTVAL]], v{{[0-9]+}}, [[LASTCC]] 413define float @float32_extelt_vec(i32 %sel) { 414entry: 415 %ext = extractelement <32 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0, float 17.0, float 18.0, float 19.0, float 20.0, float 21.0, float 22.0, float 23.0, float 24.0, float 25.0, float 26.0, float 27.0, float 28.0, float 29.0, float 30.0, float 31.0, float 32.0>, i32 %sel 416 ret float %ext 417} 418 419; GCN-LABEL: {{^}}double16_extelt_vec: 420; GCN-NOT: buffer_ 421; GCN-DAG: v_mov_b32_e32 [[V1HI:v[0-9]+]], 0x3ff19999 422; GCN-DAG: v_mov_b32_e32 [[V1LO:v[0-9]+]], 0x9999999a 423; GCN-DAG: v_mov_b32_e32 [[V2HI:v[0-9]+]], 0x4000cccc 424; GCN-DAG: v_mov_b32_e32 [[V2LO:v[0-9]+]], 0xcccccccd 425; GCN-DAG: v_cmp_eq_u32_e{{32|64}} [[CC1:[^,]+]], 1, v0 426; GCN-DAG: v_cndmask_b32_e{{32|64}} [[R1HI:v[0-9]+]], [[V1HI]], [[V2HI]], [[CC1]] 427; GCN-DAG: v_cndmask_b32_e{{32|64}} [[R1LO:v[0-9]+]], [[V1LO]], [[V2LO]], [[CC1]] 428define double @double16_extelt_vec(i32 %sel) { 429entry: 430 %ext = extractelement <16 x double> <double 1.1, double 2.1, double 3.1, double 4.1, double 5.1, double 6.1, double 7.1, double 8.1, double 9.1, double 10.1, double 11.1, double 12.1, double 13.1, double 14.1, double 15.1, double 16.1>, i32 %sel 431 ret double %ext 432} 433