1; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
2
3; GCN-LABEL: {{^}}float4_extelt:
4; GCN-NOT: buffer_
5; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
6; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2
7; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3
8; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1.0, [[C1]]
9; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], 2.0, [[V1]], [[C2]]
10; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], 4.0, [[V2]], [[C3]]
11; GCN:     store_dword v[{{[0-9:]+}}], [[V3]]
12define amdgpu_kernel void @float4_extelt(float addrspace(1)* %out, i32 %sel) {
13entry:
14  %ext = extractelement <4 x float> <float 0.0, float 1.0, float 2.0, float 4.0>, i32 %sel
15  store float %ext, float addrspace(1)* %out
16  ret void
17}
18
19; GCN-LABEL: {{^}}int4_extelt:
20; GCN-NOT: buffer_
21; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
22; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2
23; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3
24; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1, [[C1]]
25; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], 2, [[V1]], [[C2]]
26; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], 4, [[V2]], [[C3]]
27; GCN: store_dword v[{{[0-9:]+}}], [[V3]]
28define amdgpu_kernel void @int4_extelt(i32 addrspace(1)* %out, i32 %sel) {
29entry:
30  %ext = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 4>, i32 %sel
31  store i32 %ext, i32 addrspace(1)* %out
32  ret void
33}
34
35; GCN-LABEL: {{^}}double4_extelt:
36; GCN-NOT: buffer_
37; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
38; GCN-DAG: v_cmp_eq_u32_e64 [[C2:[^,]+]], [[IDX]], 2
39; GCN-DAG: v_cmp_eq_u32_e64 [[C3:[^,]+]], [[IDX]], 3
40; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]]
41; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C2]]
42; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C3]]
43; GCN: store_dwordx2 v[{{[0-9:]+}}]
44define amdgpu_kernel void @double4_extelt(double addrspace(1)* %out, i32 %sel) {
45entry:
46  %ext = extractelement <4 x double> <double 0.01, double 1.01, double 2.01, double 4.01>, i32 %sel
47  store double %ext, double addrspace(1)* %out
48  ret void
49}
50
51; GCN-LABEL: {{^}}half4_extelt:
52; GCN-NOT: buffer_
53; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c00
54; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x44004200
55; GCN-DAG: s_lshl_b32 [[SEL:s[0-p]+]], s{{[0-9]+}}, 4
56; GCN:     s_lshr_b64 s{{\[}}[[RL:[0-9]+]]:{{[0-9]+}}], s{{\[}}[[SL]]:[[SH]]], [[SEL]]
57; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]]
58; GCN:     store_short v[{{[0-9:]+}}], v[[VRL]]
59define amdgpu_kernel void @half4_extelt(half addrspace(1)* %out, i32 %sel) {
60entry:
61  %ext = extractelement <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, i32 %sel
62  store half %ext, half addrspace(1)* %out
63  ret void
64}
65
66; GCN-LABEL: {{^}}float2_extelt:
67; GCN-NOT: buffer_
68; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
69; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1.0, [[C1]]
70; GCN: store_dword v[{{[0-9:]+}}], [[V1]]
71define amdgpu_kernel void @float2_extelt(float addrspace(1)* %out, i32 %sel) {
72entry:
73  %ext = extractelement <2 x float> <float 0.0, float 1.0>, i32 %sel
74  store float %ext, float addrspace(1)* %out
75  ret void
76}
77
78; GCN-LABEL: {{^}}double2_extelt:
79; GCN-NOT: buffer_
80; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
81; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]]
82; GCN-DAG: v_cndmask_b32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, {{[^,]+}}, [[C1]]
83; GCN: store_dwordx2 v[{{[0-9:]+}}]
84define amdgpu_kernel void @double2_extelt(double addrspace(1)* %out, i32 %sel) {
85entry:
86  %ext = extractelement <2 x double> <double 0.01, double 1.01>, i32 %sel
87  store double %ext, double addrspace(1)* %out
88  ret void
89}
90
91; GCN-LABEL: {{^}}half8_extelt:
92; GCN-NOT: buffer_
93; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
94; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2
95; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3
96; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4
97; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5
98; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6
99; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7
100; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]]
101; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]]
102; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]]
103; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]]
104; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]]
105; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]]
106; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]]
107; GCN:     store_short v[{{[0-9:]+}}], [[V7]]
108define amdgpu_kernel void @half8_extelt(half addrspace(1)* %out, i32 %sel) {
109entry:
110  %ext = extractelement <8 x half> <half 1.0, half 2.0, half 3.0, half 4.0, half 5.0, half 6.0, half 7.0, half 8.0>, i32 %sel
111  store half %ext, half addrspace(1)* %out
112  ret void
113}
114
115; GCN-LABEL: {{^}}short8_extelt:
116; GCN-NOT: buffer_
117; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
118; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2
119; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3
120; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4
121; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5
122; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6
123; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7
124; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]]
125; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]]
126; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]]
127; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]]
128; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]]
129; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]]
130; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]]
131; GCN:     store_short v[{{[0-9:]+}}], [[V7]]
132define amdgpu_kernel void @short8_extelt(i16 addrspace(1)* %out, i32 %sel) {
133entry:
134  %ext = extractelement <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i32 %sel
135  store i16 %ext, i16 addrspace(1)* %out
136  ret void
137}
138
139; GCN-LABEL: {{^}}float8_extelt:
140; GCN-NOT: buffer_
141; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
142; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2
143; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3
144; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4
145; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5
146; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6
147; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7
148; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]]
149; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]]
150; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]]
151; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]]
152; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]]
153; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]]
154; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]]
155; GCN:     store_dword v[{{[0-9:]+}}], [[V7]]
156define amdgpu_kernel void @float8_extelt(float addrspace(1)* %out, i32 %sel) {
157entry:
158  %ext = extractelement <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, i32 %sel
159  store float %ext, float addrspace(1)* %out
160  ret void
161}
162
163; TODO: Should be able to copy to m0 only once and increment base instead.
164
165; GCN-LABEL: {{^}}double8_extelt:
166; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
167; GCN-DAG: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ZERO]]
168; GCN-DAG: s_mov_b32 m0, [[IND0:s[0-9]+]]
169; GCN-DAG: s_or_b32 [[IND1:s[0-9]+]], [[IND0]], 1
170; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], [[BASE]]
171; GCN:     s_mov_b32 m0, [[IND1:s[0-9]+]]
172; GCN:     v_movrels_b32_e32 v[[RES_HI:[0-9]+]], [[BASE]]
173; GCN:     store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]]
174define amdgpu_kernel void @double8_extelt(double addrspace(1)* %out, i32 %sel) {
175entry:
176  %ext = extractelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, i32 %sel
177  store double %ext, double addrspace(1)* %out
178  ret void
179}
180
181; GCN-LABEL: {{^}}double7_extelt:
182; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
183; GCN-DAG: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ZERO]]
184; GCN-DAG: s_mov_b32 m0, [[IND0:s[0-9]+]]
185; GCN-DAG: s_or_b32 [[IND1:s[0-9]+]], [[IND0]], 1
186; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], [[BASE]]
187; GCN:     s_mov_b32 m0, [[IND1:s[0-9]+]]
188; GCN:     v_movrels_b32_e32 v[[RES_HI:[0-9]+]], [[BASE]]
189; GCN:     store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]]
190define amdgpu_kernel void @double7_extelt(double addrspace(1)* %out, i32 %sel) {
191entry:
192  %ext = extractelement <7 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0>, i32 %sel
193  store double %ext, double addrspace(1)* %out
194  ret void
195}
196
197; GCN-LABEL: {{^}}float16_extelt:
198; GCN-NOT: buffer_
199; GCN-DAG: s_mov_b32 m0,
200; GCN-DAG: v_mov_b32_e32 [[VLO:v[0-9]+]], 1.0
201; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0
202; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000
203; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0
204; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40a00000
205; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40c00000
206; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40e00000
207; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41000000
208; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41100000
209; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41200000
210; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41300000
211; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41400000
212; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41500000
213; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41600000
214; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41700000
215; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41800000
216; GCN-DAG: v_movrels_b32_e32 [[RES:v[0-9]+]], [[VLO]]
217; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]
218define amdgpu_kernel void @float16_extelt(float addrspace(1)* %out, i32 %sel) {
219entry:
220  %ext = extractelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, i32 %sel
221  store float %ext, float addrspace(1)* %out
222  ret void
223}
224
225; GCN-LABEL: {{^}}double16_extelt:
226; GCN: buffer_store_dword
227; GCN: buffer_store_dword
228; GCN: buffer_store_dword
229; GCN: buffer_store_dword
230; GCN: buffer_store_dword
231; GCN: buffer_store_dword
232; GCN: buffer_store_dword
233; GCN: buffer_store_dword
234; GCN: buffer_store_dword
235; GCN: buffer_store_dword
236; GCN: buffer_store_dword
237; GCN: buffer_store_dword
238; GCN: buffer_store_dword
239; GCN: buffer_store_dword
240; GCN: buffer_store_dword
241; GCN: buffer_store_dword
242; GCN: buffer_store_dword
243; GCN: buffer_store_dword
244; GCN: buffer_store_dword
245; GCN: buffer_store_dword
246; GCN: buffer_store_dword
247; GCN: buffer_store_dword
248; GCN: buffer_store_dword
249; GCN: buffer_store_dword
250; GCN: buffer_store_dword
251; GCN: buffer_store_dword
252; GCN: buffer_store_dword
253; GCN: buffer_store_dword
254; GCN: buffer_store_dword
255; GCN: buffer_store_dword
256; GCN: buffer_store_dword
257; GCN: buffer_store_dword
258; GCN: buffer_load_dword
259; GCN: buffer_load_dword
260; GCN: store_dword
261define amdgpu_kernel void @double16_extelt(double addrspace(1)* %out, i32 %sel) {
262entry:
263  %ext = extractelement <16 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0, double 16.0>, i32 %sel
264  store double %ext, double addrspace(1)* %out
265  ret void
266}
267
268; GCN-LABEL: {{^}}byte8_extelt:
269; GCN-NOT: buffer_
270; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x4030201
271; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x8070605
272; GCN-DAG: s_lshl_b32 [[SEL:s[0-p]+]], s{{[0-9]+}}, 3
273; GCN:     s_lshr_b64 s{{\[}}[[RL:[0-9]+]]:{{[0-9]+}}], s{{\[}}[[SL]]:[[SH]]], [[SEL]]
274; GCN-DAG: v_mov_b32_e32 v[[VRL:[0-9]+]], s[[RL]]
275; GCN:     store_byte v[{{[0-9:]+}}], v[[VRL]]
276define amdgpu_kernel void @byte8_extelt(i8 addrspace(1)* %out, i32 %sel) {
277entry:
278  %ext = extractelement <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i32 %sel
279  store i8 %ext, i8 addrspace(1)* %out
280  ret void
281}
282
283; GCN-LABEL: {{^}}byte16_extelt:
284; GCN-NOT: buffer_
285; GCN-DAG: v_cmp_eq_u32_e64 [[C1:[^,]+]], [[IDX:s[0-9]+]], 1
286; GCN-DAG: v_cmp_ne_u32_e64 [[C2:[^,]+]], [[IDX]], 2
287; GCN-DAG: v_cmp_ne_u32_e64 [[C3:[^,]+]], [[IDX]], 3
288; GCN-DAG: v_cmp_ne_u32_e64 [[C4:[^,]+]], [[IDX]], 4
289; GCN-DAG: v_cmp_ne_u32_e64 [[C5:[^,]+]], [[IDX]], 5
290; GCN-DAG: v_cmp_ne_u32_e64 [[C6:[^,]+]], [[IDX]], 6
291; GCN-DAG: v_cmp_ne_u32_e64 [[C7:[^,]+]], [[IDX]], 7
292; GCN-DAG: v_cmp_ne_u32_e64 [[C8:[^,]+]], [[IDX]], 8
293; GCN-DAG: v_cmp_ne_u32_e64 [[C9:[^,]+]], [[IDX]], 9
294; GCN-DAG: v_cmp_ne_u32_e64 [[C10:[^,]+]], [[IDX]], 10
295; GCN-DAG: v_cmp_ne_u32_e64 [[C11:[^,]+]], [[IDX]], 11
296; GCN-DAG: v_cmp_ne_u32_e64 [[C12:[^,]+]], [[IDX]], 12
297; GCN-DAG: v_cmp_ne_u32_e64 [[C13:[^,]+]], [[IDX]], 13
298; GCN-DAG: v_cmp_ne_u32_e64 [[C14:[^,]+]], [[IDX]], 14
299; GCN-DAG: v_cmp_ne_u32_e64 [[C15:[^,]+]], [[IDX]], 15
300; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], {{[^,]+}}, {{[^,]+}}, [[C1]]
301; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V2:v[0-9]+]], {{[^,]+}}, [[V1]], [[C2]]
302; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V3:v[0-9]+]], {{[^,]+}}, [[V2]], [[C3]]
303; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V4:v[0-9]+]], {{[^,]+}}, [[V3]], [[C4]]
304; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V5:v[0-9]+]], {{[^,]+}}, [[V4]], [[C5]]
305; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V6:v[0-9]+]], {{[^,]+}}, [[V5]], [[C6]]
306; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V7:v[0-9]+]], {{[^,]+}}, [[V6]], [[C7]]
307; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V8:v[0-9]+]], {{[^,]+}}, [[V7]], [[C8]]
308; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V9:v[0-9]+]], {{[^,]+}}, [[V8]], [[C8]]
309; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V10:v[0-9]+]], {{[^,]+}}, [[V9]], [[C10]]
310; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V11:v[0-9]+]], {{[^,]+}}, [[V10]], [[C11]]
311; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V12:v[0-9]+]], {{[^,]+}}, [[V11]], [[C12]]
312; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V13:v[0-9]+]], {{[^,]+}}, [[V12]], [[C13]]
313; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V14:v[0-9]+]], {{[^,]+}}, [[V13]], [[C14]]
314; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V15:v[0-9]+]], {{[^,]+}}, [[V14]], [[C15]]
315; GCN:     store_byte v[{{[0-9:]+}}], [[V15]]
316define amdgpu_kernel void @byte16_extelt(i8 addrspace(1)* %out, i32 %sel) {
317entry:
318  %ext = extractelement <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, i32 %sel
319  store i8 %ext, i8 addrspace(1)* %out
320  ret void
321}
322
323; GCN-LABEL: {{^}}bit4_extelt:
324; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
325; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
326; GCN-DAG: buffer_store_byte [[ZERO]],
327; GCN-DAG: buffer_store_byte [[ONE]],
328; GCN-DAG: buffer_store_byte [[ZERO]],
329; GCN-DAG: buffer_store_byte [[ONE]],
330; GCN:     buffer_load_ubyte [[LOAD:v[0-9]+]],
331; GCN:     v_and_b32_e32 [[RES:v[0-9]+]], 1, [[LOAD]]
332; GCN:     flat_store_dword v[{{[0-9:]+}}], [[RES]]
333define amdgpu_kernel void @bit4_extelt(i32 addrspace(1)* %out, i32 %sel) {
334entry:
335  %ext = extractelement <4 x i1> <i1 0, i1 1, i1 0, i1 1>, i32 %sel
336  %zext = zext i1 %ext to i32
337  store i32 %zext, i32 addrspace(1)* %out
338  ret void
339}
340
341; GCN-LABEL: {{^}}bit128_extelt:
342; GCN-NOT: buffer_
343; GCN-DAG: v_cndmask_b32_e{{32|64}} [[V1:v[0-9]+]], 0, 1
344; GCN-DAG: v_mov_b32_e32 [[LASTIDX:v[0-9]+]], 0x7f
345; GCN-DAG: v_cmp_ne_u32_e32 [[CL:[^,]+]], s{{[0-9]+}}, [[LASTIDX]]
346; GCN-DAG: v_cndmask_b32_e{{32|64}} [[VL:v[0-9]+]], 0, [[V1]], [[CL]]
347; GCN:     v_and_b32_e32 [[RES:v[0-9]+]], 1, [[VL]]
348; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]
349define amdgpu_kernel void @bit128_extelt(i32 addrspace(1)* %out, i32 %sel) {
350entry:
351  %ext = extractelement <128 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0>, i32 %sel
352  %zext = zext i1 %ext to i32
353  store i32 %zext, i32 addrspace(1)* %out
354  ret void
355}
356