1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s
3
4# Initially %2 starts out with 2 subranges (one for sub0, and one for
5# the rest of the lanes). After %2 is split, after refineSubRanges the
6# newly created register has a different set of lane masks since the
7# copy bundle uses 2 different defs to cover the register. This was
8# fixed by doing refineSubRanges after all the COPYs being inserted.
9
10---
11name: subrange_for_this_mask_not_found
12tracksRegLiveness: true
13machineFunctionInfo:
14  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
15  stackPtrOffsetReg: '$sgpr32'
16  occupancy:       7
17body:             |
18  ; CHECK-LABEL: name: subrange_for_this_mask_not_found
19  ; CHECK: bb.0:
20  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
21  ; CHECK-NEXT: {{  $}}
22  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
23  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
24  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:av_1024_align2 = COPY [[DEF1]]
25  ; CHECK-NEXT: {{  $}}
26  ; CHECK-NEXT: bb.1:
27  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
28  ; CHECK-NEXT: {{  $}}
29  ; CHECK-NEXT:   dead %3:vreg_64 = IMPLICIT_DEF
30  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF1]]
31  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF1]]
32  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
33  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
34  ; CHECK-NEXT: {{  $}}
35  ; CHECK-NEXT: bb.2:
36  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
37  ; CHECK-NEXT: {{  $}}
38  ; CHECK-NEXT:   undef %6.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16:av_1024_align2 = COPY [[COPY]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 {
39  ; CHECK-NEXT:     internal %6.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31:av_1024_align2 = COPY [[COPY]].sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
40  ; CHECK-NEXT:   }
41  ; CHECK-NEXT:   %6.sub0:av_1024_align2 = IMPLICIT_DEF
42  ; CHECK-NEXT:   S_NOP 0, implicit %6.sub0
43  ; CHECK-NEXT: {{  $}}
44  ; CHECK-NEXT: bb.3:
45  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
46  ; CHECK-NEXT: {{  $}}
47  ; CHECK-NEXT:   S_NOP 0, implicit %6
48  ; CHECK-NEXT: {{  $}}
49  ; CHECK-NEXT: bb.4:
50  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
51  ; CHECK-NEXT: {{  $}}
52  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
53  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
54  ; CHECK-NEXT: {{  $}}
55  ; CHECK-NEXT: bb.5:
56  ; CHECK-NEXT:   undef %4.sub0:vreg_1024_align2 = COPY [[DEF]]
57  ; CHECK-NEXT:   S_NOP 0, implicit %4
58  bb.0:
59    %0:vgpr_32 = IMPLICIT_DEF
60    %1:vreg_1024_align2 = IMPLICIT_DEF
61    %2:vreg_1024_align2 = COPY %1
62
63  bb.1:
64    %5:vreg_64 = IMPLICIT_DEF
65    S_NOP 0, implicit %1
66    S_NOP 0, implicit %1
67    %1:vreg_1024_align2 = IMPLICIT_DEF
68    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
69
70  bb.3:
71    %2.sub0:vreg_1024_align2 = IMPLICIT_DEF
72    S_NOP 0, implicit %2.sub0
73
74  bb.4:
75    S_NOP 0, implicit %2
76
77  bb.5:
78    %2:vreg_1024_align2 = IMPLICIT_DEF
79    S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc
80
81  bb.6:
82    undef %4.sub0:vreg_1024_align2 = COPY %0
83    S_NOP 0, implicit %4
84...
85