1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 define amdgpu_ps void @early_term_scc0_end_block() { 6 ret void 7 } 8 9 define amdgpu_ps void @early_term_scc0_next_terminator() { 10 ret void 11 } 12 13 define amdgpu_ps void @early_term_scc0_in_block() { 14 ret void 15 } 16 17 define amdgpu_gs void @early_term_scc0_gs() { 18 ret void 19 } 20 21 define amdgpu_cs void @early_term_scc0_cs() { 22 ret void 23 } 24... 25 26--- 27name: early_term_scc0_end_block 28tracksRegLiveness: true 29liveins: 30 - { reg: '$sgpr0' } 31 - { reg: '$sgpr1' } 32body: | 33 ; CHECK-LABEL: name: early_term_scc0_end_block 34 ; CHECK: bb.0: 35 ; CHECK: successors: %bb.1(0x80000000), %bb.2(0x00000000) 36 ; CHECK: liveins: $sgpr0, $sgpr1 37 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 38 ; CHECK: dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 39 ; CHECK: S_CBRANCH_SCC0 %bb.2, implicit $scc 40 ; CHECK: bb.1: 41 ; CHECK: liveins: $vgpr0 42 ; CHECK: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec 43 ; CHECK: S_ENDPGM 0 44 ; CHECK: bb.2: 45 ; CHECK: $exec_lo = S_MOV_B32 0 46 ; CHECK: EXP_DONE 9, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec 47 ; CHECK: S_ENDPGM 0 48 bb.0: 49 liveins: $sgpr0, $sgpr1 50 successors: %bb.1 51 52 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 53 dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 54 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec 55 56 bb.1: 57 liveins: $vgpr0 58 EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec 59 S_ENDPGM 0 60... 61 62--- 63name: early_term_scc0_next_terminator 64tracksRegLiveness: true 65liveins: 66 - { reg: '$sgpr0' } 67 - { reg: '$sgpr1' } 68body: | 69 ; CHECK-LABEL: name: early_term_scc0_next_terminator 70 ; CHECK: bb.0: 71 ; CHECK: successors: %bb.2(0x80000000), %bb.3(0x00000000) 72 ; CHECK: liveins: $sgpr0, $sgpr1 73 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 74 ; CHECK: dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 75 ; CHECK: S_CBRANCH_SCC0 %bb.3, implicit $scc 76 ; CHECK: S_BRANCH %bb.2 77 ; CHECK: bb.1: 78 ; CHECK: successors: %bb.2(0x80000000) 79 ; CHECK: $vgpr0 = V_MOV_B32_e32 1, implicit $exec 80 ; CHECK: bb.2: 81 ; CHECK: liveins: $vgpr0 82 ; CHECK: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec 83 ; CHECK: S_ENDPGM 0 84 ; CHECK: bb.3: 85 ; CHECK: $exec_lo = S_MOV_B32 0 86 ; CHECK: EXP_DONE 9, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec 87 ; CHECK: S_ENDPGM 0 88 bb.0: 89 liveins: $sgpr0, $sgpr1 90 successors: %bb.2 91 92 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 93 dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 94 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec 95 S_BRANCH %bb.2 96 97 bb.1: 98 successors: %bb.2 99 $vgpr0 = V_MOV_B32_e32 1, implicit $exec 100 S_BRANCH %bb.2 101 102 bb.2: 103 liveins: $vgpr0 104 EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec 105 S_ENDPGM 0 106... 107 108--- 109name: early_term_scc0_in_block 110tracksRegLiveness: true 111liveins: 112 - { reg: '$sgpr0' } 113 - { reg: '$sgpr1' } 114body: | 115 ; CHECK-LABEL: name: early_term_scc0_in_block 116 ; CHECK: bb.0: 117 ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) 118 ; CHECK: liveins: $sgpr0, $sgpr1 119 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 120 ; CHECK: dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 121 ; CHECK: S_CBRANCH_SCC0 %bb.2, implicit $scc 122 ; CHECK: bb.3: 123 ; CHECK: successors: %bb.1(0x80000000) 124 ; CHECK: liveins: $vgpr0, $scc 125 ; CHECK: $vgpr1 = V_MOV_B32_e32 1, implicit $exec 126 ; CHECK: bb.1: 127 ; CHECK: liveins: $vgpr0, $vgpr1 128 ; CHECK: EXP 1, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec 129 ; CHECK: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec 130 ; CHECK: S_ENDPGM 0 131 ; CHECK: bb.2: 132 ; CHECK: $exec_lo = S_MOV_B32 0 133 ; CHECK: EXP_DONE 9, undef $vgpr0, undef $vgpr0, undef $vgpr0, undef $vgpr0, 1, 0, 0, implicit $exec 134 ; CHECK: S_ENDPGM 0 135 bb.0: 136 liveins: $sgpr0, $sgpr1 137 successors: %bb.1 138 139 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 140 dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 141 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec 142 $vgpr1 = V_MOV_B32_e32 1, implicit $exec 143 144 bb.1: 145 liveins: $vgpr0, $vgpr1 146 EXP 1, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec 147 EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec 148 S_ENDPGM 0 149... 150 151--- 152name: early_term_scc0_gs 153tracksRegLiveness: true 154liveins: 155 - { reg: '$sgpr0' } 156 - { reg: '$sgpr1' } 157body: | 158 ; CHECK-LABEL: name: early_term_scc0_gs 159 ; CHECK: bb.0: 160 ; CHECK: successors: %bb.1(0x80000000) 161 ; CHECK: liveins: $sgpr0, $sgpr1 162 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 163 ; CHECK: dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 164 ; CHECK: bb.1: 165 ; CHECK: liveins: $vgpr0 166 ; CHECK: S_ENDPGM 0 167 bb.0: 168 liveins: $sgpr0, $sgpr1 169 successors: %bb.1 170 171 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 172 dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 173 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec 174 175 bb.1: 176 liveins: $vgpr0 177 S_ENDPGM 0 178... 179 180--- 181name: early_term_scc0_cs 182tracksRegLiveness: true 183liveins: 184 - { reg: '$sgpr0' } 185 - { reg: '$sgpr1' } 186body: | 187 ; CHECK-LABEL: name: early_term_scc0_cs 188 ; CHECK: bb.0: 189 ; CHECK: successors: %bb.1(0x80000000), %bb.2(0x00000000) 190 ; CHECK: liveins: $sgpr0, $sgpr1 191 ; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec 192 ; CHECK: dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 193 ; CHECK: S_CBRANCH_SCC0 %bb.2, implicit $scc 194 ; CHECK: bb.1: 195 ; CHECK: liveins: $vgpr0 196 ; CHECK: S_ENDPGM 0 197 ; CHECK: bb.2: 198 ; CHECK: $exec_lo = S_MOV_B32 0 199 ; CHECK: S_ENDPGM 0 200 bb.0: 201 liveins: $sgpr0, $sgpr1 202 successors: %bb.1 203 204 $vgpr0 = V_MOV_B32_e32 0, implicit $exec 205 dead $sgpr0 = S_AND_B32 $sgpr0, killed $sgpr1, implicit-def $scc 206 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec 207 208 bb.1: 209 liveins: $vgpr0 210 S_ENDPGM 0 211... 212