1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,CI %s 2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,+flat-for-global,-unaligned-access-mode < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,GFX9,GFX9-ALIGNED %s 3; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,+flat-for-global,+unaligned-access-mode < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,GFX9,GFX9-UNALIGNED %s 4 5@lds = addrspace(3) global [512 x float] undef, align 4 6@lds.f64 = addrspace(3) global [512 x double] undef, align 8 7 8; GCN-LABEL: {{^}}simple_write2_one_val_f32: 9; CI-DAG: s_mov_b32 m0 10; GFX9-NOT: m0 11 12; GCN-DAG: {{buffer|flat|global}}_load_dword [[VAL:v[0-9]+]] 13; GCN-DAG: v_lshlrev_b32_e32 [[VBASE:v[0-9]+]], 2, v{{[0-9]+}} 14; GCN-DAG: v_add_{{[ui]}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}lds@abs32@lo, [[VBASE]] 15; GCN: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8 16; GCN: s_endpgm 17define amdgpu_kernel void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { 18 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 19 %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i 20 %val = load float, float addrspace(1)* %in.gep, align 4 21 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 22 store float %val, float addrspace(3)* %arrayidx0, align 4 23 %add.x = add nsw i32 %x.i, 8 24 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 25 store float %val, float addrspace(3)* %arrayidx1, align 4 26 ret void 27} 28 29; GCN-LABEL: {{^}}simple_write2_two_val_f32: 30; CI-DAG: s_mov_b32 m0 31; GFX9-NOT: m0 32 33; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 34; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 35 36; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}{{$}} 37; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4{{$}} 38 39; GCN-DAG: v_lshlrev_b32_e32 [[VBASE:v[0-9]+]], 2, v{{[0-9]+}} 40; GCN-DAG: v_add_{{[ui]}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}lds@abs32@lo, [[VBASE]] 41; GCN: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8 42; GCN: s_endpgm 43define amdgpu_kernel void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { 44 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 45 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i 46 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 47 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 48 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 49 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 50 store float %val0, float addrspace(3)* %arrayidx0, align 4 51 %add.x = add nsw i32 %x.i, 8 52 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 53 store float %val1, float addrspace(3)* %arrayidx1, align 4 54 ret void 55} 56 57; GCN-LABEL: @simple_write2_two_val_f32_volatile_0 58; CI-DAG: s_mov_b32 m0 59; GFX9-NOT: m0 60 61; GCN-NOT: ds_write2_b32 62; GCN: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} 63; GCN: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32 64; GCN: s_endpgm 65define amdgpu_kernel void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { 66 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 67 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i 68 %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i 69 %val0 = load volatile float, float addrspace(1)* %in0.gep, align 4 70 %val1 = load volatile float, float addrspace(1)* %in1.gep, align 4 71 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 72 store volatile float %val0, float addrspace(3)* %arrayidx0, align 4 73 %add.x = add nsw i32 %x.i, 8 74 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 75 store float %val1, float addrspace(3)* %arrayidx1, align 4 76 ret void 77} 78 79; GCN-LABEL: @simple_write2_two_val_f32_volatile_1 80; CI-DAG: s_mov_b32 m0 81; GFX9-NOT: m0 82 83; GCN-NOT: ds_write2_b32 84; GCN: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} 85; GCN: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32 86; GCN: s_endpgm 87define amdgpu_kernel void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { 88 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 89 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i 90 %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i 91 %val0 = load volatile float, float addrspace(1)* %in0.gep, align 4 92 %val1 = load volatile float, float addrspace(1)* %in1.gep, align 4 93 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 94 store float %val0, float addrspace(3)* %arrayidx0, align 4 95 %add.x = add nsw i32 %x.i, 8 96 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 97 store volatile float %val1, float addrspace(3)* %arrayidx1, align 4 98 ret void 99} 100 101; 2 data subregisters from different super registers. 102; GCN-LABEL: {{^}}simple_write2_two_val_subreg2_mixed_f32: 103; GFX9-NOT: m0 104 105; CI: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}} 106; CI: buffer_load_dwordx2 v{{\[[0-9]+}}:[[VAL1:[0-9]+]]{{\]}} 107; CI-DAG: s_mov_b32 m0 108 109; CI-DAG: v_lshlrev_b32_e32 [[VOFS:v[0-9]+]], 2, v{{[0-9]+}} 110; CI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]], vcc, lds@abs32@lo, [[VOFS]] 111; 112; TODO: This should be an s_mov_b32. The v_mov_b32 gets introduced by an 113; early legalization of the constant bus constraint on the v_lshl_add_u32, 114; and then SIFoldOperands folds in an unlucky order. 115; GFX9-DAG: v_mov_b32_e32 [[VBASE:v[0-9]+]], lds@abs32@lo 116; GFX9-DAG: v_lshl_add_u32 [[VPTR:v[0-9]+]], {{v[0-9]+}}, 2, [[VBASE]] 117 118; GFX9-DAG: global_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}} 119; GFX9-DAG: global_load_dwordx2 v{{\[[0-9]+}}:[[VAL1:[0-9]+]]{{\]}} 120 121; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 122; GCN: s_endpgm 123define amdgpu_kernel void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 { 124 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 125 %in.gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i 126 %in.gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in.gep.0, i32 1 127 %val0 = load volatile <2 x float>, <2 x float> addrspace(1)* %in.gep.0, align 8 128 %val1 = load volatile <2 x float>, <2 x float> addrspace(1)* %in.gep.1, align 8 129 %val0.0 = extractelement <2 x float> %val0, i32 0 130 %val1.1 = extractelement <2 x float> %val1, i32 1 131 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 132 store float %val0.0, float addrspace(3)* %arrayidx0, align 4 133 %add.x = add nsw i32 %x.i, 8 134 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 135 store float %val1.1, float addrspace(3)* %arrayidx1, align 4 136 ret void 137} 138 139; GCN-LABEL: @simple_write2_two_val_subreg2_f32 140; CI-DAG: s_mov_b32 m0 141; GFX9-NOT: m0 142 143; GCN-DAG: {{buffer|global}}_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} 144 145; CI-DAG: v_lshlrev_b32_e32 [[VOFS:v[0-9]+]], 2, v{{[0-9]+}} 146; CI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]], vcc, lds@abs32@lo, [[VOFS]] 147; GFX9-DAG: v_mov_b32_e32 [[VBASE:v[0-9]+]], lds@abs32@lo 148; GFX9-DAG: v_lshl_add_u32 [[VPTR:v[0-9]+]], v{{[0-9]+}}, 2, [[VBASE]] 149 150; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 151; GCN: s_endpgm 152define amdgpu_kernel void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 { 153 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 154 %in.gep = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i 155 %val = load <2 x float>, <2 x float> addrspace(1)* %in.gep, align 8 156 %val0 = extractelement <2 x float> %val, i32 0 157 %val1 = extractelement <2 x float> %val, i32 1 158 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 159 store float %val0, float addrspace(3)* %arrayidx0, align 4 160 %add.x = add nsw i32 %x.i, 8 161 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 162 store float %val1, float addrspace(3)* %arrayidx1, align 4 163 ret void 164} 165 166; GCN-LABEL: @simple_write2_two_val_subreg4_f32 167; CI-DAG: s_mov_b32 m0 168; GFX9-NOT: m0 169 170; GCN-DAG: {{buffer|global}}_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} 171 172; CI-DAG: v_lshlrev_b32_e32 [[VOFS:v[0-9]+]], 2, v{{[0-9]+}} 173; CI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]], vcc, lds@abs32@lo, [[VOFS]] 174; GFX9-DAG: v_mov_b32_e32 [[VBASE:v[0-9]+]], lds@abs32@lo 175; GFX9-DAG: v_lshl_add_u32 [[VPTR:v[0-9]+]], v{{[0-9]+}}, 2, [[VBASE]] 176 177; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 178; GCN: s_endpgm 179define amdgpu_kernel void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x float> addrspace(1)* %in) #0 { 180 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 181 %in.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 %x.i 182 %val = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 16 183 %val0 = extractelement <4 x float> %val, i32 0 184 %val1 = extractelement <4 x float> %val, i32 3 185 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 186 store float %val0, float addrspace(3)* %arrayidx0, align 4 187 %add.x = add nsw i32 %x.i, 8 188 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 189 store float %val1, float addrspace(3)* %arrayidx1, align 4 190 ret void 191} 192 193; GCN-LABEL: @simple_write2_two_val_max_offset_f32 194; CI-DAG: s_mov_b32 m0 195; GFX9-NOT: m0 196 197; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 198; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 199 200; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}{{$}} 201; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4{{$}} 202 203; GCN-DAG: v_lshlrev_b32_e32 [[VBASE:v[0-9]+]], 2, v{{[0-9]+}} 204; GCN-DAG: v_add_{{[ui]}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}lds@abs32@lo, [[VBASE]] 205 206; GCN: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255 207; GCN: s_endpgm 208define amdgpu_kernel void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { 209 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 210 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i 211 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 212 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 213 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 214 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 215 store float %val0, float addrspace(3)* %arrayidx0, align 4 216 %add.x = add nsw i32 %x.i, 255 217 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 218 store float %val1, float addrspace(3)* %arrayidx1, align 4 219 ret void 220} 221 222; GCN-LABEL: @simple_write2_two_val_too_far_f32 223; CI-DAG: s_mov_b32 m0 224; GFX9-NOT: m0 225 226; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} 227; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028 228; GCN: s_endpgm 229define amdgpu_kernel void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { 230 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 231 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i 232 %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i 233 %val0 = load float, float addrspace(1)* %in0.gep, align 4 234 %val1 = load float, float addrspace(1)* %in1.gep, align 4 235 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 236 store float %val0, float addrspace(3)* %arrayidx0, align 4 237 %add.x = add nsw i32 %x.i, 257 238 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 239 store float %val1, float addrspace(3)* %arrayidx1, align 4 240 ret void 241} 242 243; GCN-LABEL: @simple_write2_two_val_f32_x2 244; CI-DAG: s_mov_b32 m0 245; GFX9-NOT: m0 246 247; GCN: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset1:8 248; GCN: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0]], [[VAL1]] offset0:11 offset1:27 249; GCN: s_endpgm 250define amdgpu_kernel void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { 251 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 252 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x 253 %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x 254 %val0 = load float, float addrspace(1)* %in0.gep, align 4 255 %val1 = load float, float addrspace(1)* %in1.gep, align 4 256 257 %idx.0 = add nsw i32 %tid.x, 0 258 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0 259 store float %val0, float addrspace(3)* %arrayidx0, align 4 260 261 %idx.1 = add nsw i32 %tid.x, 8 262 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1 263 store float %val1, float addrspace(3)* %arrayidx1, align 4 264 265 %idx.2 = add nsw i32 %tid.x, 11 266 %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2 267 store float %val0, float addrspace(3)* %arrayidx2, align 4 268 269 %idx.3 = add nsw i32 %tid.x, 27 270 %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3 271 store float %val1, float addrspace(3)* %arrayidx3, align 4 272 273 ret void 274} 275 276; GCN-LABEL: @simple_write2_two_val_f32_x2_nonzero_base 277; CI-DAG: s_mov_b32 m0 278; GFX9-NOT: m0 279 280; GCN: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:3 offset1:8 281; GCN: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0]], [[VAL1]] offset0:11 offset1:27 282; GCN: s_endpgm 283define amdgpu_kernel void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { 284 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 285 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x 286 %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x 287 %val0 = load float, float addrspace(1)* %in0.gep, align 4 288 %val1 = load float, float addrspace(1)* %in1.gep, align 4 289 290 %idx.0 = add nsw i32 %tid.x, 3 291 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0 292 store float %val0, float addrspace(3)* %arrayidx0, align 4 293 294 %idx.1 = add nsw i32 %tid.x, 8 295 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.1 296 store float %val1, float addrspace(3)* %arrayidx1, align 4 297 298 %idx.2 = add nsw i32 %tid.x, 11 299 %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2 300 store float %val0, float addrspace(3)* %arrayidx2, align 4 301 302 %idx.3 = add nsw i32 %tid.x, 27 303 %arrayidx3 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.3 304 store float %val1, float addrspace(3)* %arrayidx3, align 4 305 306 ret void 307} 308 309; GCN-LABEL: @write2_ptr_subreg_arg_two_val_f32 310; CI-DAG: s_mov_b32 m0 311; GFX9-NOT: m0 312 313; GCN-NOT: ds_write2_b32 314; GCN: ds_write_b32 315; GCN: ds_write_b32 316; GCN: s_endpgm 317define amdgpu_kernel void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1, <2 x float addrspace(3)*> %lds.ptr) #0 { 318 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 319 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i 320 %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i 321 %val0 = load float, float addrspace(1)* %in0.gep, align 4 322 %val1 = load float, float addrspace(1)* %in1.gep, align 4 323 324 %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0 325 %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0 326 %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1 327 %gep.0 = extractelement <2 x float addrspace(3)*> %gep, i32 0 328 %gep.1 = extractelement <2 x float addrspace(3)*> %gep, i32 1 329 330 ; Apply an additional offset after the vector that will be more obviously folded. 331 %gep.1.offset = getelementptr float, float addrspace(3)* %gep.1, i32 8 332 store float %val0, float addrspace(3)* %gep.0, align 4 333 334 %add.x = add nsw i32 %x.i, 8 335 store float %val1, float addrspace(3)* %gep.1.offset, align 4 336 ret void 337} 338 339; GCN-LABEL: @simple_write2_one_val_f64 340; CI-DAG: s_mov_b32 m0 341; GFX9-NOT: m0 342 343; GCN-DAG: {{buffer|global}}_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], 344; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}} 345; GCN: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset1:8 346; GCN: s_endpgm 347define amdgpu_kernel void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 { 348 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 349 %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i 350 %val = load double, double addrspace(1)* %in.gep, align 8 351 %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i 352 store double %val, double addrspace(3)* %arrayidx0, align 8 353 %add.x = add nsw i32 %x.i, 8 354 %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x 355 store double %val, double addrspace(3)* %arrayidx1, align 8 356 ret void 357} 358 359; GCN-LABEL: @misaligned_simple_write2_one_val_f64 360; CI-DAG: s_mov_b32 m0 361; GFX9-NOT: m0 362 363; GCN-DAG: {{buffer|global}}_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}} 364; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}} 365; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:1 366; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15 367; GCN: s_endpgm 368define amdgpu_kernel void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { 369 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 370 %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i 371 %val = load double, double addrspace(1)* %in.gep, align 8 372 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i 373 store double %val, double addrspace(3)* %arrayidx0, align 4 374 %add.x = add nsw i32 %x.i, 7 375 %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x 376 store double %val, double addrspace(3)* %arrayidx1, align 4 377 ret void 378} 379 380; GCN-LABEL: @simple_write2_two_val_f64 381; CI-DAG: s_mov_b32 m0 382; GFX9-NOT: m0 383 384; CI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 385; CI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 386 387; GFX9-DAG: global_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]$}} 388; GFX9-DAG: global_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:8 389 390; GCN-DAG: v_lshlrev_b32_e32 [[VBASE:v[0-9]+]], 3, v{{[0-9]+}} 391; GCN-DAG: v_add_{{[ui]}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}lds.f64@abs32@lo, [[VBASE]] 392; GCN: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8 393; GCN: s_endpgm 394define amdgpu_kernel void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 { 395 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 396 %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i 397 %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1 398 %val0 = load volatile double, double addrspace(1)* %in.gep.0, align 8 399 %val1 = load volatile double, double addrspace(1)* %in.gep.1, align 8 400 %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i 401 store double %val0, double addrspace(3)* %arrayidx0, align 8 402 %add.x = add nsw i32 %x.i, 8 403 %arrayidx1 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %add.x 404 store double %val1, double addrspace(3)* %arrayidx1, align 8 405 ret void 406} 407 408@foo = addrspace(3) global [4 x i32] undef, align 4 409 410; GCN-LABEL: @store_constant_adjacent_offsets 411; CI-DAG: s_mov_b32 m0 412; GFX9-NOT: m0 413 414; GCN-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], foo@abs32@lo{{$}} 415; GCN: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1 416define amdgpu_kernel void @store_constant_adjacent_offsets() { 417 store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4 418 store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 1), align 4 419 ret void 420} 421 422; GCN-LABEL: @store_constant_disjoint_offsets 423; CI-DAG: s_mov_b32 m0 424; GFX9-NOT: m0 425 426; GCN-DAG: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b{{$}} 427; GCN-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], foo@abs32@lo{{$}} 428; GCN: ds_write2_b32 [[PTR]], [[VAL]], [[VAL]] offset1:2 429define amdgpu_kernel void @store_constant_disjoint_offsets() { 430 store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 0), align 4 431 store i32 123, i32 addrspace(3)* getelementptr inbounds ([4 x i32], [4 x i32] addrspace(3)* @foo, i32 0, i32 2), align 4 432 ret void 433} 434 435@bar = addrspace(3) global [4 x i64] undef, align 4 436 437; GCN-LABEL: @store_misaligned64_constant_offsets 438; CI-DAG: s_mov_b32 m0 439; GFX9-NOT: m0 440 441; GCN-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], bar@abs32@lo{{$}} 442; CI-DAG: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1 443; CI-DAG: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3 444 445; GFX9-ALIGNED-DAG: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1 446; GFX9-ALIGNED-DAG: ds_write2_b32 [[PTR]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3 447 448; GFX9-UNALIGNED: ds_write_b128 [[PTR]], {{v\[[0-9]+:[0-9]+\]}} 449 450; GCN: s_endpgm 451define amdgpu_kernel void @store_misaligned64_constant_offsets() { 452 store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4 453 store i64 123, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4 454 ret void 455} 456 457@bar.large = addrspace(3) global [4096 x i64] undef, align 4 458 459; GCN-LABEL: @store_misaligned64_constant_large_offsets 460; CI-DAG: s_mov_b32 m0 461; GFX9-NOT: m0 462 463; GCN-DAG: s_mov_b32 [[SBASE0:s[0-9]+]], bar.large@abs32@lo 464; GCN-DAG: s_add_i32 [[SBASE1:s[0-9]+]], [[SBASE0]], 0x4000{{$}} 465; GCN-DAG: s_addk_i32 [[SBASE0]], 0x7ff8{{$}} 466; GCN-DAG: v_mov_b32_e32 [[VBASE0:v[0-9]+]], [[SBASE0]]{{$}} 467; GCN-DAG: v_mov_b32_e32 [[VBASE1:v[0-9]+]], [[SBASE1]]{{$}} 468; GCN-DAG: ds_write2_b32 [[VBASE0]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1 469; GCN-DAG: ds_write2_b32 [[VBASE1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1 470; GCN: s_endpgm 471define amdgpu_kernel void @store_misaligned64_constant_large_offsets() { 472 store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 2048), align 4 473 store i64 123, i64 addrspace(3)* getelementptr inbounds ([4096 x i64], [4096 x i64] addrspace(3)* @bar.large, i32 0, i32 4095), align 4 474 ret void 475} 476 477@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4 478@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4 479 480define amdgpu_kernel void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, float addrspace(1)* %in) #0 { 481 %x.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #1 482 %y.i = tail call i32 @llvm.amdgcn.workitem.id.y() #1 483 %val = load float, float addrspace(1)* %in 484 %arrayidx44 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i 485 store float %val, float addrspace(3)* %arrayidx44, align 4 486 %add47 = add nsw i32 %x.i, 1 487 %arrayidx48 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add47 488 store float %val, float addrspace(3)* %arrayidx48, align 4 489 %add51 = add nsw i32 %x.i, 16 490 %arrayidx52 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add51 491 store float %val, float addrspace(3)* %arrayidx52, align 4 492 %add55 = add nsw i32 %x.i, 17 493 %arrayidx56 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %add55 494 store float %val, float addrspace(3)* %arrayidx56, align 4 495 %arrayidx60 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %y.i 496 store float %val, float addrspace(3)* %arrayidx60, align 4 497 %add63 = add nsw i32 %y.i, 1 498 %arrayidx64 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add63 499 store float %val, float addrspace(3)* %arrayidx64, align 4 500 %add67 = add nsw i32 %y.i, 32 501 %arrayidx68 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add67 502 store float %val, float addrspace(3)* %arrayidx68, align 4 503 %add71 = add nsw i32 %y.i, 33 504 %arrayidx72 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add71 505 store float %val, float addrspace(3)* %arrayidx72, align 4 506 %add75 = add nsw i32 %y.i, 64 507 %arrayidx76 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add75 508 store float %val, float addrspace(3)* %arrayidx76, align 4 509 %add79 = add nsw i32 %y.i, 65 510 %arrayidx80 = getelementptr inbounds [776 x float], [776 x float] addrspace(3)* @sgemm.lB, i32 0, i32 %add79 511 store float %val, float addrspace(3)* %arrayidx80, align 4 512 ret void 513} 514 515; GCN-LABEL: {{^}}simple_write2_v4f32_superreg_align4: 516; CI: s_mov_b32 m0 517; GFX9-NOT: m0 518 519; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}} 520; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:2 offset1:3{{$}} 521 522; GFX9-ALIGNED-DAG: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}} 523; GFX9-ALIGNED-DAG: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:2 offset1:3{{$}} 524 525; GFX9-UNALIGNED: ds_write_b128 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} 526define amdgpu_kernel void @simple_write2_v4f32_superreg_align4(<4 x float> addrspace(3)* %out, <4 x float> addrspace(1)* %in) #0 { 527 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 528 %in.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in 529 %val0 = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 4 530 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(3)* %out, i32 %x.i 531 store <4 x float> %val0, <4 x float> addrspace(3)* %out.gep, align 4 532 ret void 533} 534 535@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] undef, align 1 536 537; GCN-LABEL: {{^}}write2_v2i32_align1_odd_offset: 538; CI-COUNT-8: ds_write_b8 539 540; GFX9-ALIGNED-COUNT-8: ds_write_b8 541 542; GFX9-UNALIGNED: v_mov_b32_e32 [[BASE_ADDR:v[0-9]+]], 0x41{{$}} 543; GFX9-UNALIGNED: ds_write2_b32 [[BASE_ADDR]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} 544define amdgpu_kernel void @write2_v2i32_align1_odd_offset() { 545entry: 546 store <2 x i32> <i32 123, i32 456>, <2 x i32> addrspace(3)* bitcast (i8 addrspace(3)* getelementptr (i8, i8 addrspace(3)* bitcast ([100 x <2 x i32>] addrspace(3)* @v2i32_align1 to i8 addrspace(3)*), i32 65) to <2 x i32> addrspace(3)*), align 1 547 ret void 548} 549 550declare i32 @llvm.amdgcn.workgroup.id.x() #1 551declare i32 @llvm.amdgcn.workgroup.id.y() #1 552declare i32 @llvm.amdgcn.workitem.id.x() #1 553declare i32 @llvm.amdgcn.workitem.id.y() #1 554 555attributes #0 = { nounwind } 556attributes #1 = { nounwind readnone speculatable } 557attributes #2 = { convergent nounwind } 558