1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s 2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s 3 4declare i32 @llvm.amdgcn.workitem.id.x() #0 5 6@lds.obj = addrspace(3) global [256 x i32] undef, align 4 7 8; GCN-LABEL: {{^}}write_ds_sub0_offset0_global: 9; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0 10; CI: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]] 11; GFX9: v_sub_u32_e32 [[BASEPTR:v[0-9]+]], 0, [[SHL]] 12; GCN: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b 13; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12 14define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 { 15entry: 16 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1 17 %sub1 = sub i32 0, %x.i 18 %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1 19 %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3 20 store i32 123, i32 addrspace(3)* %arrayidx 21 ret void 22} 23 24; GFX9-LABEL: {{^}}write_ds_sub0_offset0_global_clamp_bit: 25; GFX9: v_sub_u32 26; GFX9: s_endpgm 27define amdgpu_kernel void @write_ds_sub0_offset0_global_clamp_bit(float %dummy.val) #0 { 28entry: 29 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1 30 %sub1 = sub i32 0, %x.i 31 %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1 32 %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3 33 store i32 123, i32 addrspace(3)* %arrayidx 34 %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false) 35 store volatile float %fmas, float addrspace(1)* null 36 ret void 37} 38 39; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset: 40; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 41; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 42; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 43; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 44; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535 45define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 { 46 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 47 %neg = sub i32 0, %x.i 48 %shl = shl i32 %neg, 2 49 %add = add i32 65535, %shl 50 %ptr = inttoptr i32 %add to i8 addrspace(3)* 51 store i8 13, i8 addrspace(3)* %ptr 52 ret void 53} 54 55; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset_p1: 56; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 57; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]] 58; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x10000, [[SCALED]] 59; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 60; GCN: ds_write_b8 [[NEG]], [[K]]{{$}} 61define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_p1() #1 { 62 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 63 %neg = sub i32 0, %x.i 64 %shl = shl i32 %neg, 2 65 %add = add i32 65536, %shl 66 %ptr = inttoptr i32 %add to i8 addrspace(3)* 67 store i8 13, i8 addrspace(3)* %ptr 68 ret void 69} 70 71; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use: 72; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 73; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 74; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 75; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 76; GCN-NOT: v_sub 77; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 78; GCN-NOT: v_sub 79; GCN: ds_write_b32 [[NEG]], [[K]] offset:456{{$}} 80; GCN: s_endpgm 81define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use() #1 { 82 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 83 %neg = sub i32 0, %x.i 84 %shl = shl i32 %neg, 2 85 %add0 = add i32 123, %shl 86 %add1 = add i32 456, %shl 87 %ptr0 = inttoptr i32 %add0 to i32 addrspace(3)* 88 store volatile i32 13, i32 addrspace(3)* %ptr0 89 %ptr1 = inttoptr i32 %add1 to i32 addrspace(3)* 90 store volatile i32 13, i32 addrspace(3)* %ptr1 91 ret void 92} 93 94; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use_same_offset: 95; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 96; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 97; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 98; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 99; GCN-NOT: v_sub 100; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 101; GCN-NOT: v_sub 102; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 103; GCN: s_endpgm 104define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use_same_offset() #1 { 105 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 106 %neg = sub i32 0, %x.i 107 %shl = shl i32 %neg, 2 108 %add = add i32 123, %shl 109 %ptr = inttoptr i32 %add to i32 addrspace(3)* 110 store volatile i32 13, i32 addrspace(3)* %ptr 111 store volatile i32 13, i32 addrspace(3)* %ptr 112 ret void 113} 114 115; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset: 116; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 117; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 118; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 119; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255 120define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 { 121 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 122 %neg = sub i32 0, %x.i 123 %shl = shl i32 %neg, 2 124 %add = add i32 1019, %shl 125 %ptr = inttoptr i32 %add to i64 addrspace(3)* 126 store i64 123, i64 addrspace(3)* %ptr, align 4 127 ret void 128} 129 130; GFX9-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit: 131; GFX9: v_sub_u32 132; GFX9: s_endpgm 133define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit(float %dummy.val) #1 { 134 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 135 %neg = sub i32 0, %x.i 136 %shl = shl i32 %neg, 2 137 %add = add i32 1019, %shl 138 %ptr = inttoptr i32 %add to i64 addrspace(3)* 139 store i64 123, i64 addrspace(3)* %ptr, align 4 140 %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false) 141 store volatile float %fmas, float addrspace(1)* null 142 ret void 143} 144 145; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1: 146; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 147; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]] 148; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x3fc, [[SCALED]] 149; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}} 150define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 { 151 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 152 %neg = sub i32 0, %x.i 153 %shl = shl i32 %neg, 2 154 %add = add i32 1020, %shl 155 %ptr = inttoptr i32 %add to i64 addrspace(3)* 156 store i64 123, i64 addrspace(3)* %ptr, align 4 157 ret void 158} 159 160declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) 161 162attributes #0 = { nounwind readnone } 163attributes #1 = { nounwind } 164attributes #2 = { nounwind convergent } 165