1; RUN: llc -march=amdgcn -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s
2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
3; RUN: llc -march=amdgcn -verify-machineinstrs -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
4
5declare i32 @llvm.amdgcn.workitem.id.x() #0
6declare void @llvm.amdgcn.s.barrier() #1
7
8; Function Attrs: nounwind
9; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop:
10; SI: s_movk_i32 [[K_0X88:s[0-9]+]], 0x
11; SI: s_movk_i32 [[K_0X100:s[0-9]+]], 0x100
12; CHECK: BB0_1:
13; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]],
14; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]]
15; SI-DAG: v_add_i32_e32 [[VADDR8:v[0-9]+]], vcc, 8, [[VADDR]]
16; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR8]]
17; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], vcc, 0x80, [[VADDR]]
18; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]]
19; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, [[K_0X88]], [[VADDR]]
20; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x88]]
21; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, [[K_0X100]], [[VADDR]]
22; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]]
23
24; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:2
25; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:34
26; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:256
27; CHECK: s_endpgm
28define amdgpu_kernel void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 {
29entry:
30  %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #0
31  %mul = shl nsw i32 %x.i, 1
32  br label %for.body
33
34for.body:                                         ; preds = %for.body, %entry
35  %sum.03 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ]
36  %offset.02 = phi i32 [ %mul, %entry ], [ %add14, %for.body ]
37  %k.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
38  tail call void @llvm.amdgcn.s.barrier() #1
39  %arrayidx = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %offset.02
40  %tmp = load float, float addrspace(3)* %arrayidx, align 4
41  %add1 = add nsw i32 %offset.02, 2
42  %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add1
43  %tmp1 = load float, float addrspace(3)* %arrayidx2, align 4
44  %add3 = add nsw i32 %offset.02, 32
45  %arrayidx4 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add3
46  %tmp2 = load float, float addrspace(3)* %arrayidx4, align 4
47  %add5 = add nsw i32 %offset.02, 34
48  %arrayidx6 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add5
49  %tmp3 = load float, float addrspace(3)* %arrayidx6, align 4
50  %add7 = add nsw i32 %offset.02, 64
51  %arrayidx8 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add7
52  %tmp4 = load float, float addrspace(3)* %arrayidx8, align 4
53  %add9 = fadd float %tmp, %tmp1
54  %add10 = fadd float %add9, %tmp2
55  %add11 = fadd float %add10, %tmp3
56  %add12 = fadd float %add11, %tmp4
57  %add13 = fadd float %sum.03, %add12
58  %inc = add nsw i32 %k.01, 1
59  %add14 = add nsw i32 %offset.02, 97
60  %exitcond = icmp eq i32 %inc, 8
61  br i1 %exitcond, label %for.end, label %for.body
62
63for.end:                                          ; preds = %for.body
64  %tmp5 = sext i32 %x.i to i64
65  %arrayidx15 = getelementptr inbounds float, float addrspace(1)* %out, i64 %tmp5
66  store float %add13, float addrspace(1)* %arrayidx15, align 4
67  ret void
68}
69
70attributes #0 = { nounwind readnone }
71attributes #1 = { convergent nounwind }
72attributes #2 = { nounwind }
73