1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
3
4; GCN-LABEL: ds_read32_combine_stride_400:
5; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
6; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
7
8; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
9; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
10; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
11
12; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x200, [[BASE]]
13; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
14; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x800, [[BASE]]
15
16; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
17; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:72 offset1:172
18; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:144 offset1:244
19; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B3]] offset0:88 offset1:188
20define amdgpu_kernel void @ds_read32_combine_stride_400(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
21bb:
22  %tmp = load float, float addrspace(3)* %arg, align 4
23  %tmp2 = fadd float %tmp, 0.000000e+00
24  %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
25  %tmp4 = load float, float addrspace(3)* %tmp3, align 4
26  %tmp5 = fadd float %tmp2, %tmp4
27  %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 200
28  %tmp7 = load float, float addrspace(3)* %tmp6, align 4
29  %tmp8 = fadd float %tmp5, %tmp7
30  %tmp9 = getelementptr inbounds float, float addrspace(3)* %arg, i32 300
31  %tmp10 = load float, float addrspace(3)* %tmp9, align 4
32  %tmp11 = fadd float %tmp8, %tmp10
33  %tmp12 = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
34  %tmp13 = load float, float addrspace(3)* %tmp12, align 4
35  %tmp14 = fadd float %tmp11, %tmp13
36  %tmp15 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
37  %tmp16 = load float, float addrspace(3)* %tmp15, align 4
38  %tmp17 = fadd float %tmp14, %tmp16
39  %tmp18 = getelementptr inbounds float, float addrspace(3)* %arg, i32 600
40  %tmp19 = load float, float addrspace(3)* %tmp18, align 4
41  %tmp20 = fadd float %tmp17, %tmp19
42  %tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
43  %tmp22 = load float, float addrspace(3)* %tmp21, align 4
44  %tmp23 = fadd float %tmp20, %tmp22
45  store float %tmp23, float *%arg1, align 4
46  ret void
47}
48
49; GCN-LABEL: ds_read32_combine_stride_20:
50; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
51; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
52
53; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
54; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
55
56; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x400, [[BASE]]
57; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x800, [[BASE]]
58
59; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:144 offset1:164
60; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:184 offset1:204
61; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:224 offset1:244
62; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:8 offset1:28
63define amdgpu_kernel void @ds_read32_combine_stride_20(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
64bb:
65  %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
66  %tmp1 = load float, float addrspace(3)* %tmp, align 4
67  %tmp2 = fadd float %tmp1, 0.000000e+00
68  %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 420
69  %tmp4 = load float, float addrspace(3)* %tmp3, align 4
70  %tmp5 = fadd float %tmp2, %tmp4
71  %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 440
72  %tmp7 = load float, float addrspace(3)* %tmp6, align 4
73  %tmp8 = fadd float %tmp5, %tmp7
74  %tmp9 = getelementptr inbounds float, float addrspace(3)* %arg, i32 460
75  %tmp10 = load float, float addrspace(3)* %tmp9, align 4
76  %tmp11 = fadd float %tmp8, %tmp10
77  %tmp12 = getelementptr inbounds float, float addrspace(3)* %arg, i32 480
78  %tmp13 = load float, float addrspace(3)* %tmp12, align 4
79  %tmp14 = fadd float %tmp11, %tmp13
80  %tmp15 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
81  %tmp16 = load float, float addrspace(3)* %tmp15, align 4
82  %tmp17 = fadd float %tmp14, %tmp16
83  %tmp18 = getelementptr inbounds float, float addrspace(3)* %arg, i32 520
84  %tmp19 = load float, float addrspace(3)* %tmp18, align 4
85  %tmp20 = fadd float %tmp17, %tmp19
86  %tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 540
87  %tmp22 = load float, float addrspace(3)* %tmp21, align 4
88  %tmp23 = fadd float %tmp20, %tmp22
89  store float %tmp23, float *%arg1, align 4
90  ret void
91}
92
93; GCN-LABEL: ds_read32_combine_stride_400_back:
94; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
95; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
96
97; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
98; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
99; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
100
101; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
102; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
103; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x200, [[BASE]]
104
105; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
106; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:88 offset1:188
107; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:144 offset1:244
108; GCN-DAG: ds_read2_b32  v[{{[0-9]+:[0-9]+}}], [[B3]] offset0:72 offset1:172
109define amdgpu_kernel void @ds_read32_combine_stride_400_back(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
110bb:
111  %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
112  %tmp2 = load float, float addrspace(3)* %tmp, align 4
113  %tmp3 = fadd float %tmp2, 0.000000e+00
114  %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 600
115  %tmp5 = load float, float addrspace(3)* %tmp4, align 4
116  %tmp6 = fadd float %tmp3, %tmp5
117  %tmp7 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
118  %tmp8 = load float, float addrspace(3)* %tmp7, align 4
119  %tmp9 = fadd float %tmp6, %tmp8
120  %tmp10 = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
121  %tmp11 = load float, float addrspace(3)* %tmp10, align 4
122  %tmp12 = fadd float %tmp9, %tmp11
123  %tmp13 = getelementptr inbounds float, float addrspace(3)* %arg, i32 300
124  %tmp14 = load float, float addrspace(3)* %tmp13, align 4
125  %tmp15 = fadd float %tmp12, %tmp14
126  %tmp16 = getelementptr inbounds float, float addrspace(3)* %arg, i32 200
127  %tmp17 = load float, float addrspace(3)* %tmp16, align 4
128  %tmp18 = fadd float %tmp15, %tmp17
129  %tmp19 = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
130  %tmp20 = load float, float addrspace(3)* %tmp19, align 4
131  %tmp21 = fadd float %tmp18, %tmp20
132  %tmp22 = load float, float addrspace(3)* %arg, align 4
133  %tmp23 = fadd float %tmp21, %tmp22
134  store float %tmp23, float *%arg1, align 4
135  ret void
136}
137
138; GCN-LABEL: ds_read32_combine_stride_8192:
139; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
140; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
141; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:32
142; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:64 offset1:96
143; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:128 offset1:160
144; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:192 offset1:224
145define amdgpu_kernel void @ds_read32_combine_stride_8192(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
146bb:
147  %tmp = load float, float addrspace(3)* %arg, align 4
148  %tmp2 = fadd float %tmp, 0.000000e+00
149  %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2048
150  %tmp4 = load float, float addrspace(3)* %tmp3, align 4
151  %tmp5 = fadd float %tmp2, %tmp4
152  %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 4096
153  %tmp7 = load float, float addrspace(3)* %tmp6, align 4
154  %tmp8 = fadd float %tmp5, %tmp7
155  %tmp9 = getelementptr inbounds float, float addrspace(3)* %arg, i32 6144
156  %tmp10 = load float, float addrspace(3)* %tmp9, align 4
157  %tmp11 = fadd float %tmp8, %tmp10
158  %tmp12 = getelementptr inbounds float, float addrspace(3)* %arg, i32 8192
159  %tmp13 = load float, float addrspace(3)* %tmp12, align 4
160  %tmp14 = fadd float %tmp11, %tmp13
161  %tmp15 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10240
162  %tmp16 = load float, float addrspace(3)* %tmp15, align 4
163  %tmp17 = fadd float %tmp14, %tmp16
164  %tmp18 = getelementptr inbounds float, float addrspace(3)* %arg, i32 12288
165  %tmp19 = load float, float addrspace(3)* %tmp18, align 4
166  %tmp20 = fadd float %tmp17, %tmp19
167  %tmp21 = getelementptr inbounds float, float addrspace(3)* %arg, i32 14336
168  %tmp22 = load float, float addrspace(3)* %tmp21, align 4
169  %tmp23 = fadd float %tmp20, %tmp22
170  store float %tmp23, float *%arg1, align 4
171  ret void
172}
173
174; GCN-LABEL: ds_read32_combine_stride_8192_shifted:
175; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
176; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
177
178; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
179; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
180
181; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32
182; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:64 offset1:96
183; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:128 offset1:160
184define amdgpu_kernel void @ds_read32_combine_stride_8192_shifted(float addrspace(3)* nocapture readonly %arg, float *nocapture %arg1) {
185bb:
186  %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 2
187  %tmp2 = load float, float addrspace(3)* %tmp, align 4
188  %tmp3 = fadd float %tmp2, 0.000000e+00
189  %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2050
190  %tmp5 = load float, float addrspace(3)* %tmp4, align 4
191  %tmp6 = fadd float %tmp3, %tmp5
192  %tmp7 = getelementptr inbounds float, float addrspace(3)* %arg, i32 4098
193  %tmp8 = load float, float addrspace(3)* %tmp7, align 4
194  %tmp9 = fadd float %tmp6, %tmp8
195  %tmp10 = getelementptr inbounds float, float addrspace(3)* %arg, i32 6146
196  %tmp11 = load float, float addrspace(3)* %tmp10, align 4
197  %tmp12 = fadd float %tmp9, %tmp11
198  %tmp13 = getelementptr inbounds float, float addrspace(3)* %arg, i32 8194
199  %tmp14 = load float, float addrspace(3)* %tmp13, align 4
200  %tmp15 = fadd float %tmp12, %tmp14
201  %tmp16 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10242
202  %tmp17 = load float, float addrspace(3)* %tmp16, align 4
203  %tmp18 = fadd float %tmp15, %tmp17
204  store float %tmp18, float *%arg1, align 4
205  ret void
206}
207
208; GCN-LABEL: ds_read64_combine_stride_400:
209; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
210; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
211
212; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
213; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
214
215; GCN-DAG: ds_read2_b64  v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50
216; GCN-DAG: ds_read2_b64  v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:100 offset1:150
217; GCN-DAG: ds_read2_b64  v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:200 offset1:250
218; GCN-DAG: ds_read2_b64  v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:44 offset1:94
219define amdgpu_kernel void @ds_read64_combine_stride_400(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) {
220bb:
221  %tmp = load double, double addrspace(3)* %arg, align 8
222  %tmp2 = fadd double %tmp, 0.000000e+00
223  %tmp3 = getelementptr inbounds double, double addrspace(3)* %arg, i32 50
224  %tmp4 = load double, double addrspace(3)* %tmp3, align 8
225  %tmp5 = fadd double %tmp2, %tmp4
226  %tmp6 = getelementptr inbounds double, double addrspace(3)* %arg, i32 100
227  %tmp7 = load double, double addrspace(3)* %tmp6, align 8
228  %tmp8 = fadd double %tmp5, %tmp7
229  %tmp9 = getelementptr inbounds double, double addrspace(3)* %arg, i32 150
230  %tmp10 = load double, double addrspace(3)* %tmp9, align 8
231  %tmp11 = fadd double %tmp8, %tmp10
232  %tmp12 = getelementptr inbounds double, double addrspace(3)* %arg, i32 200
233  %tmp13 = load double, double addrspace(3)* %tmp12, align 8
234  %tmp14 = fadd double %tmp11, %tmp13
235  %tmp15 = getelementptr inbounds double, double addrspace(3)* %arg, i32 250
236  %tmp16 = load double, double addrspace(3)* %tmp15, align 8
237  %tmp17 = fadd double %tmp14, %tmp16
238  %tmp18 = getelementptr inbounds double, double addrspace(3)* %arg, i32 300
239  %tmp19 = load double, double addrspace(3)* %tmp18, align 8
240  %tmp20 = fadd double %tmp17, %tmp19
241  %tmp21 = getelementptr inbounds double, double addrspace(3)* %arg, i32 350
242  %tmp22 = load double, double addrspace(3)* %tmp21, align 8
243  %tmp23 = fadd double %tmp20, %tmp22
244  store double %tmp23, double *%arg1, align 8
245  ret void
246}
247
248; GCN-LABEL: ds_read64_combine_stride_8192_shifted:
249; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
250; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
251
252; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]]
253; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]]
254
255; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16
256; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:32 offset1:48
257; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:64 offset1:80
258define amdgpu_kernel void @ds_read64_combine_stride_8192_shifted(double addrspace(3)* nocapture readonly %arg, double *nocapture %arg1) {
259bb:
260  %tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 1
261  %tmp2 = load double, double addrspace(3)* %tmp, align 8
262  %tmp3 = fadd double %tmp2, 0.000000e+00
263  %tmp4 = getelementptr inbounds double, double addrspace(3)* %arg, i32 1025
264  %tmp5 = load double, double addrspace(3)* %tmp4, align 8
265  %tmp6 = fadd double %tmp3, %tmp5
266  %tmp7 = getelementptr inbounds double, double addrspace(3)* %arg, i32 2049
267  %tmp8 = load double, double addrspace(3)* %tmp7, align 8
268  %tmp9 = fadd double %tmp6, %tmp8
269  %tmp10 = getelementptr inbounds double, double addrspace(3)* %arg, i32 3073
270  %tmp11 = load double, double addrspace(3)* %tmp10, align 8
271  %tmp12 = fadd double %tmp9, %tmp11
272  %tmp13 = getelementptr inbounds double, double addrspace(3)* %arg, i32 4097
273  %tmp14 = load double, double addrspace(3)* %tmp13, align 8
274  %tmp15 = fadd double %tmp12, %tmp14
275  %tmp16 = getelementptr inbounds double, double addrspace(3)* %arg, i32 5121
276  %tmp17 = load double, double addrspace(3)* %tmp16, align 8
277  %tmp18 = fadd double %tmp15, %tmp17
278  store double %tmp18, double *%arg1, align 8
279  ret void
280}
281
282; GCN-LABEL: ds_write32_combine_stride_400:
283; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
284; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
285
286; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
287; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
288; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
289
290; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x200, [[BASE]]
291; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
292; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x800, [[BASE]]
293
294; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
295; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset0:72 offset1:172
296; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset0:144 offset1:244
297; GCN-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset0:88 offset1:188
298define amdgpu_kernel void @ds_write32_combine_stride_400(float addrspace(3)* nocapture %arg) {
299bb:
300  store float 1.000000e+00, float addrspace(3)* %arg, align 4
301  %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
302  store float 1.000000e+00, float addrspace(3)* %tmp, align 4
303  %tmp1 = getelementptr inbounds float, float addrspace(3)* %arg, i32 200
304  store float 1.000000e+00, float addrspace(3)* %tmp1, align 4
305  %tmp2 = getelementptr inbounds float, float addrspace(3)* %arg, i32 300
306  store float 1.000000e+00, float addrspace(3)* %tmp2, align 4
307  %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
308  store float 1.000000e+00, float addrspace(3)* %tmp3, align 4
309  %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
310  store float 1.000000e+00, float addrspace(3)* %tmp4, align 4
311  %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 600
312  store float 1.000000e+00, float addrspace(3)* %tmp5, align 4
313  %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
314  store float 1.000000e+00, float addrspace(3)* %tmp6, align 4
315  ret void
316}
317
318; GCN-LABEL: ds_write32_combine_stride_400_back:
319; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
320; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
321
322; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
323; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
324; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
325
326; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
327; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x400, [[BASE]]
328; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x200, [[BASE]]
329
330; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset0:88 offset1:188
331; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset0:144 offset1:244
332; GCN-DAG: ds_write2_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset0:72 offset1:172
333; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100
334define amdgpu_kernel void @ds_write32_combine_stride_400_back(float addrspace(3)* nocapture %arg) {
335bb:
336  %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 700
337  store float 1.000000e+00, float addrspace(3)* %tmp, align 4
338  %tmp1 = getelementptr inbounds float, float addrspace(3)* %arg, i32 600
339  store float 1.000000e+00, float addrspace(3)* %tmp1, align 4
340  %tmp2 = getelementptr inbounds float, float addrspace(3)* %arg, i32 500
341  store float 1.000000e+00, float addrspace(3)* %tmp2, align 4
342  %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 400
343  store float 1.000000e+00, float addrspace(3)* %tmp3, align 4
344  %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 300
345  store float 1.000000e+00, float addrspace(3)* %tmp4, align 4
346  %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 200
347  store float 1.000000e+00, float addrspace(3)* %tmp5, align 4
348  %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 100
349  store float 1.000000e+00, float addrspace(3)* %tmp6, align 4
350  store float 1.000000e+00, float addrspace(3)* %arg, align 4
351  ret void
352}
353
354; GCN-LABEL: ds_write32_combine_stride_8192:
355; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
356; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
357; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
358; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:64 offset1:96
359; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:128 offset1:160
360; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:192 offset1:224
361define amdgpu_kernel void @ds_write32_combine_stride_8192(float addrspace(3)* nocapture %arg) {
362bb:
363  store float 1.000000e+00, float addrspace(3)* %arg, align 4
364  %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 2048
365  store float 1.000000e+00, float addrspace(3)* %tmp, align 4
366  %tmp1 = getelementptr inbounds float, float addrspace(3)* %arg, i32 4096
367  store float 1.000000e+00, float addrspace(3)* %tmp1, align 4
368  %tmp2 = getelementptr inbounds float, float addrspace(3)* %arg, i32 6144
369  store float 1.000000e+00, float addrspace(3)* %tmp2, align 4
370  %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 8192
371  store float 1.000000e+00, float addrspace(3)* %tmp3, align 4
372  %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10240
373  store float 1.000000e+00, float addrspace(3)* %tmp4, align 4
374  %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 12288
375  store float 1.000000e+00, float addrspace(3)* %tmp5, align 4
376  %tmp6 = getelementptr inbounds float, float addrspace(3)* %arg, i32 14336
377  store float 1.000000e+00, float addrspace(3)* %tmp6, align 4
378  ret void
379}
380
381; GCN-LABEL: ds_write32_combine_stride_8192_shifted:
382; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
383; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
384
385; VI-DAG: v_add_u32_e32 [[BASE:v[0-9]+]], vcc, 4, [[BASE]]
386; GFX9-DAG: v_add_u32_e32 [[BASE:v[0-9]+]], 4, [[BASE]]
387
388; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32
389; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:64 offset1:96
390; GCN-DAG: ds_write2st64_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset0:128 offset1:160
391define amdgpu_kernel void @ds_write32_combine_stride_8192_shifted(float addrspace(3)* nocapture %arg) {
392bb:
393  %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 1
394  store float 1.000000e+00, float addrspace(3)* %tmp, align 4
395  %tmp1 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2049
396  store float 1.000000e+00, float addrspace(3)* %tmp1, align 4
397  %tmp2 = getelementptr inbounds float, float addrspace(3)* %arg, i32 4097
398  store float 1.000000e+00, float addrspace(3)* %tmp2, align 4
399  %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 6145
400  store float 1.000000e+00, float addrspace(3)* %tmp3, align 4
401  %tmp4 = getelementptr inbounds float, float addrspace(3)* %arg, i32 8193
402  store float 1.000000e+00, float addrspace(3)* %tmp4, align 4
403  %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 10241
404  store float 1.000000e+00, float addrspace(3)* %tmp5, align 4
405  ret void
406}
407
408; GCN-LABEL: ds_write64_combine_stride_400:
409; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
410; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
411
412; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, {{s[0-9]+}}, [[BASE]]
413; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x800, [[BASE]]
414
415; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50
416; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:100 offset1:150
417; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:200 offset1:250
418; GCN-DAG: ds_write2_b64 [[B1]],   v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:44 offset1:94
419define amdgpu_kernel void @ds_write64_combine_stride_400(double addrspace(3)* nocapture %arg) {
420bb:
421  store double 1.000000e+00, double addrspace(3)* %arg, align 8
422  %tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 50
423  store double 1.000000e+00, double addrspace(3)* %tmp, align 8
424  %tmp1 = getelementptr inbounds double, double addrspace(3)* %arg, i32 100
425  store double 1.000000e+00, double addrspace(3)* %tmp1, align 8
426  %tmp2 = getelementptr inbounds double, double addrspace(3)* %arg, i32 150
427  store double 1.000000e+00, double addrspace(3)* %tmp2, align 8
428  %tmp3 = getelementptr inbounds double, double addrspace(3)* %arg, i32 200
429  store double 1.000000e+00, double addrspace(3)* %tmp3, align 8
430  %tmp4 = getelementptr inbounds double, double addrspace(3)* %arg, i32 250
431  store double 1.000000e+00, double addrspace(3)* %tmp4, align 8
432  %tmp5 = getelementptr inbounds double, double addrspace(3)* %arg, i32 300
433  store double 1.000000e+00, double addrspace(3)* %tmp5, align 8
434  %tmp6 = getelementptr inbounds double, double addrspace(3)* %arg, i32 350
435  store double 1.000000e+00, double addrspace(3)* %tmp6, align 8
436  ret void
437}
438
439; GCN-LABEL: ds_write64_combine_stride_8192_shifted:
440; GCN:     s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0
441; GCN:     v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]]
442
443; VI-DAG: v_add_u32_e32 [[BASE]], vcc, 8, [[BASE]]
444; GFX9-DAG: v_add_u32_e32 [[BASE]], 8, [[BASE]]
445
446; GCN-DAG: ds_write2st64_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16
447; GCN-DAG: ds_write2st64_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:32 offset1:48
448; GCN-DAG: ds_write2st64_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:64 offset1:80
449define amdgpu_kernel void @ds_write64_combine_stride_8192_shifted(double addrspace(3)* nocapture %arg) {
450bb:
451  %tmp = getelementptr inbounds double, double addrspace(3)* %arg, i32 1
452  store double 1.000000e+00, double addrspace(3)* %tmp, align 8
453  %tmp1 = getelementptr inbounds double, double addrspace(3)* %arg, i32 1025
454  store double 1.000000e+00, double addrspace(3)* %tmp1, align 8
455  %tmp2 = getelementptr inbounds double, double addrspace(3)* %arg, i32 2049
456  store double 1.000000e+00, double addrspace(3)* %tmp2, align 8
457  %tmp3 = getelementptr inbounds double, double addrspace(3)* %arg, i32 3073
458  store double 1.000000e+00, double addrspace(3)* %tmp3, align 8
459  %tmp4 = getelementptr inbounds double, double addrspace(3)* %arg, i32 4097
460  store double 1.000000e+00, double addrspace(3)* %tmp4, align 8
461  %tmp5 = getelementptr inbounds double, double addrspace(3)* %arg, i32 5121
462  store double 1.000000e+00, double addrspace(3)* %tmp5, align 8
463  ret void
464}
465