1; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,GFX90A
2; RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,DPPMOV64
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10
4
5; GCN-LABEL: {{^}}dpp64_ceil:
6; GCN:           global_load_dwordx2 [[V:v\[[0-9:]+\]]],
7; DPP64:         v_ceil_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
8; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
9define amdgpu_kernel void @dpp64_ceil(i64 addrspace(1)* %arg, i64 %in1) {
10  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
11  %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
12  %load = load i64, i64 addrspace(1)* %gep
13  %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
14  %tmp1 = bitcast i64 %tmp0 to double
15  %round = tail call double @llvm.ceil.f64(double %tmp1)
16  %tmp2 = bitcast double %round to i64
17  store i64 %tmp2, i64 addrspace(1)* %gep
18  ret void
19}
20
21; GCN-LABEL: {{^}}dpp64_rcp:
22; GCN:           global_load_dwordx2 [[V:v\[[0-9:]+\]]],
23; DPP64:         v_rcp_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
24; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
25define amdgpu_kernel void @dpp64_rcp(i64 addrspace(1)* %arg, i64 %in1) {
26  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
27  %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
28  %load = load i64, i64 addrspace(1)* %gep
29  %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
30  %tmp1 = bitcast i64 %tmp0 to double
31  %rcp = call double @llvm.amdgcn.rcp.f64(double %tmp1)
32  %tmp2 = bitcast double %rcp to i64
33  store i64 %tmp2, i64 addrspace(1)* %gep
34  ret void
35}
36
37; GCN-LABEL: {{^}}dpp64_rcp_unsupported_ctl:
38; GCN-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
39; GCN:         v_rcp_f64_e32
40define amdgpu_kernel void @dpp64_rcp_unsupported_ctl(i64 addrspace(1)* %arg, i64 %in1) {
41  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
42  %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
43  %load = load i64, i64 addrspace(1)* %gep
44  %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 15, i32 15, i1 1) #0
45  %tmp1 = bitcast i64 %tmp0 to double
46  %rcp = fdiv fast double 1.0, %tmp1
47  %tmp2 = bitcast double %rcp to i64
48  store i64 %tmp2, i64 addrspace(1)* %gep
49  ret void
50}
51
52; GCN-LABEL: {{^}}dpp64_div:
53; GCN:            global_load_dwordx2 [[V:v\[[0-9:]+\]]],
54; DPPMOV64:       v_mov_b64_dpp v[{{[0-9:]+}}], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
55; GFX90A-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
56; GFX10-COUNT-2:  v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
57; GCN:            v_div_scale_f64
58; GCN:            v_rcp_f64_e32
59define amdgpu_kernel void @dpp64_div(i64 addrspace(1)* %arg, i64 %in1) {
60  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
61  %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
62  %load = load i64, i64 addrspace(1)* %gep
63  %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
64  %tmp1 = bitcast i64 %tmp0 to double
65  %rcp = fdiv double 15.0, %tmp1
66  %tmp2 = bitcast double %rcp to i64
67  store i64 %tmp2, i64 addrspace(1)* %gep
68  ret void
69}
70
71declare i32 @llvm.amdgcn.workitem.id.x()
72declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32, i32, i32, i1) #0
73declare double @llvm.ceil.f64(double)
74declare double @llvm.amdgcn.rcp.f64(double)
75
76attributes #0 = { nounwind readnone convergent }
77