1; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -O0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}eq_t:
4; GCN-DAG: s_load_dword [[X:s[0-9]+]]
5; GCN-DAG: s_mov_b32 [[SONE:s[0-9]+]], 1.0
6; GCN-DAG: v_mov_b32_e32 [[VONE:v[0-9]+]], [[SONE]]
7; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[VONE]]{{$}}
8; GCN-NOT: 0xddd5
9; GCN-NOT: v_cndmask_b32
10; GCN-NOT: v_cmp_eq_u32
11; GCN-NOT: v_cndmask_b32
12; GCN-DAG: s_mov_b32 [[STWO:s[0-9]+]], 2.0
13; GCN-DAG: v_mov_b32_e32 [[VTWO:v[0-9]+]], [[STWO]]
14; GCN-DAG: s_mov_b32 [[SFOUR:s[0-9]+]], 4.0
15; GCN-DAG: v_mov_b32_e32 [[VFOUR:v[0-9]+]], [[SFOUR]]
16; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[VTWO]], [[VFOUR]], [[CC]]
17; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
18define amdgpu_kernel void @eq_t(float %x) {
19  %c1 = fcmp olt float %x, 1.0
20  %s1 = select i1 %c1, i32 56789, i32 1
21  %c2 = icmp eq i32 %s1, 56789
22  %s2 = select i1 %c2, float 4.0, float 2.0
23  store float %s2, float* undef, align 4
24  ret void
25}
26
27; GCN-LABEL: {{^}}ne_t:
28; GCN-DAG: s_load_dword [[X:s[0-9]+]]
29; GCN-DAG: s_mov_b32 [[SONE:s[0-9]+]], 1.0
30; GCN-DAG: v_mov_b32_e32 [[VONE:v[0-9]+]], [[SONE]]
31; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[VONE]]{{$}}
32; GCN-NOT: 0xddd5
33; GCN-NOT: v_cndmask_b32
34; GCN-NOT: v_cmp_eq_u32
35; GCN-NOT: v_cndmask_b32
36; GCN-DAG: s_mov_b32 [[STWO:s[0-9]+]], 2.0
37; GCN-DAG: v_mov_b32_e32 [[VTWO:v[0-9]+]], [[STWO]]
38; GCN-DAG: s_mov_b32 [[SFOUR:s[0-9]+]], 4.0
39; GCN-DAG: v_mov_b32_e32 [[VFOUR:v[0-9]+]], [[SFOUR]]
40; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[VFOUR]], [[VTWO]], [[CC]]
41; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
42define amdgpu_kernel void @ne_t(float %x) {
43  %c1 = fcmp olt float %x, 1.0
44  %s1 = select i1 %c1, i32 56789, i32 1
45  %c2 = icmp ne i32 %s1, 56789
46  %s2 = select i1 %c2, float 4.0, float 2.0
47  store float %s2, float* undef, align 4
48  ret void
49}
50
51; GCN-LABEL: {{^}}eq_f:
52; GCN-DAG: s_load_dword [[X:s[0-9]+]]
53; GCN-DAG: s_mov_b32 [[SONE:s[0-9]+]], 1.0
54; GCN-DAG: v_mov_b32_e32 [[VONE:v[0-9]+]], [[SONE]]
55; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[VONE]]{{$}}
56; GCN-NOT: 0xddd5
57; GCN-NOT: v_cndmask_b32
58; GCN-NOT: v_cmp_eq_u32
59; GCN-NOT: v_cndmask_b32
60; GCN-DAG: s_mov_b32 [[STWO:s[0-9]+]], 2.0
61; GCN-DAG: v_mov_b32_e32 [[VTWO:v[0-9]+]], [[STWO]]
62; GCN-DAG: s_mov_b32 [[SFOUR:s[0-9]+]], 4.0
63; GCN-DAG: v_mov_b32_e32 [[VFOUR:v[0-9]+]], [[SFOUR]]
64; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[VFOUR]], [[VTWO]], [[CC]]
65; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
66define amdgpu_kernel void @eq_f(float %x) {
67  %c1 = fcmp olt float %x, 1.0
68  %s1 = select i1 %c1, i32 1, i32 56789
69  %c2 = icmp eq i32 %s1, 56789
70  %s2 = select i1 %c2, float 4.0, float 2.0
71  store float %s2, float* undef, align 4
72  ret void
73}
74
75; GCN-LABEL: {{^}}ne_f:
76; GCN-DAG: s_load_dword [[X:s[0-9]+]]
77; GCN-DAG: s_mov_b32 [[SONE:s[0-9]+]], 1.0
78; GCN-DAG: v_mov_b32_e32 [[VONE:v[0-9]+]], [[SONE]]
79; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[VONE]]{{$}}
80; GCN-NOT: 0xddd5
81; GCN-NOT: v_cndmask_b32
82; GCN-NOT: v_cmp_eq_u32
83; GCN-NOT: v_cndmask_b32
84; GCN-DAG: s_mov_b32 [[STWO:s[0-9]+]], 2.0
85; GCN-DAG: v_mov_b32_e32 [[VTWO:v[0-9]+]], [[STWO]]
86; GCN-DAG: s_mov_b32 [[SFOUR:s[0-9]+]], 4.0
87; GCN-DAG: v_mov_b32_e32 [[VFOUR:v[0-9]+]], [[SFOUR]]
88; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[VTWO]], [[VFOUR]], [[CC]]
89; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
90define amdgpu_kernel void @ne_f(float %x) {
91  %c1 = fcmp olt float %x, 1.0
92  %s1 = select i1 %c1, i32 1, i32 56789
93  %c2 = icmp ne i32 %s1, 56789
94  %s2 = select i1 %c2, float 4.0, float 2.0
95  store float %s2, float* undef, align 4
96  ret void
97}
98
99; GCN-LABEL: {{^}}different_constants:
100; GCN-DAG: s_load_dword [[X:s[0-9]+]]
101; GCN-DAG: s_mov_b32 [[SONE:s[0-9]+]], 1.0
102; GCN-DAG: v_mov_b32_e32 [[VONE:v[0-9]+]], [[SONE]]
103; GCN-DAG: v_cmp_lt_f32_e{{32|64}} [[CC1:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[VONE]]{{$}}
104; GCN-DAG: v_cndmask_b32_e{{32|64}} [[CND1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}, [[CC1]]
105; GCN-DAG: v_cmp_eq_u32_e{{32|64}} [[CC2:s\[[0-9]+:[0-9]+\]|vcc]], s{{[0-9]+}}, v{{[0-9]+}}{{$}}
106; GCN-DAG: s_mov_b32 [[STWO:s[0-9]+]], 2.0
107; GCN-DAG: v_mov_b32_e32 [[VTWO:v[0-9]+]], [[STWO]]
108; GCN-DAG: s_mov_b32 [[SFOUR:s[0-9]+]], 4.0
109; GCN-DAG: v_mov_b32_e32 [[VFOUR:v[0-9]+]], [[SFOUR]]
110; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[VTWO]], [[VFOUR]], [[CC2]]
111; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
112define amdgpu_kernel void @different_constants(float %x) {
113  %c1 = fcmp olt float %x, 1.0
114  %s1 = select i1 %c1, i32 56789, i32 1
115  %c2 = icmp eq i32 %s1, 5678
116  %s2 = select i1 %c2, float 4.0, float 2.0
117  store float %s2, float* undef, align 4
118  ret void
119}
120