1; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}eq_t:
4; GCN-DAG: s_load_dword [[X:s[0-9]+]]
5; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], 1.0{{$}}
6; GCN-NOT: 0xddd5
7; GCN-NOT: v_cndmask_b32
8; GCN-NOT: v_cmp_eq_u32
9; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], 2.0, 4.0, [[CC]]
10; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
11define amdgpu_kernel void @eq_t(float %x) {
12  %c1 = fcmp olt float %x, 1.0
13  %s1 = select i1 %c1, i32 56789, i32 1
14  %c2 = icmp eq i32 %s1, 56789
15  %s2 = select i1 %c2, float 4.0, float 2.0
16  store float %s2, float* undef, align 4
17  ret void
18}
19
20; GCN-LABEL: {{^}}ne_t:
21; GCN-DAG: s_load_dword [[X:s[0-9]+]]
22; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], 1.0{{$}}
23; GCN-NOT: 0xddd5
24; GCN-NOT: v_cndmask_b32
25; GCN-NOT: v_cmp_eq_u32
26; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], 4.0, 2.0, [[CC]]
27; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
28define amdgpu_kernel void @ne_t(float %x) {
29  %c1 = fcmp olt float %x, 1.0
30  %s1 = select i1 %c1, i32 56789, i32 1
31  %c2 = icmp ne i32 %s1, 56789
32  %s2 = select i1 %c2, float 4.0, float 2.0
33  store float %s2, float* undef, align 4
34  ret void
35}
36
37; GCN-LABEL: {{^}}eq_f:
38; GCN-DAG: s_load_dword [[X:s[0-9]+]]
39; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], 1.0{{$}}
40; GCN-NOT: 0xddd5
41; GCN-NOT: v_cndmask_b32
42; GCN-NOT: v_cmp_eq_u32
43; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], 4.0, 2.0, [[CC]]
44; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
45define amdgpu_kernel void @eq_f(float %x) {
46  %c1 = fcmp olt float %x, 1.0
47  %s1 = select i1 %c1, i32 1, i32 56789
48  %c2 = icmp eq i32 %s1, 56789
49  %s2 = select i1 %c2, float 4.0, float 2.0
50  store float %s2, float* undef, align 4
51  ret void
52}
53
54; GCN-LABEL: {{^}}ne_f:
55; GCN-DAG: s_load_dword [[X:s[0-9]+]]
56; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], 1.0{{$}}
57; GCN-NOT: 0xddd5
58; GCN-NOT: v_cndmask_b32
59; GCN-NOT: v_cmp_eq_u32
60; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], 2.0, 4.0, [[CC]]
61; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
62define amdgpu_kernel void @ne_f(float %x) {
63  %c1 = fcmp olt float %x, 1.0
64  %s1 = select i1 %c1, i32 1, i32 56789
65  %c2 = icmp ne i32 %s1, 56789
66  %s2 = select i1 %c2, float 4.0, float 2.0
67  store float %s2, float* undef, align 4
68  ret void
69}
70
71; GCN-LABEL: {{^}}different_constants:
72; GCN: v_mov_b32_e32 [[RES:v[0-9]+]], 2.0
73; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
74define amdgpu_kernel void @different_constants(float %x) {
75  %c1 = fcmp olt float %x, 1.0
76  %s1 = select i1 %c1, i32 56789, i32 1
77  %c2 = icmp eq i32 %s1, 5678
78  %s2 = select i1 %c2, float 4.0, float 2.0
79  store float %s2, float* undef, align 4
80  ret void
81}
82