1; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s 2 3; GCN-LABEL: {{^}}select_and1: 4; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 5; GCN-NOT: v_and_b32 6; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 7define amdgpu_kernel void @select_and1(i32 addrspace(1)* %p, i32 %x, i32 %y) { 8 %c = icmp slt i32 %x, 11 9 %s = select i1 %c, i32 0, i32 -1 10 %a = and i32 %y, %s 11 store i32 %a, i32 addrspace(1)* %p, align 4 12 ret void 13} 14 15; GCN-LABEL: {{^}}select_and2: 16; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 17; GCN-NOT: v_and_b32 18; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 19define amdgpu_kernel void @select_and2(i32 addrspace(1)* %p, i32 %x, i32 %y) { 20 %c = icmp slt i32 %x, 11 21 %s = select i1 %c, i32 0, i32 -1 22 %a = and i32 %s, %y 23 store i32 %a, i32 addrspace(1)* %p, align 4 24 ret void 25} 26 27; GCN-LABEL: {{^}}select_and3: 28; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 29; GCN-NOT: v_and_b32 30; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 31define amdgpu_kernel void @select_and3(i32 addrspace(1)* %p, i32 %x, i32 %y) { 32 %c = icmp slt i32 %x, 11 33 %s = select i1 %c, i32 -1, i32 0 34 %a = and i32 %y, %s 35 store i32 %a, i32 addrspace(1)* %p, align 4 36 ret void 37} 38 39; GCN-LABEL: {{^}}select_and_v4: 40; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 41; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 42; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 43; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, v{{[0-9]+}}, 44; GCN-NOT: v_and_b32 45; GCN: store_dword 46define amdgpu_kernel void @select_and_v4(<4 x i32> addrspace(1)* %p, i32 %x, <4 x i32> %y) { 47 %c = icmp slt i32 %x, 11 48 %s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 49 %a = and <4 x i32> %s, %y 50 store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32 51 ret void 52} 53 54; GCN-LABEL: {{^}}select_or1: 55; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 56; GCN-NOT: v_or_b32 57; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 58define amdgpu_kernel void @select_or1(i32 addrspace(1)* %p, i32 %x, i32 %y) { 59 %c = icmp slt i32 %x, 11 60 %s = select i1 %c, i32 0, i32 -1 61 %a = or i32 %y, %s 62 store i32 %a, i32 addrspace(1)* %p, align 4 63 ret void 64} 65 66; GCN-LABEL: {{^}}select_or2: 67; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 68; GCN-NOT: v_or_b32 69; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 70define amdgpu_kernel void @select_or2(i32 addrspace(1)* %p, i32 %x, i32 %y) { 71 %c = icmp slt i32 %x, 11 72 %s = select i1 %c, i32 0, i32 -1 73 %a = or i32 %s, %y 74 store i32 %a, i32 addrspace(1)* %p, align 4 75 ret void 76} 77 78; GCN-LABEL: {{^}}select_or3: 79; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 80; GCN-NOT: v_or_b32 81; GCN: store_dword v[{{[0-9:]+}}], [[SEL]], 82define amdgpu_kernel void @select_or3(i32 addrspace(1)* %p, i32 %x, i32 %y) { 83 %c = icmp slt i32 %x, 11 84 %s = select i1 %c, i32 -1, i32 0 85 %a = or i32 %y, %s 86 store i32 %a, i32 addrspace(1)* %p, align 4 87 ret void 88} 89 90; GCN-LABEL: {{^}}select_or_v4: 91; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 92; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 93; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 94; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], -1, v{{[0-9]+}}, 95; GCN-NOT: v_or_b32 96; GCN: store_dword 97define amdgpu_kernel void @select_or_v4(<4 x i32> addrspace(1)* %p, i32 %x, <4 x i32> %y) { 98 %c = icmp slt i32 %x, 11 99 %s = select i1 %c, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 100 %a = or <4 x i32> %s, %y 101 store <4 x i32> %a, <4 x i32> addrspace(1)* %p, align 32 102 ret void 103} 104 105; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants: 106; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9, 107define amdgpu_kernel void @sel_constants_sub_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) { 108 %sel = select i1 %cond, i32 -4, i32 3 109 %bo = sub i32 5, %sel 110 store i32 %bo, i32 addrspace(1)* %p, align 4 111 ret void 112} 113 114; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_i16: 115; GCN: v_cndmask_b32_e64 v2, 2, 9, 116define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16(i16 addrspace(1)* %p, i1 %cond) { 117 %sel = select i1 %cond, i16 -4, i16 3 118 %bo = sub i16 5, %sel 119 store i16 %bo, i16 addrspace(1)* %p, align 2 120 ret void 121} 122 123; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_i16_neg: 124; GCN: v_mov_b32_e32 [[F:v[0-9]+]], 0xfffff449 125; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, [[F]], -3, 126define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_i16_neg(i16 addrspace(1)* %p, i1 %cond) { 127 %sel = select i1 %cond, i16 4, i16 3000 128 %bo = sub i16 1, %sel 129 store i16 %bo, i16 addrspace(1)* %p, align 2 130 ret void 131} 132 133; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v2i16: 134; GCN-DAG: v_mov_b32_e32 [[F:v[0-9]+]], 0x60002 135; GCN-DAG: v_mov_b32_e32 [[T:v[0-9]+]], 0x50009 136; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, [[F]], [[T]], 137define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v2i16(<2 x i16> addrspace(1)* %p, i1 %cond) { 138 %sel = select i1 %cond, <2 x i16> <i16 -4, i16 2>, <2 x i16> <i16 3, i16 1> 139 %bo = sub <2 x i16> <i16 5, i16 7>, %sel 140 store <2 x i16> %bo, <2 x i16> addrspace(1)* %p, align 4 141 ret void 142} 143 144; GCN-LABEL: {{^}}sel_constants_sub_constant_sel_constants_v4i32: 145; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 9, 146; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 6, 5, 147; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 10, 6, 148; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 14, 7, 149define amdgpu_kernel void @sel_constants_sub_constant_sel_constants_v4i32(<4 x i32> addrspace(1)* %p, i1 %cond) { 150 %sel = select i1 %cond, <4 x i32> <i32 -4, i32 2, i32 3, i32 4>, <4 x i32> <i32 3, i32 1, i32 -1, i32 -3> 151 %bo = sub <4 x i32> <i32 5, i32 7, i32 9, i32 11>, %sel 152 store <4 x i32> %bo, <4 x i32> addrspace(1)* %p, align 32 153 ret void 154} 155 156; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i64: 157; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 5, 0, 158define amdgpu_kernel void @sdiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) { 159 %sel = select i1 %cond, i64 121, i64 23 160 %bo = sdiv i64 120, %sel 161 store i64 %bo, i64 addrspace(1)* %p, align 8 162 ret void 163} 164 165; GCN-LABEL: {{^}}sdiv_constant_sel_constants_i32: 166; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 8, 26, 167define amdgpu_kernel void @sdiv_constant_sel_constants_i32(i32 addrspace(1)* %p, i1 %cond) { 168 %sel = select i1 %cond, i32 7, i32 23 169 %bo = sdiv i32 184, %sel 170 store i32 %bo, i32 addrspace(1)* %p, align 8 171 ret void 172} 173 174; GCN-LABEL: {{^}}udiv_constant_sel_constants_i64: 175; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 5, 0, 176define amdgpu_kernel void @udiv_constant_sel_constants_i64(i64 addrspace(1)* %p, i1 %cond) { 177 %sel = select i1 %cond, i64 -4, i64 23 178 %bo = udiv i64 120, %sel 179 store i64 %bo, i64 addrspace(1)* %p, align 8 180 ret void 181} 182 183; GCN-LABEL: {{^}}srem_constant_sel_constants: 184; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 3, 33, 185define amdgpu_kernel void @srem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) { 186 %sel = select i1 %cond, i64 34, i64 15 187 %bo = srem i64 33, %sel 188 store i64 %bo, i64 addrspace(1)* %p, align 8 189 ret void 190} 191 192; GCN-LABEL: {{^}}urem_constant_sel_constants: 193; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 3, 33, 194define amdgpu_kernel void @urem_constant_sel_constants(i64 addrspace(1)* %p, i1 %cond) { 195 %sel = select i1 %cond, i64 34, i64 15 196 %bo = urem i64 33, %sel 197 store i64 %bo, i64 addrspace(1)* %p, align 8 198 ret void 199} 200 201; GCN-LABEL: {{^}}shl_constant_sel_constants: 202; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 8, 4, 203define amdgpu_kernel void @shl_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) { 204 %sel = select i1 %cond, i32 2, i32 3 205 %bo = shl i32 1, %sel 206 store i32 %bo, i32 addrspace(1)* %p, align 4 207 ret void 208} 209 210; GCN-LABEL: {{^}}lshr_constant_sel_constants: 211; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 8, 16, 212define amdgpu_kernel void @lshr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) { 213 %sel = select i1 %cond, i32 2, i32 3 214 %bo = lshr i32 64, %sel 215 store i32 %bo, i32 addrspace(1)* %p, align 4 216 ret void 217} 218 219; GCN-LABEL: {{^}}ashr_constant_sel_constants: 220; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 16, 32, 221define amdgpu_kernel void @ashr_constant_sel_constants(i32 addrspace(1)* %p, i1 %cond) { 222 %sel = select i1 %cond, i32 2, i32 3 223 %bo = ashr i32 128, %sel 224 store i32 %bo, i32 addrspace(1)* %p, align 4 225 ret void 226} 227 228; GCN-LABEL: {{^}}fsub_constant_sel_constants: 229; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, -4.0, 1.0, 230define amdgpu_kernel void @fsub_constant_sel_constants(float addrspace(1)* %p, i1 %cond) { 231 %sel = select i1 %cond, float -2.0, float 3.0 232 %bo = fsub float -1.0, %sel 233 store float %bo, float addrspace(1)* %p, align 4 234 ret void 235} 236 237; GCN-LABEL: {{^}}fsub_constant_sel_constants_f16: 238; TODO: it shall be possible to fold constants with OpSel 239; GCN-DAG: v_mov_b32_e32 [[T:v[0-9]+]], 0x3c00 240; GCN-DAG: v_mov_b32_e32 [[F:v[0-9]+]], 0xc400 241; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, [[F]], [[T]], 242define amdgpu_kernel void @fsub_constant_sel_constants_f16(half addrspace(1)* %p, i1 %cond) { 243 %sel = select i1 %cond, half -2.0, half 3.0 244 %bo = fsub half -1.0, %sel 245 store half %bo, half addrspace(1)* %p, align 2 246 ret void 247} 248 249; GCN-LABEL: {{^}}fsub_constant_sel_constants_v2f16: 250; GCN-DAG: v_mov_b32_e32 [[T:v[0-9]+]], 0x45003c00 251; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, -2.0, [[T]], 252define amdgpu_kernel void @fsub_constant_sel_constants_v2f16(<2 x half> addrspace(1)* %p, i1 %cond) { 253 %sel = select i1 %cond, <2 x half> <half -2.0, half -3.0>, <2 x half> <half -1.0, half 4.0> 254 %bo = fsub <2 x half> <half -1.0, half 2.0>, %sel 255 store <2 x half> %bo, <2 x half> addrspace(1)* %p, align 4 256 ret void 257} 258 259; GCN-LABEL: {{^}}fsub_constant_sel_constants_v4f32: 260; GCN-DAG: v_mov_b32_e32 [[T2:v[0-9]+]], 0x40a00000 261; GCN-DAG: v_mov_b32_e32 [[T3:v[0-9]+]], 0x41100000 262; GCN-DAG: v_mov_b32_e32 [[T4:v[0-9]+]], 0x41500000 263; GCN-DAG: v_mov_b32_e32 [[F4:v[0-9]+]], 0x40c00000 264; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, 265; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 2.0, [[T2]], 266; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, 4.0, [[T3]], 267; GCN-DAG: v_cndmask_b32_e32 v{{[0-9]+}}, [[F4]], [[T4]], 268define amdgpu_kernel void @fsub_constant_sel_constants_v4f32(<4 x float> addrspace(1)* %p, i1 %cond) { 269 %sel = select i1 %cond, <4 x float> <float -2.0, float -3.0, float -4.0, float -5.0>, <4 x float> <float -1.0, float 0.0, float 1.0, float 2.0> 270 %bo = fsub <4 x float> <float -1.0, float 2.0, float 5.0, float 8.0>, %sel 271 store <4 x float> %bo, <4 x float> addrspace(1)* %p, align 32 272 ret void 273} 274 275; GCN-LABEL: {{^}}fdiv_constant_sel_constants: 276; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 4.0, -2.0, 277define amdgpu_kernel void @fdiv_constant_sel_constants(float addrspace(1)* %p, i1 %cond) { 278 %sel = select i1 %cond, float -4.0, float 2.0 279 %bo = fdiv float 8.0, %sel 280 store float %bo, float addrspace(1)* %p, align 4 281 ret void 282} 283 284; GCN-LABEL: {{^}}frem_constant_sel_constants: 285; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, 286define amdgpu_kernel void @frem_constant_sel_constants(float addrspace(1)* %p, i1 %cond) { 287 %sel = select i1 %cond, float -4.0, float 3.0 288 %bo = frem float 5.0, %sel 289 store float %bo, float addrspace(1)* %p, align 4 290 ret void 291} 292