1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 5declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone 6 7; GCN-LABEL: {{^}}load_i8_to_f32: 8; GCN: buffer_load_ubyte [[LOADREG:v[0-9]+]], 9; GCN-NOT: bfe 10; GCN-NOT: lshr 11; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]] 12; GCN: buffer_store_dword [[CONV]], 13define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind { 14 %load = load i8, i8 addrspace(1)* %in, align 1 15 %cvt = uitofp i8 %load to float 16 store float %cvt, float addrspace(1)* %out, align 4 17 ret void 18} 19 20; GCN-LABEL: {{^}}load_v2i8_to_v2f32: 21; GCN: buffer_load_ushort [[LD:v[0-9]+]] 22; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LD]] 23; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LD]] 24; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, 25define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind { 26 %load = load <2 x i8>, <2 x i8> addrspace(1)* %in, align 2 27 %cvt = uitofp <2 x i8> %load to <2 x float> 28 store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16 29 ret void 30} 31 32; GCN-LABEL: {{^}}load_v3i8_to_v3f32: 33; GCN: buffer_load_dword [[VAL:v[0-9]+]] 34; GCN-NOT: v_cvt_f32_ubyte3_e32 35; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[VAL]] 36; GCN-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[VAL]] 37; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[VAL]] 38; GCN: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, 39define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind { 40 %load = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4 41 %cvt = uitofp <3 x i8> %load to <3 x float> 42 store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16 43 ret void 44} 45 46; GCN-LABEL: {{^}}load_v4i8_to_v4f32: 47; GCN: buffer_load_dword [[LOADREG:v[0-9]+]] 48; GCN-NOT: bfe 49; GCN-NOT: lshr 50; GCN-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]] 51; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]] 52; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]] 53; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]] 54; GCN: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, 55define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { 56 %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 57 %cvt = uitofp <4 x i8> %load to <4 x float> 58 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16 59 ret void 60} 61 62; This should not be adding instructions to shift into the correct 63; position in the word for the component. 64 65; FIXME: Packing bytes 66; GCN-LABEL: {{^}}load_v4i8_to_v4f32_unaligned: 67; GCN: buffer_load_ubyte [[LOADREG3:v[0-9]+]] 68; GCN: buffer_load_ubyte [[LOADREG2:v[0-9]+]] 69; GCN: buffer_load_ubyte [[LOADREG1:v[0-9]+]] 70; GCN: buffer_load_ubyte [[LOADREG0:v[0-9]+]] 71; GCN-DAG: v_lshlrev_b32 72; GCN-DAG: v_or_b32 73; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], 74; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, 75; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, 76; GCN-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]] 77 78; GCN: buffer_store_dwordx4 79define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { 80 %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1 81 %cvt = uitofp <4 x i8> %load to <4 x float> 82 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16 83 ret void 84} 85 86; FIXME: Need to handle non-uniform case for function below (load without gep). 87; Instructions still emitted to repack bytes for add use. 88 89; GCN-LABEL: {{^}}load_v4i8_to_v4f32_2_uses: 90; GCN: {{buffer|flat}}_load_dword 91; GCN-DAG: v_cvt_f32_ubyte0_e32 92; GCN-DAG: v_cvt_f32_ubyte1_e32 93; GCN-DAG: v_cvt_f32_ubyte2_e32 94; GCN-DAG: v_cvt_f32_ubyte3_e32 95 96; GCN-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 24 97; GCN-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16 98 99; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16 100; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 8 101; SI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffff, 102; SI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xff00, 103; SI-DAG: v_add_i32 104 105; VI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffffff00, 106; VI-DAG: v_add_u16_e32 107; VI-DAG: v_add_u16_e32 108 109; GCN: {{buffer|flat}}_store_dwordx4 110; GCN: {{buffer|flat}}_store_dword 111 112; GCN: s_endpgm 113define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind { 114 %tid.x = call i32 @llvm.amdgcn.workitem.id.x() 115 %in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x 116 %load = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4 117 %cvt = uitofp <4 x i8> %load to <4 x float> 118 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16 119 %add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load 120 store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4 121 ret void 122} 123 124; Make sure this doesn't crash. 125; GCN-LABEL: {{^}}load_v7i8_to_v7f32: 126; GCN: s_endpgm 127define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind { 128 %load = load <7 x i8>, <7 x i8> addrspace(1)* %in, align 1 129 %cvt = uitofp <7 x i8> %load to <7 x float> 130 store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16 131 ret void 132} 133 134; GCN-LABEL: {{^}}load_v8i8_to_v8f32: 135; GCN: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}}, 136; GCN-NOT: bfe 137; GCN-NOT: lshr 138; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]] 139; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]] 140; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]] 141; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]] 142; GCN-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]] 143; GCN-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]] 144; GCN-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]] 145; GCN-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]] 146; GCN-NOT: bfe 147; GCN-NOT: lshr 148; GCN: buffer_store_dwordx4 149; GCN: buffer_store_dwordx4 150define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind { 151 %load = load <8 x i8>, <8 x i8> addrspace(1)* %in, align 8 152 %cvt = uitofp <8 x i8> %load to <8 x float> 153 store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16 154 ret void 155} 156 157; GCN-LABEL: {{^}}i8_zext_inreg_i32_to_f32: 158; GCN: buffer_load_dword [[LOADREG:v[0-9]+]], 159; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 2, [[LOADREG]] 160; GCN-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]] 161; GCN: buffer_store_dword [[CONV]], 162define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { 163 %load = load i32, i32 addrspace(1)* %in, align 4 164 %add = add i32 %load, 2 165 %inreg = and i32 %add, 255 166 %cvt = uitofp i32 %inreg to float 167 store float %cvt, float addrspace(1)* %out, align 4 168 ret void 169} 170 171; GCN-LABEL: {{^}}i8_zext_inreg_hi1_to_f32: 172define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { 173 %load = load i32, i32 addrspace(1)* %in, align 4 174 %inreg = and i32 %load, 65280 175 %shr = lshr i32 %inreg, 8 176 %cvt = uitofp i32 %shr to float 177 store float %cvt, float addrspace(1)* %out, align 4 178 ret void 179} 180 181; We don't get these ones because of the zext, but instcombine removes 182; them so it shouldn't really matter. 183; GCN-LABEL: {{^}}i8_zext_i32_to_f32: 184define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind { 185 %load = load i8, i8 addrspace(1)* %in, align 1 186 %ext = zext i8 %load to i32 187 %cvt = uitofp i32 %ext to float 188 store float %cvt, float addrspace(1)* %out, align 4 189 ret void 190} 191 192; GCN-LABEL: {{^}}v4i8_zext_v4i32_to_v4f32: 193define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { 194 %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1 195 %ext = zext <4 x i8> %load to <4 x i32> 196 %cvt = uitofp <4 x i32> %ext to <4 x float> 197 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16 198 ret void 199} 200 201; GCN-LABEL: {{^}}extract_byte0_to_f32: 202; GCN: buffer_load_dword [[VAL:v[0-9]+]] 203; GCN-NOT: [[VAL]] 204; GCN: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]] 205; GCN: buffer_store_dword [[CONV]] 206define void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { 207 %val = load i32, i32 addrspace(1)* %in 208 %and = and i32 %val, 255 209 %cvt = uitofp i32 %and to float 210 store float %cvt, float addrspace(1)* %out 211 ret void 212} 213 214; GCN-LABEL: {{^}}extract_byte1_to_f32: 215; GCN: buffer_load_dword [[VAL:v[0-9]+]] 216; GCN-NOT: [[VAL]] 217; GCN: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]] 218; GCN: buffer_store_dword [[CONV]] 219define void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { 220 %val = load i32, i32 addrspace(1)* %in 221 %srl = lshr i32 %val, 8 222 %and = and i32 %srl, 255 223 %cvt = uitofp i32 %and to float 224 store float %cvt, float addrspace(1)* %out 225 ret void 226} 227 228; GCN-LABEL: {{^}}extract_byte2_to_f32: 229; GCN: buffer_load_dword [[VAL:v[0-9]+]] 230; GCN-NOT: [[VAL]] 231; GCN: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] 232; GCN: buffer_store_dword [[CONV]] 233define void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { 234 %val = load i32, i32 addrspace(1)* %in 235 %srl = lshr i32 %val, 16 236 %and = and i32 %srl, 255 237 %cvt = uitofp i32 %and to float 238 store float %cvt, float addrspace(1)* %out 239 ret void 240} 241 242; GCN-LABEL: {{^}}extract_byte3_to_f32: 243; GCN: buffer_load_dword [[VAL:v[0-9]+]] 244; GCN-NOT: [[VAL]] 245; GCN: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]] 246; GCN: buffer_store_dword [[CONV]] 247define void @extract_byte3_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { 248 %val = load i32, i32 addrspace(1)* %in 249 %srl = lshr i32 %val, 24 250 %and = and i32 %srl, 255 251 %cvt = uitofp i32 %and to float 252 store float %cvt, float addrspace(1)* %out 253 ret void 254} 255