1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s 3; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 4 5declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone 6 7declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 8declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone 9declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone 10 11declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 12declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone 13declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone 14 15declare i32 @llvm.r600.read.tidig.x() nounwind readnone 16 17; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32: 18; GCN: s_load_dword [[VAL:s[0-9]+]], 19; GCN: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]] 20; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] 21; GCN: buffer_store_dword [[VRESULT]], 22; GCN: s_endpgm 23; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 24; EG: FFBH_UINT {{\*? *}}[[RESULT]] 25define amdgpu_kernel void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { 26 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 27 store i32 %ctlz, i32 addrspace(1)* %out, align 4 28 ret void 29} 30 31; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32: 32; GCN: buffer_load_dword [[VAL:v[0-9]+]], 33; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 34; GCN: buffer_store_dword [[RESULT]], 35; GCN: s_endpgm 36; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 37; EG: FFBH_UINT {{\*? *}}[[RESULT]] 38define amdgpu_kernel void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 39 %val = load i32, i32 addrspace(1)* %valptr, align 4 40 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 41 store i32 %ctlz, i32 addrspace(1)* %out, align 4 42 ret void 43} 44 45; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32: 46; GCN: buffer_load_dwordx2 47; GCN: v_ffbh_u32_e32 48; GCN: v_ffbh_u32_e32 49; GCN: buffer_store_dwordx2 50; GCN: s_endpgm 51; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 52; EG: FFBH_UINT {{\*? *}}[[RESULT]] 53; EG: FFBH_UINT {{\*? *}}[[RESULT]] 54define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind { 55 %val = load <2 x i32>, <2 x i32> addrspace(1)* %valptr, align 8 56 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone 57 store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8 58 ret void 59} 60 61; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32: 62; GCN: buffer_load_dwordx4 63; GCN: v_ffbh_u32_e32 64; GCN: v_ffbh_u32_e32 65; GCN: v_ffbh_u32_e32 66; GCN: v_ffbh_u32_e32 67; GCN: buffer_store_dwordx4 68; GCN: s_endpgm 69; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 70; EG: FFBH_UINT {{\*? *}}[[RESULT]] 71; EG: FFBH_UINT {{\*? *}}[[RESULT]] 72; EG: FFBH_UINT {{\*? *}}[[RESULT]] 73; EG: FFBH_UINT {{\*? *}}[[RESULT]] 74define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind { 75 %val = load <4 x i32>, <4 x i32> addrspace(1)* %valptr, align 16 76 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone 77 store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16 78 ret void 79} 80 81; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8: 82; GCN: buffer_load_ubyte [[VAL:v[0-9]+]], 83; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 84; GCN: buffer_store_byte [[RESULT]], 85define amdgpu_kernel void @v_ctlz_zero_undef_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 86 %val = load i8, i8 addrspace(1)* %valptr 87 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone 88 store i8 %ctlz, i8 addrspace(1)* %out 89 ret void 90} 91 92; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64: 93; GCN: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} 94; GCN-DAG: v_cmp_eq_u32_e64 vcc, s[[HI]], 0{{$}} 95; GCN-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]] 96; GCN-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32 97; GCN-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]] 98; GCN-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[FFBH_LO]] 99; GCN-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]] 100; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]] 101; GCN-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}} 102; GCN: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}} 103define amdgpu_kernel void @s_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 %val) nounwind { 104 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 105 store i64 %ctlz, i64 addrspace(1)* %out 106 ret void 107} 108 109; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64_trunc: 110define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind { 111 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 112 %trunc = trunc i64 %ctlz to i32 113 store i32 %trunc, i32 addrspace(1)* %out 114 ret void 115} 116 117; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64: 118; GCN-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} 119; GCN-DAG: v_cmp_eq_u32_e64 [[CMPHI:s\[[0-9]+:[0-9]+\]]], 0, v[[HI]] 120; GCN-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]] 121; GCN-DAG: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]] 122; GCN-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]] 123; GCN-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]] 124; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI:[0-9]+]]{{\]}} 125define amdgpu_kernel void @v_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 126 %tid = call i32 @llvm.r600.read.tidig.x() 127 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 128 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 129 %val = load i64, i64 addrspace(1)* %in.gep 130 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 131 store i64 %ctlz, i64 addrspace(1)* %out.gep 132 ret void 133} 134 135; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64_trunc: 136define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 137 %tid = call i32 @llvm.r600.read.tidig.x() 138 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 139 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 140 %val = load i64, i64 addrspace(1)* %in.gep 141 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 142 %trunc = trunc i64 %ctlz to i32 143 store i32 %trunc, i32 addrspace(1)* %out.gep 144 ret void 145} 146 147; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1: 148; GCN: buffer_load_dword [[VAL:v[0-9]+]], 149; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 150; GCN: buffer_store_dword [[RESULT]], 151 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 152 %val = load i32, i32 addrspace(1)* %valptr 153 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 154 %cmp = icmp eq i32 %val, 0 155 %sel = select i1 %cmp, i32 -1, i32 %ctlz 156 store i32 %sel, i32 addrspace(1)* %out 157 ret void 158} 159 160; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_neg1: 161; GCN: buffer_load_dword [[VAL:v[0-9]+]], 162; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 163; GCN: buffer_store_dword [[RESULT]], 164define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 165 %val = load i32, i32 addrspace(1)* %valptr 166 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 167 %cmp = icmp ne i32 %val, 0 168 %sel = select i1 %cmp, i32 %ctlz, i32 -1 169 store i32 %sel, i32 addrspace(1)* %out 170 ret void 171} 172 173; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8_sel_eq_neg1: 174; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]], 175; GCN: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]] 176; GCN: {{buffer|flat}}_store_byte [[FFBH]], 177define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 178 %tid = call i32 @llvm.r600.read.tidig.x() 179 %valptr.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid 180 %val = load i8, i8 addrspace(1)* %valptr.gep 181 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone 182 %cmp = icmp eq i8 %val, 0 183 %sel = select i1 %cmp, i8 -1, i8 %ctlz 184 store i8 %sel, i8 addrspace(1)* %out 185 ret void 186} 187 188; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1_two_use: 189; GCN: buffer_load_dword [[VAL:v[0-9]+]], 190; GCN-DAG: v_ffbh_u32_e32 [[RESULT0:v[0-9]+]], [[VAL]] 191; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, [[VAL]] 192; GCN-DAG: v_cndmask_b32_e64 [[RESULT1:v[0-9]+]], 0, 1, vcc 193; GCN-DAG: buffer_store_dword [[RESULT0]] 194; GCN-DAG: buffer_store_byte [[RESULT1]] 195; GCN: s_endpgm 196 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 197 %val = load i32, i32 addrspace(1)* %valptr 198 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 199 %cmp = icmp eq i32 %val, 0 200 %sel = select i1 %cmp, i32 -1, i32 %ctlz 201 store volatile i32 %sel, i32 addrspace(1)* %out 202 store volatile i1 %cmp, i1 addrspace(1)* undef 203 ret void 204} 205 206; Selected on wrong constant 207; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_0: 208; GCN: buffer_load_dword 209; GCN: v_ffbh_u32_e32 210; GCN: v_cmp 211; GCN: v_cndmask 212; GCN: buffer_store_dword 213 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 214 %val = load i32, i32 addrspace(1)* %valptr 215 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 216 %cmp = icmp eq i32 %val, 0 217 %sel = select i1 %cmp, i32 0, i32 %ctlz 218 store i32 %sel, i32 addrspace(1)* %out 219 ret void 220} 221 222; Selected on wrong constant 223; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_0: 224; GCN: buffer_load_dword 225; GCN: v_ffbh_u32_e32 226; GCN: v_cmp 227; GCN: v_cndmask 228; GCN: buffer_store_dword 229define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 230 %val = load i32, i32 addrspace(1)* %valptr 231 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 232 %cmp = icmp ne i32 %val, 0 233 %sel = select i1 %cmp, i32 %ctlz, i32 0 234 store i32 %sel, i32 addrspace(1)* %out 235 ret void 236} 237 238; Compare on wrong constant 239; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_cmp_non0: 240; GCN: buffer_load_dword 241; GCN: v_ffbh_u32_e32 242; GCN: v_cmp 243; GCN: v_cndmask 244; GCN: buffer_store_dword 245 define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 246 %val = load i32, i32 addrspace(1)* %valptr 247 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 248 %cmp = icmp eq i32 %val, 1 249 %sel = select i1 %cmp, i32 0, i32 %ctlz 250 store i32 %sel, i32 addrspace(1)* %out 251 ret void 252} 253 254; Selected on wrong constant 255; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_cmp_non0: 256; GCN: buffer_load_dword 257; GCN: v_ffbh_u32_e32 258; GCN: v_cmp 259; GCN: v_cndmask 260; GCN: buffer_store_dword 261define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 262 %val = load i32, i32 addrspace(1)* %valptr 263 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 264 %cmp = icmp ne i32 %val, 1 265 %sel = select i1 %cmp, i32 %ctlz, i32 0 266 store i32 %sel, i32 addrspace(1)* %out 267 ret void 268} 269