1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s 3; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 4 5declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone 6 7declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 8declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone 9declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone 10 11declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 12declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone 13declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone 14 15declare i32 @llvm.r600.read.tidig.x() nounwind readnone 16 17; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32: 18; GCN: s_load_dword [[VAL:s[0-9]+]], 19; GCN: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]] 20; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] 21; GCN: buffer_store_dword [[VRESULT]], 22; GCN: s_endpgm 23; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 24; EG: FFBH_UINT {{\*? *}}[[RESULT]] 25define amdgpu_kernel void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { 26 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 27 store i32 %ctlz, i32 addrspace(1)* %out, align 4 28 ret void 29} 30 31; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32: 32; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 33; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 34; GCN: buffer_store_dword [[RESULT]], 35; GCN: s_endpgm 36; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 37; EG: FFBH_UINT {{\*? *}}[[RESULT]] 38define amdgpu_kernel void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 39 %tid = call i32 @llvm.r600.read.tidig.x() 40 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 41 %val = load i32, i32 addrspace(1)* %in.gep, align 4 42 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 43 store i32 %ctlz, i32 addrspace(1)* %out, align 4 44 ret void 45} 46 47; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32: 48; GCN: {{buffer|flat}}_load_dwordx2 49; GCN: v_ffbh_u32_e32 50; GCN: v_ffbh_u32_e32 51; GCN: buffer_store_dwordx2 52; GCN: s_endpgm 53; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 54; EG: FFBH_UINT {{\*? *}}[[RESULT]] 55; EG: FFBH_UINT {{\*? *}}[[RESULT]] 56define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind { 57 %tid = call i32 @llvm.r600.read.tidig.x() 58 %in.gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid 59 %val = load <2 x i32>, <2 x i32> addrspace(1)* %in.gep, align 8 60 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone 61 store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8 62 ret void 63} 64 65; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32: 66; GCN: {{buffer|flat}}_load_dwordx4 67; GCN: v_ffbh_u32_e32 68; GCN: v_ffbh_u32_e32 69; GCN: v_ffbh_u32_e32 70; GCN: v_ffbh_u32_e32 71; GCN: buffer_store_dwordx4 72; GCN: s_endpgm 73; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 74; EG: FFBH_UINT {{\*? *}}[[RESULT]] 75; EG: FFBH_UINT {{\*? *}}[[RESULT]] 76; EG: FFBH_UINT {{\*? *}}[[RESULT]] 77; EG: FFBH_UINT {{\*? *}}[[RESULT]] 78define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind { 79 %tid = call i32 @llvm.r600.read.tidig.x() 80 %in.gep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %valptr, i32 %tid 81 %val = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep, align 16 82 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone 83 store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16 84 ret void 85} 86 87; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8: 88; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]], 89; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 90; GCN: buffer_store_byte [[RESULT]], 91define amdgpu_kernel void @v_ctlz_zero_undef_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 92 %tid = call i32 @llvm.r600.read.tidig.x() 93 %in.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid 94 %val = load i8, i8 addrspace(1)* %in.gep 95 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone 96 store i8 %ctlz, i8 addrspace(1)* %out 97 ret void 98} 99 100; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64: 101; GCN: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} 102; GCN-DAG: v_cmp_eq_u32_e64 vcc, s[[HI]], 0{{$}} 103; GCN-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]] 104; GCN-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32 105; GCN-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]] 106; GCN-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[FFBH_LO]] 107; GCN-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]] 108; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]] 109; GCN-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}} 110; GCN: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}} 111define amdgpu_kernel void @s_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 %val) nounwind { 112 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 113 store i64 %ctlz, i64 addrspace(1)* %out 114 ret void 115} 116 117; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64_trunc: 118define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind { 119 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 120 %trunc = trunc i64 %ctlz to i32 121 store i32 %trunc, i32 addrspace(1)* %out 122 ret void 123} 124 125; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64: 126; GCN-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} 127; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, v[[HI]] 128; GCN-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]] 129; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]] 130; GCN-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]] 131; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]] 132; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI:[0-9]+]]{{\]}} 133define amdgpu_kernel void @v_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 134 %tid = call i32 @llvm.r600.read.tidig.x() 135 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 136 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 137 %val = load i64, i64 addrspace(1)* %in.gep 138 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 139 store i64 %ctlz, i64 addrspace(1)* %out.gep 140 ret void 141} 142 143; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64_trunc: 144define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 145 %tid = call i32 @llvm.r600.read.tidig.x() 146 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 147 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 148 %val = load i64, i64 addrspace(1)* %in.gep 149 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 150 %trunc = trunc i64 %ctlz to i32 151 store i32 %trunc, i32 addrspace(1)* %out.gep 152 ret void 153} 154 155; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1: 156; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 157; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 158; GCN: buffer_store_dword [[RESULT]], 159define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 160 %tid = call i32 @llvm.r600.read.tidig.x() 161 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 162 %val = load i32, i32 addrspace(1)* %in.gep 163 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 164 %cmp = icmp eq i32 %val, 0 165 %sel = select i1 %cmp, i32 -1, i32 %ctlz 166 store i32 %sel, i32 addrspace(1)* %out 167 ret void 168} 169 170; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_neg1: 171; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 172; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 173; GCN: buffer_store_dword [[RESULT]], 174define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 175 %tid = call i32 @llvm.r600.read.tidig.x() 176 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 177 %val = load i32, i32 addrspace(1)* %in.gep 178 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 179 %cmp = icmp ne i32 %val, 0 180 %sel = select i1 %cmp, i32 %ctlz, i32 -1 181 store i32 %sel, i32 addrspace(1)* %out 182 ret void 183} 184 185; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8_sel_eq_neg1: 186; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]], 187; GCN: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]] 188; GCN: {{buffer|flat}}_store_byte [[FFBH]], 189define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 190 %tid = call i32 @llvm.r600.read.tidig.x() 191 %valptr.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid 192 %val = load i8, i8 addrspace(1)* %valptr.gep 193 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone 194 %cmp = icmp eq i8 %val, 0 195 %sel = select i1 %cmp, i8 -1, i8 %ctlz 196 store i8 %sel, i8 addrspace(1)* %out 197 ret void 198} 199 200; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1_two_use: 201; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 202; GCN-DAG: v_ffbh_u32_e32 [[RESULT0:v[0-9]+]], [[VAL]] 203; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, [[VAL]] 204; GCN-DAG: v_cndmask_b32_e64 [[RESULT1:v[0-9]+]], 0, 1, vcc 205; GCN-DAG: buffer_store_dword [[RESULT0]] 206; GCN-DAG: buffer_store_byte [[RESULT1]] 207; GCN: s_endpgm 208define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 209 %tid = call i32 @llvm.r600.read.tidig.x() 210 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 211 %val = load i32, i32 addrspace(1)* %in.gep 212 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 213 %cmp = icmp eq i32 %val, 0 214 %sel = select i1 %cmp, i32 -1, i32 %ctlz 215 store volatile i32 %sel, i32 addrspace(1)* %out 216 store volatile i1 %cmp, i1 addrspace(1)* undef 217 ret void 218} 219 220; Selected on wrong constant 221; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_0: 222; GCN: {{buffer|flat}}_load_dword 223; GCN: v_ffbh_u32_e32 224; GCN: v_cmp 225; GCN: v_cndmask 226; GCN: buffer_store_dword 227define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 228 %tid = call i32 @llvm.r600.read.tidig.x() 229 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 230 %val = load i32, i32 addrspace(1)* %in.gep 231 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 232 %cmp = icmp eq i32 %val, 0 233 %sel = select i1 %cmp, i32 0, i32 %ctlz 234 store i32 %sel, i32 addrspace(1)* %out 235 ret void 236} 237 238; Selected on wrong constant 239; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_0: 240; GCN: {{buffer|flat}}_load_dword 241; GCN: v_ffbh_u32_e32 242; GCN: v_cmp 243; GCN: v_cndmask 244; GCN: buffer_store_dword 245define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 246 %tid = call i32 @llvm.r600.read.tidig.x() 247 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 248 %val = load i32, i32 addrspace(1)* %in.gep 249 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 250 %cmp = icmp ne i32 %val, 0 251 %sel = select i1 %cmp, i32 %ctlz, i32 0 252 store i32 %sel, i32 addrspace(1)* %out 253 ret void 254} 255 256; Compare on wrong constant 257; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_cmp_non0: 258; GCN: {{buffer|flat}}_load_dword 259; GCN: v_ffbh_u32_e32 260; GCN: v_cmp 261; GCN: v_cndmask 262; GCN: buffer_store_dword 263define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 264 %tid = call i32 @llvm.r600.read.tidig.x() 265 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 266 %val = load i32, i32 addrspace(1)* %in.gep 267 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 268 %cmp = icmp eq i32 %val, 1 269 %sel = select i1 %cmp, i32 0, i32 %ctlz 270 store i32 %sel, i32 addrspace(1)* %out 271 ret void 272} 273 274; Selected on wrong constant 275; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_cmp_non0: 276; GCN: {{buffer|flat}}_load_dword 277; GCN: v_ffbh_u32_e32 278; GCN: v_cmp 279; GCN: v_cndmask 280; GCN: buffer_store_dword 281define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 282 %tid = call i32 @llvm.r600.read.tidig.x() 283 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 284 %val = load i32, i32 addrspace(1)* %in.gep 285 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 286 %cmp = icmp ne i32 %val, 1 287 %sel = select i1 %cmp, i32 %ctlz, i32 0 288 store i32 %sel, i32 addrspace(1)* %out 289 ret void 290} 291