1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s 3; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 4 5declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone 6 7declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 8declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone 9declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone 10 11declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 12declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone 13declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone 14 15declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 16 17; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i32: 18; GCN: s_load_dword [[VAL:s[0-9]+]], 19; GCN: s_flbit_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]] 20; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] 21; GCN: buffer_store_dword [[VRESULT]], 22; GCN: s_endpgm 23; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 24; EG: FFBH_UINT {{\*? *}}[[RESULT]] 25define amdgpu_kernel void @s_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { 26 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 27 store i32 %ctlz, i32 addrspace(1)* %out, align 4 28 ret void 29} 30 31; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32: 32; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 33; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 34; GCN: buffer_store_dword [[RESULT]], 35; GCN: s_endpgm 36; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] 37; EG: FFBH_UINT {{\*? *}}[[RESULT]] 38define amdgpu_kernel void @v_ctlz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 39 %tid = call i32 @llvm.amdgcn.workitem.id.x() 40 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 41 %val = load i32, i32 addrspace(1)* %in.gep, align 4 42 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 43 store i32 %ctlz, i32 addrspace(1)* %out, align 4 44 ret void 45} 46 47; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v2i32: 48; GCN: {{buffer|flat}}_load_dwordx2 49; GCN: v_ffbh_u32_e32 50; GCN: v_ffbh_u32_e32 51; GCN: buffer_store_dwordx2 52; GCN: s_endpgm 53; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 54; EG: FFBH_UINT {{\*? *}}[[RESULT]] 55; EG: FFBH_UINT {{\*? *}}[[RESULT]] 56define amdgpu_kernel void @v_ctlz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind { 57 %tid = call i32 @llvm.amdgcn.workitem.id.x() 58 %in.gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid 59 %val = load <2 x i32>, <2 x i32> addrspace(1)* %in.gep, align 8 60 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 true) nounwind readnone 61 store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8 62 ret void 63} 64 65; FUNC-LABEL: {{^}}v_ctlz_zero_undef_v4i32: 66; GCN: {{buffer|flat}}_load_dwordx4 67; GCN: v_ffbh_u32_e32 68; GCN: v_ffbh_u32_e32 69; GCN: v_ffbh_u32_e32 70; GCN: v_ffbh_u32_e32 71; GCN: buffer_store_dwordx4 72; GCN: s_endpgm 73; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} 74; EG: FFBH_UINT {{\*? *}}[[RESULT]] 75; EG: FFBH_UINT {{\*? *}}[[RESULT]] 76; EG: FFBH_UINT {{\*? *}}[[RESULT]] 77; EG: FFBH_UINT {{\*? *}}[[RESULT]] 78define amdgpu_kernel void @v_ctlz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind { 79 %tid = call i32 @llvm.amdgcn.workitem.id.x() 80 %in.gep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %valptr, i32 %tid 81 %val = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep, align 16 82 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 true) nounwind readnone 83 store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16 84 ret void 85} 86 87; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8: 88; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]], 89; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 90; GCN: buffer_store_byte [[RESULT]], 91define amdgpu_kernel void @v_ctlz_zero_undef_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 92 %tid = call i32 @llvm.amdgcn.workitem.id.x() 93 %in.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid 94 %val = load i8, i8 addrspace(1)* %in.gep 95 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone 96 store i8 %ctlz, i8 addrspace(1)* %out 97 ret void 98} 99 100; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64: 101; GCN: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}} 102; GCN-DAG: s_cmp_eq_u32 s[[HI]], 0{{$}} 103; GCN-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]] 104; GCN-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32 105; GCN-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]] 106; GCN-DAG: s_cselect_b32 [[RES:s[0-9]+]], [[ADD]], [[FFBH_HI]] 107; GCN-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}} 108; GCN-DAG: v_mov_b32_e32 v[[CTLZ:[0-9]+]], [[RES]] 109; GCN: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}} 110define amdgpu_kernel void @s_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind { 111 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 112 store i64 %ctlz, i64 addrspace(1)* %out 113 ret void 114} 115 116; FUNC-LABEL: {{^}}s_ctlz_zero_undef_i64_trunc: 117define amdgpu_kernel void @s_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind { 118 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 119 %trunc = trunc i64 %ctlz to i32 120 store i32 %trunc, i32 addrspace(1)* %out 121 ret void 122} 123 124; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64: 125; GCN-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} 126; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, v[[HI]] 127; GCN-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]] 128; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]] 129; GCN-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]] 130; GCN-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]] 131; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI:[0-9]+]]{{\]}} 132define amdgpu_kernel void @v_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 133 %tid = call i32 @llvm.amdgcn.workitem.id.x() 134 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 135 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 136 %val = load i64, i64 addrspace(1)* %in.gep 137 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 138 store i64 %ctlz, i64 addrspace(1)* %out.gep 139 ret void 140} 141 142; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64_trunc: 143define amdgpu_kernel void @v_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 144 %tid = call i32 @llvm.amdgcn.workitem.id.x() 145 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 146 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 147 %val = load i64, i64 addrspace(1)* %in.gep 148 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 true) 149 %trunc = trunc i64 %ctlz to i32 150 store i32 %trunc, i32 addrspace(1)* %out.gep 151 ret void 152} 153 154; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1: 155; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 156; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 157; GCN: buffer_store_dword [[RESULT]], 158define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 159 %tid = call i32 @llvm.amdgcn.workitem.id.x() 160 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 161 %val = load i32, i32 addrspace(1)* %in.gep 162 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 163 %cmp = icmp eq i32 %val, 0 164 %sel = select i1 %cmp, i32 -1, i32 %ctlz 165 store i32 %sel, i32 addrspace(1)* %out 166 ret void 167} 168 169; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_neg1: 170; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 171; GCN: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] 172; GCN: buffer_store_dword [[RESULT]], 173define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 174 %tid = call i32 @llvm.amdgcn.workitem.id.x() 175 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 176 %val = load i32, i32 addrspace(1)* %in.gep 177 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 178 %cmp = icmp ne i32 %val, 0 179 %sel = select i1 %cmp, i32 %ctlz, i32 -1 180 store i32 %sel, i32 addrspace(1)* %out 181 ret void 182} 183 184; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i8_sel_eq_neg1: 185; GCN: {{buffer|flat}}_load_ubyte [[VAL:v[0-9]+]], 186; GCN: v_ffbh_u32_e32 [[FFBH:v[0-9]+]], [[VAL]] 187; GCN: {{buffer|flat}}_store_byte [[FFBH]], 188define amdgpu_kernel void @v_ctlz_zero_undef_i8_sel_eq_neg1(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 189 %tid = call i32 @llvm.amdgcn.workitem.id.x() 190 %valptr.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid 191 %val = load i8, i8 addrspace(1)* %valptr.gep 192 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 true) nounwind readnone 193 %cmp = icmp eq i8 %val, 0 194 %sel = select i1 %cmp, i8 -1, i8 %ctlz 195 store i8 %sel, i8 addrspace(1)* %out 196 ret void 197} 198 199; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1_two_use: 200; GCN: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]], 201; GCN-DAG: v_ffbh_u32_e32 [[RESULT0:v[0-9]+]], [[VAL]] 202; GCN-DAG: v_cmp_eq_u32_e32 vcc, 0, [[VAL]] 203; GCN-DAG: v_cndmask_b32_e64 [[RESULT1:v[0-9]+]], 0, 1, vcc 204; GCN-DAG: buffer_store_dword [[RESULT0]] 205; GCN-DAG: buffer_store_byte [[RESULT1]] 206; GCN: s_endpgm 207define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_neg1_two_use(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 208 %tid = call i32 @llvm.amdgcn.workitem.id.x() 209 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 210 %val = load i32, i32 addrspace(1)* %in.gep 211 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 212 %cmp = icmp eq i32 %val, 0 213 %sel = select i1 %cmp, i32 -1, i32 %ctlz 214 store volatile i32 %sel, i32 addrspace(1)* %out 215 store volatile i1 %cmp, i1 addrspace(1)* undef 216 ret void 217} 218 219; Selected on wrong constant 220; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_0: 221; GCN: {{buffer|flat}}_load_dword 222; GCN: v_ffbh_u32_e32 223; GCN: v_cmp 224; GCN: v_cndmask 225; GCN: buffer_store_dword 226define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 227 %tid = call i32 @llvm.amdgcn.workitem.id.x() 228 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 229 %val = load i32, i32 addrspace(1)* %in.gep 230 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 231 %cmp = icmp eq i32 %val, 0 232 %sel = select i1 %cmp, i32 0, i32 %ctlz 233 store i32 %sel, i32 addrspace(1)* %out 234 ret void 235} 236 237; Selected on wrong constant 238; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_0: 239; GCN: {{buffer|flat}}_load_dword 240; GCN: v_ffbh_u32_e32 241; GCN: v_cmp 242; GCN: v_cndmask 243; GCN: buffer_store_dword 244define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 245 %tid = call i32 @llvm.amdgcn.workitem.id.x() 246 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 247 %val = load i32, i32 addrspace(1)* %in.gep 248 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 249 %cmp = icmp ne i32 %val, 0 250 %sel = select i1 %cmp, i32 %ctlz, i32 0 251 store i32 %sel, i32 addrspace(1)* %out 252 ret void 253} 254 255; Compare on wrong constant 256; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_cmp_non0: 257; GCN: {{buffer|flat}}_load_dword 258; GCN: v_ffbh_u32_e32 259; GCN: v_cmp 260; GCN: v_cndmask 261; GCN: buffer_store_dword 262define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_eq_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 263 %tid = call i32 @llvm.amdgcn.workitem.id.x() 264 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 265 %val = load i32, i32 addrspace(1)* %in.gep 266 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 267 %cmp = icmp eq i32 %val, 1 268 %sel = select i1 %cmp, i32 0, i32 %ctlz 269 store i32 %sel, i32 addrspace(1)* %out 270 ret void 271} 272 273; Selected on wrong constant 274; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_cmp_non0: 275; GCN: {{buffer|flat}}_load_dword 276; GCN: v_ffbh_u32_e32 277; GCN: v_cmp 278; GCN: v_cndmask 279; GCN: buffer_store_dword 280define amdgpu_kernel void @v_ctlz_zero_undef_i32_sel_ne_cmp_non0(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 281 %tid = call i32 @llvm.amdgcn.workitem.id.x() 282 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 283 %val = load i32, i32 addrspace(1)* %in.gep 284 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone 285 %cmp = icmp ne i32 %val, 1 286 %sel = select i1 %cmp, i32 %ctlz, i32 0 287 store i32 %sel, i32 addrspace(1)* %out 288 ret void 289} 290