1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=FUNC,GCN,SI 3; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=FUNC,GCN,VI 4; RUN: llc < %s -march=r600 -mcpu=cypress -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=FUNC,EG 5 6declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone 7declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone 8declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone 9 10declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 11declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone 12declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone 13 14declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 15declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone 16declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone 17 18declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 19 20define amdgpu_kernel void @s_ctlz_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { 21; SI-LABEL: s_ctlz_i32: 22; SI: ; %bb.0: 23; SI-NEXT: s_load_dword s2, s[0:1], 0xb 24; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 25; SI-NEXT: s_mov_b32 s7, 0xf000 26; SI-NEXT: s_waitcnt lgkmcnt(0) 27; SI-NEXT: s_flbit_i32_b32 s0, s2 28; SI-NEXT: s_mov_b32 s6, -1 29; SI-NEXT: v_mov_b32_e32 v0, s0 30; SI-NEXT: v_cmp_ne_u32_e64 vcc, s2, 0 31; SI-NEXT: v_cndmask_b32_e32 v0, 32, v0, vcc 32; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 33; SI-NEXT: s_endpgm 34; 35; VI-LABEL: s_ctlz_i32: 36; VI: ; %bb.0: 37; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 38; VI-NEXT: s_load_dword s0, s[0:1], 0x2c 39; VI-NEXT: s_mov_b32 s7, 0xf000 40; VI-NEXT: s_mov_b32 s6, -1 41; VI-NEXT: s_waitcnt lgkmcnt(0) 42; VI-NEXT: s_flbit_i32_b32 s1, s0 43; VI-NEXT: v_mov_b32_e32 v0, s1 44; VI-NEXT: v_cmp_ne_u32_e64 vcc, s0, 0 45; VI-NEXT: v_cndmask_b32_e32 v0, 32, v0, vcc 46; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 47; VI-NEXT: s_endpgm 48; 49; EG-LABEL: s_ctlz_i32: 50; EG: ; %bb.0: 51; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] 52; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 53; EG-NEXT: CF_END 54; EG-NEXT: PAD 55; EG-NEXT: ALU clause starting at 4: 56; EG-NEXT: FFBH_UINT * T0.W, KC0[2].Z, 57; EG-NEXT: CNDE_INT T0.X, KC0[2].Z, literal.x, PV.W, 58; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 59; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45) 60 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone 61 store i32 %ctlz, i32 addrspace(1)* %out, align 4 62 ret void 63} 64 65define amdgpu_kernel void @v_ctlz_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 66; SI-LABEL: v_ctlz_i32: 67; SI: ; %bb.0: 68; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 69; SI-NEXT: s_mov_b32 s3, 0xf000 70; SI-NEXT: s_mov_b32 s6, 0 71; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 72; SI-NEXT: v_mov_b32_e32 v1, 0 73; SI-NEXT: s_mov_b32 s7, s3 74; SI-NEXT: s_waitcnt lgkmcnt(0) 75; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 76; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 77; SI-NEXT: s_mov_b32 s2, -1 78; SI-NEXT: s_waitcnt vmcnt(0) 79; SI-NEXT: v_ffbh_u32_e32 v1, v0 80; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 81; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc 82; SI-NEXT: s_waitcnt lgkmcnt(0) 83; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 84; SI-NEXT: s_endpgm 85; 86; VI-LABEL: v_ctlz_i32: 87; VI: ; %bb.0: 88; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 89; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 90; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 91; VI-NEXT: s_mov_b32 s7, 0xf000 92; VI-NEXT: s_mov_b32 s6, -1 93; VI-NEXT: s_waitcnt lgkmcnt(0) 94; VI-NEXT: v_mov_b32_e32 v1, s1 95; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 96; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 97; VI-NEXT: flat_load_dword v0, v[0:1] 98; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 99; VI-NEXT: v_ffbh_u32_e32 v1, v0 100; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 101; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc 102; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 103; VI-NEXT: s_endpgm 104; 105; EG-LABEL: v_ctlz_i32: 106; EG: ; %bb.0: 107; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 108; EG-NEXT: TEX 0 @6 109; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[] 110; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 111; EG-NEXT: CF_END 112; EG-NEXT: PAD 113; EG-NEXT: Fetch clause starting at 6: 114; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 115; EG-NEXT: ALU clause starting at 8: 116; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 117; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 118; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 119; EG-NEXT: ALU clause starting at 11: 120; EG-NEXT: FFBH_UINT * T0.W, T0.X, 121; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, 122; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 123; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45) 124 %tid = call i32 @llvm.amdgcn.workitem.id.x() 125 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 126 %val = load i32, i32 addrspace(1)* %in.gep, align 4 127 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone 128 store i32 %ctlz, i32 addrspace(1)* %out, align 4 129 ret void 130} 131 132define amdgpu_kernel void @v_ctlz_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind { 133; SI-LABEL: v_ctlz_v2i32: 134; SI: ; %bb.0: 135; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 136; SI-NEXT: s_mov_b32 s3, 0xf000 137; SI-NEXT: s_mov_b32 s6, 0 138; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 139; SI-NEXT: v_mov_b32_e32 v1, 0 140; SI-NEXT: s_mov_b32 s7, s3 141; SI-NEXT: s_waitcnt lgkmcnt(0) 142; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 143; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 144; SI-NEXT: s_mov_b32 s2, -1 145; SI-NEXT: s_waitcnt vmcnt(0) 146; SI-NEXT: v_ffbh_u32_e32 v2, v1 147; SI-NEXT: v_ffbh_u32_e32 v3, v0 148; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 149; SI-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc 150; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 151; SI-NEXT: v_cndmask_b32_e32 v0, 32, v3, vcc 152; SI-NEXT: s_waitcnt lgkmcnt(0) 153; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 154; SI-NEXT: s_endpgm 155; 156; VI-LABEL: v_ctlz_v2i32: 157; VI: ; %bb.0: 158; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 159; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 160; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 161; VI-NEXT: s_mov_b32 s7, 0xf000 162; VI-NEXT: s_mov_b32 s6, -1 163; VI-NEXT: s_waitcnt lgkmcnt(0) 164; VI-NEXT: v_mov_b32_e32 v1, s1 165; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 166; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 167; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] 168; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 169; VI-NEXT: v_ffbh_u32_e32 v2, v1 170; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 171; VI-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc 172; VI-NEXT: v_ffbh_u32_e32 v3, v0 173; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 174; VI-NEXT: v_cndmask_b32_e32 v0, 32, v3, vcc 175; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 176; VI-NEXT: s_endpgm 177; 178; EG-LABEL: v_ctlz_v2i32: 179; EG: ; %bb.0: 180; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 181; EG-NEXT: TEX 0 @6 182; EG-NEXT: ALU 6, @11, KC0[CB0:0-32], KC1[] 183; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 184; EG-NEXT: CF_END 185; EG-NEXT: PAD 186; EG-NEXT: Fetch clause starting at 6: 187; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 188; EG-NEXT: ALU clause starting at 8: 189; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 190; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 191; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 192; EG-NEXT: ALU clause starting at 11: 193; EG-NEXT: FFBH_UINT * T0.W, T0.Y, 194; EG-NEXT: CNDE_INT T0.Y, T0.Y, literal.x, PV.W, 195; EG-NEXT: FFBH_UINT * T0.W, T0.X, 196; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 197; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, 198; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 199; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45) 200 %tid = call i32 @llvm.amdgcn.workitem.id.x() 201 %in.gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid 202 %val = load <2 x i32>, <2 x i32> addrspace(1)* %in.gep, align 8 203 %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 false) nounwind readnone 204 store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8 205 ret void 206} 207 208define amdgpu_kernel void @v_ctlz_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind { 209; SI-LABEL: v_ctlz_v4i32: 210; SI: ; %bb.0: 211; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 212; SI-NEXT: s_mov_b32 s3, 0xf000 213; SI-NEXT: s_mov_b32 s6, 0 214; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0 215; SI-NEXT: v_mov_b32_e32 v1, 0 216; SI-NEXT: s_mov_b32 s7, s3 217; SI-NEXT: s_waitcnt lgkmcnt(0) 218; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[4:7], 0 addr64 219; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 220; SI-NEXT: s_mov_b32 s2, -1 221; SI-NEXT: s_waitcnt vmcnt(0) 222; SI-NEXT: v_ffbh_u32_e32 v4, v3 223; SI-NEXT: v_ffbh_u32_e32 v5, v2 224; SI-NEXT: v_ffbh_u32_e32 v6, v1 225; SI-NEXT: v_ffbh_u32_e32 v7, v0 226; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 227; SI-NEXT: v_cndmask_b32_e32 v3, 32, v4, vcc 228; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 229; SI-NEXT: v_cndmask_b32_e32 v2, 32, v5, vcc 230; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 231; SI-NEXT: v_cndmask_b32_e32 v1, 32, v6, vcc 232; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 233; SI-NEXT: v_cndmask_b32_e32 v0, 32, v7, vcc 234; SI-NEXT: s_waitcnt lgkmcnt(0) 235; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 236; SI-NEXT: s_endpgm 237; 238; VI-LABEL: v_ctlz_v4i32: 239; VI: ; %bb.0: 240; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 241; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 242; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0 243; VI-NEXT: s_mov_b32 s7, 0xf000 244; VI-NEXT: s_mov_b32 s6, -1 245; VI-NEXT: s_waitcnt lgkmcnt(0) 246; VI-NEXT: v_mov_b32_e32 v1, s1 247; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 248; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 249; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] 250; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 251; VI-NEXT: v_ffbh_u32_e32 v4, v3 252; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 253; VI-NEXT: v_cndmask_b32_e32 v3, 32, v4, vcc 254; VI-NEXT: v_ffbh_u32_e32 v5, v2 255; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 256; VI-NEXT: v_cndmask_b32_e32 v2, 32, v5, vcc 257; VI-NEXT: v_ffbh_u32_e32 v6, v1 258; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 259; VI-NEXT: v_cndmask_b32_e32 v1, 32, v6, vcc 260; VI-NEXT: v_ffbh_u32_e32 v7, v0 261; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 262; VI-NEXT: v_cndmask_b32_e32 v0, 32, v7, vcc 263; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 264; VI-NEXT: s_endpgm 265; 266; EG-LABEL: v_ctlz_v4i32: 267; EG: ; %bb.0: 268; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 269; EG-NEXT: TEX 0 @6 270; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[] 271; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 272; EG-NEXT: CF_END 273; EG-NEXT: PAD 274; EG-NEXT: Fetch clause starting at 6: 275; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 276; EG-NEXT: ALU clause starting at 8: 277; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 278; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) 279; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 280; EG-NEXT: ALU clause starting at 11: 281; EG-NEXT: FFBH_UINT * T1.W, T0.W, 282; EG-NEXT: FFBH_UINT T2.W, T0.Z, 283; EG-NEXT: CNDE_INT * T0.W, T0.W, literal.x, PV.W, BS:VEC_021/SCL_122 284; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 285; EG-NEXT: CNDE_INT T0.Z, T0.Z, literal.x, PV.W, 286; EG-NEXT: FFBH_UINT * T1.W, T0.Y, 287; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 288; EG-NEXT: CNDE_INT T0.Y, T0.Y, literal.x, PV.W, 289; EG-NEXT: FFBH_UINT * T1.W, T0.X, 290; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 291; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, 292; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 293; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45) 294 %tid = call i32 @llvm.amdgcn.workitem.id.x() 295 %in.gep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %valptr, i32 %tid 296 %val = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep, align 16 297 %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 false) nounwind readnone 298 store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16 299 ret void 300} 301 302define amdgpu_kernel void @v_ctlz_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 303; SI-LABEL: v_ctlz_i8: 304; SI: ; %bb.0: 305; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 306; SI-NEXT: s_mov_b32 s3, 0xf000 307; SI-NEXT: s_mov_b32 s2, -1 308; SI-NEXT: s_mov_b32 s6, s2 309; SI-NEXT: s_mov_b32 s7, s3 310; SI-NEXT: s_waitcnt lgkmcnt(0) 311; SI-NEXT: buffer_load_ubyte v0, off, s[4:7], 0 312; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 313; SI-NEXT: s_waitcnt vmcnt(0) 314; SI-NEXT: v_ffbh_u32_e32 v1, v0 315; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 316; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc 317; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0 318; SI-NEXT: s_waitcnt lgkmcnt(0) 319; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 320; SI-NEXT: s_endpgm 321; 322; VI-LABEL: v_ctlz_i8: 323; VI: ; %bb.0: 324; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 325; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 326; VI-NEXT: s_mov_b32 s7, 0xf000 327; VI-NEXT: s_mov_b32 s6, -1 328; VI-NEXT: s_mov_b32 s2, s6 329; VI-NEXT: s_mov_b32 s3, s7 330; VI-NEXT: s_waitcnt lgkmcnt(0) 331; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 332; VI-NEXT: s_waitcnt vmcnt(0) 333; VI-NEXT: v_ffbh_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 334; VI-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0 335; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc 336; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 337; VI-NEXT: v_add_u16_e32 v0, -8, v0 338; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 339; VI-NEXT: s_endpgm 340; 341; EG-LABEL: v_ctlz_i8: 342; EG: ; %bb.0: 343; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 344; EG-NEXT: TEX 0 @6 345; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[] 346; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 347; EG-NEXT: CF_END 348; EG-NEXT: PAD 349; EG-NEXT: Fetch clause starting at 6: 350; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 351; EG-NEXT: ALU clause starting at 8: 352; EG-NEXT: MOV * T0.X, KC0[2].Z, 353; EG-NEXT: ALU clause starting at 9: 354; EG-NEXT: FFBH_UINT * T0.W, T0.X, 355; EG-NEXT: CNDE_INT T0.W, T0.X, literal.x, PV.W, 356; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y, 357; EG-NEXT: 32(4.484155e-44), 3(4.203895e-45) 358; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x, 359; EG-NEXT: -24(nan), 0(0.000000e+00) 360; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 361; EG-NEXT: LSHL * T1.W, T1.W, literal.y, 362; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45) 363; EG-NEXT: LSHL T0.X, PV.W, PS, 364; EG-NEXT: LSHL * T0.W, literal.x, PS, 365; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) 366; EG-NEXT: MOV T0.Y, 0.0, 367; EG-NEXT: MOV * T0.Z, 0.0, 368; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 369; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 370 %val = load i8, i8 addrspace(1)* %valptr 371 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone 372 store i8 %ctlz, i8 addrspace(1)* %out 373 ret void 374} 375 376define amdgpu_kernel void @s_ctlz_i64(i64 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind { 377; SI-LABEL: s_ctlz_i64: 378; SI: ; %bb.0: 379; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x13 380; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 381; SI-NEXT: s_mov_b32 s7, 0xf000 382; SI-NEXT: s_mov_b32 s6, -1 383; SI-NEXT: s_waitcnt lgkmcnt(0) 384; SI-NEXT: s_flbit_i32_b32 s0, s2 385; SI-NEXT: s_flbit_i32_b32 s1, s3 386; SI-NEXT: s_add_i32 s0, s0, 32 387; SI-NEXT: s_or_b32 s2, s2, s3 388; SI-NEXT: v_mov_b32_e32 v0, s1 389; SI-NEXT: v_mov_b32_e32 v1, s0 390; SI-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 391; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 392; SI-NEXT: v_cmp_ne_u32_e64 vcc, s2, 0 393; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc 394; SI-NEXT: v_mov_b32_e32 v1, 0 395; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 396; SI-NEXT: s_endpgm 397; 398; VI-LABEL: s_ctlz_i64: 399; VI: ; %bb.0: 400; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 401; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x4c 402; VI-NEXT: s_mov_b32 s7, 0xf000 403; VI-NEXT: s_mov_b32 s6, -1 404; VI-NEXT: s_waitcnt lgkmcnt(0) 405; VI-NEXT: s_flbit_i32_b32 s2, s0 406; VI-NEXT: s_flbit_i32_b32 s3, s1 407; VI-NEXT: s_add_i32 s2, s2, 32 408; VI-NEXT: v_mov_b32_e32 v0, s3 409; VI-NEXT: v_mov_b32_e32 v1, s2 410; VI-NEXT: v_cmp_eq_u32_e64 vcc, s1, 0 411; VI-NEXT: s_or_b32 s0, s0, s1 412; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 413; VI-NEXT: v_cmp_ne_u32_e64 vcc, s0, 0 414; VI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc 415; VI-NEXT: v_mov_b32_e32 v1, 0 416; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 417; VI-NEXT: s_endpgm 418; 419; EG-LABEL: s_ctlz_i64: 420; EG: ; %bb.0: 421; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] 422; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 423; EG-NEXT: CF_END 424; EG-NEXT: PAD 425; EG-NEXT: ALU clause starting at 4: 426; EG-NEXT: FFBH_UINT * T0.W, KC0[4].W, 427; EG-NEXT: CNDE_INT * T0.W, KC0[4].W, literal.x, PV.W, 428; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 429; EG-NEXT: FFBH_UINT T1.W, KC0[5].X, 430; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x, 431; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 432; EG-NEXT: CNDE_INT T0.X, KC0[5].X, PS, PV.W, 433; EG-NEXT: MOV T0.Y, 0.0, 434; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 435; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 436 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) 437 store i64 %ctlz, i64 addrspace(1)* %out 438 ret void 439} 440 441define amdgpu_kernel void @s_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind { 442; SI-LABEL: s_ctlz_i64_trunc: 443; SI: ; %bb.0: 444; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb 445; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 446; SI-NEXT: s_mov_b32 s7, 0xf000 447; SI-NEXT: s_mov_b32 s6, -1 448; SI-NEXT: s_waitcnt lgkmcnt(0) 449; SI-NEXT: s_flbit_i32_b32 s0, s2 450; SI-NEXT: s_flbit_i32_b32 s1, s3 451; SI-NEXT: s_add_i32 s0, s0, 32 452; SI-NEXT: s_or_b32 s2, s2, s3 453; SI-NEXT: v_mov_b32_e32 v0, s1 454; SI-NEXT: v_mov_b32_e32 v1, s0 455; SI-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 456; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 457; SI-NEXT: v_cmp_ne_u32_e64 vcc, s2, 0 458; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc 459; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 460; SI-NEXT: s_endpgm 461; 462; VI-LABEL: s_ctlz_i64_trunc: 463; VI: ; %bb.0: 464; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 465; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 466; VI-NEXT: s_mov_b32 s7, 0xf000 467; VI-NEXT: s_mov_b32 s6, -1 468; VI-NEXT: s_waitcnt lgkmcnt(0) 469; VI-NEXT: s_flbit_i32_b32 s2, s0 470; VI-NEXT: s_flbit_i32_b32 s3, s1 471; VI-NEXT: s_add_i32 s2, s2, 32 472; VI-NEXT: v_mov_b32_e32 v0, s3 473; VI-NEXT: v_mov_b32_e32 v1, s2 474; VI-NEXT: v_cmp_eq_u32_e64 vcc, s1, 0 475; VI-NEXT: s_or_b32 s0, s0, s1 476; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc 477; VI-NEXT: v_cmp_ne_u32_e64 vcc, s0, 0 478; VI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc 479; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 480; VI-NEXT: s_endpgm 481; 482; EG-LABEL: s_ctlz_i64_trunc: 483; EG: ; %bb.0: 484; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[] 485; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 486; EG-NEXT: CF_END 487; EG-NEXT: PAD 488; EG-NEXT: ALU clause starting at 4: 489; EG-NEXT: FFBH_UINT * T0.W, KC0[2].W, 490; EG-NEXT: CNDE_INT * T0.W, KC0[2].W, literal.x, PV.W, 491; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 492; EG-NEXT: FFBH_UINT T1.W, KC0[3].X, 493; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x, 494; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 495; EG-NEXT: CNDE_INT T0.X, KC0[3].X, PS, PV.W, 496; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 497; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 498 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) 499 %trunc = trunc i64 %ctlz to i32 500 store i32 %trunc, i32 addrspace(1)* %out 501 ret void 502} 503 504define amdgpu_kernel void @v_ctlz_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 505; SI-LABEL: v_ctlz_i64: 506; SI: ; %bb.0: 507; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 508; SI-NEXT: s_mov_b32 s7, 0xf000 509; SI-NEXT: s_mov_b32 s6, 0 510; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 511; SI-NEXT: v_mov_b32_e32 v1, 0 512; SI-NEXT: s_waitcnt lgkmcnt(0) 513; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 514; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 515; SI-NEXT: s_waitcnt vmcnt(0) 516; SI-NEXT: v_ffbh_u32_e32 v4, v2 517; SI-NEXT: v_ffbh_u32_e32 v5, v3 518; SI-NEXT: v_or_b32_e32 v2, v2, v3 519; SI-NEXT: v_add_i32_e32 v4, vcc, 32, v4 520; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 521; SI-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc 522; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 523; SI-NEXT: v_cndmask_b32_e32 v2, 64, v3, vcc 524; SI-NEXT: v_mov_b32_e32 v3, v1 525; SI-NEXT: s_waitcnt lgkmcnt(0) 526; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 527; SI-NEXT: s_endpgm 528; 529; VI-LABEL: v_ctlz_i64: 530; VI: ; %bb.0: 531; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 532; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 533; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 534; VI-NEXT: v_mov_b32_e32 v5, 0 535; VI-NEXT: v_mov_b32_e32 v1, 0 536; VI-NEXT: s_waitcnt lgkmcnt(0) 537; VI-NEXT: v_mov_b32_e32 v6, s3 538; VI-NEXT: v_mov_b32_e32 v3, s1 539; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v0 540; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc 541; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3] 542; VI-NEXT: v_add_u32_e32 v4, vcc, s2, v0 543; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc 544; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 545; VI-NEXT: v_ffbh_u32_e32 v0, v2 546; VI-NEXT: v_add_u32_e32 v0, vcc, 32, v0 547; VI-NEXT: v_ffbh_u32_e32 v6, v3 548; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 549; VI-NEXT: v_or_b32_e32 v2, v2, v3 550; VI-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc 551; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 552; VI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc 553; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] 554; VI-NEXT: s_endpgm 555; 556; EG-LABEL: v_ctlz_i64: 557; EG: ; %bb.0: 558; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 559; EG-NEXT: TEX 0 @6 560; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[] 561; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 562; EG-NEXT: CF_END 563; EG-NEXT: PAD 564; EG-NEXT: Fetch clause starting at 6: 565; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 566; EG-NEXT: ALU clause starting at 8: 567; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 568; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 569; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 570; EG-NEXT: ALU clause starting at 11: 571; EG-NEXT: FFBH_UINT * T1.W, T0.X, 572; EG-NEXT: CNDE_INT * T1.W, T0.X, literal.x, PV.W, 573; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 574; EG-NEXT: FFBH_UINT T2.W, T0.Y, 575; EG-NEXT: ADD_INT * T1.W, PV.W, literal.x, 576; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 577; EG-NEXT: CNDE_INT T0.X, T0.Y, PS, PV.W, 578; EG-NEXT: MOV T0.Y, 0.0, 579; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, 580; EG-NEXT: LSHR * T1.X, PV.W, literal.x, 581; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 582 %tid = call i32 @llvm.amdgcn.workitem.id.x() 583 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 584 %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 585 %val = load i64, i64 addrspace(1)* %in.gep 586 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) 587 store i64 %ctlz, i64 addrspace(1)* %out.gep 588 ret void 589} 590 591define amdgpu_kernel void @v_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { 592; SI-LABEL: v_ctlz_i64_trunc: 593; SI: ; %bb.0: 594; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 595; SI-NEXT: s_mov_b32 s7, 0xf000 596; SI-NEXT: s_mov_b32 s6, 0 597; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v0 598; SI-NEXT: v_mov_b32_e32 v2, 0 599; SI-NEXT: s_waitcnt lgkmcnt(0) 600; SI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 601; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 602; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0 603; SI-NEXT: s_waitcnt vmcnt(0) 604; SI-NEXT: v_ffbh_u32_e32 v0, v3 605; SI-NEXT: v_ffbh_u32_e32 v5, v4 606; SI-NEXT: v_or_b32_e32 v3, v3, v4 607; SI-NEXT: v_add_i32_e32 v0, vcc, 32, v0 608; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 609; SI-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc 610; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 611; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc 612; SI-NEXT: s_waitcnt lgkmcnt(0) 613; SI-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 614; SI-NEXT: s_endpgm 615; 616; VI-LABEL: v_ctlz_i64_trunc: 617; VI: ; %bb.0: 618; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 619; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 620; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0 621; VI-NEXT: v_mov_b32_e32 v4, 0 622; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 623; VI-NEXT: s_waitcnt lgkmcnt(0) 624; VI-NEXT: v_mov_b32_e32 v5, s3 625; VI-NEXT: v_mov_b32_e32 v2, s1 626; VI-NEXT: v_add_u32_e32 v1, vcc, s0, v1 627; VI-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc 628; VI-NEXT: v_add_u32_e32 v3, vcc, s2, v0 629; VI-NEXT: flat_load_dwordx2 v[0:1], v[1:2] 630; VI-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc 631; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 632; VI-NEXT: v_ffbh_u32_e32 v2, v0 633; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v2 634; VI-NEXT: v_ffbh_u32_e32 v5, v1 635; VI-NEXT: v_or_b32_e32 v0, v0, v1 636; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 637; VI-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc 638; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 639; VI-NEXT: v_cndmask_b32_e32 v0, 64, v1, vcc 640; VI-NEXT: flat_store_dword v[3:4], v0 641; VI-NEXT: s_endpgm 642; 643; EG-LABEL: v_ctlz_i64_trunc: 644; EG: ; %bb.0: 645; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 646; EG-NEXT: TEX 0 @6 647; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[] 648; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 649; EG-NEXT: CF_END 650; EG-NEXT: PAD 651; EG-NEXT: Fetch clause starting at 6: 652; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #1 653; EG-NEXT: ALU clause starting at 8: 654; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 655; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 656; EG-NEXT: ADD_INT * T1.X, KC0[2].Z, PV.W, 657; EG-NEXT: ALU clause starting at 11: 658; EG-NEXT: FFBH_UINT * T0.W, T1.X, 659; EG-NEXT: CNDE_INT * T0.W, T1.X, literal.x, PV.W, 660; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 661; EG-NEXT: LSHL T0.Z, T0.X, literal.x, 662; EG-NEXT: FFBH_UINT T1.W, T1.Y, 663; EG-NEXT: ADD_INT * T0.W, PV.W, literal.y, 664; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) 665; EG-NEXT: CNDE_INT T0.X, T1.Y, PS, PV.W, 666; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, PV.Z, 667; EG-NEXT: LSHR * T1.X, PV.W, literal.x, 668; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 669 %tid = call i32 @llvm.amdgcn.workitem.id.x() 670 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 671 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid 672 %val = load i64, i64 addrspace(1)* %in.gep 673 %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) 674 %trunc = trunc i64 %ctlz to i32 675 store i32 %trunc, i32 addrspace(1)* %out.gep 676 ret void 677} 678 679define amdgpu_kernel void @v_ctlz_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 680; SI-LABEL: v_ctlz_i32_sel_eq_neg1: 681; SI: ; %bb.0: 682; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 683; SI-NEXT: s_mov_b32 s3, 0xf000 684; SI-NEXT: s_mov_b32 s6, 0 685; SI-NEXT: s_mov_b32 s7, s3 686; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 687; SI-NEXT: v_mov_b32_e32 v1, 0 688; SI-NEXT: s_waitcnt lgkmcnt(0) 689; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 690; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 691; SI-NEXT: s_mov_b32 s2, -1 692; SI-NEXT: s_waitcnt vmcnt(0) 693; SI-NEXT: v_ffbh_u32_e32 v0, v0 694; SI-NEXT: s_waitcnt lgkmcnt(0) 695; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 696; SI-NEXT: s_endpgm 697; 698; VI-LABEL: v_ctlz_i32_sel_eq_neg1: 699; VI: ; %bb.0: 700; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 701; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 702; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 703; VI-NEXT: s_mov_b32 s7, 0xf000 704; VI-NEXT: s_mov_b32 s6, -1 705; VI-NEXT: s_waitcnt lgkmcnt(0) 706; VI-NEXT: v_mov_b32_e32 v1, s1 707; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 708; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 709; VI-NEXT: flat_load_dword v0, v[0:1] 710; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 711; VI-NEXT: v_ffbh_u32_e32 v0, v0 712; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 713; VI-NEXT: s_endpgm 714; 715; EG-LABEL: v_ctlz_i32_sel_eq_neg1: 716; EG: ; %bb.0: 717; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 718; EG-NEXT: TEX 0 @6 719; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[] 720; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 721; EG-NEXT: CF_END 722; EG-NEXT: PAD 723; EG-NEXT: Fetch clause starting at 6: 724; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 725; EG-NEXT: ALU clause starting at 8: 726; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 727; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 728; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 729; EG-NEXT: ALU clause starting at 11: 730; EG-NEXT: FFBH_UINT * T0.W, T0.X, 731; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W, 732; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 733; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, 734; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 735; EG-NEXT: -1(nan), 2(2.802597e-45) 736 %tid = call i32 @llvm.amdgcn.workitem.id.x() 737 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 738 %val = load i32, i32 addrspace(1)* %in.gep 739 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone 740 %cmp = icmp eq i32 %val, 0 741 %sel = select i1 %cmp, i32 -1, i32 %ctlz 742 store i32 %sel, i32 addrspace(1)* %out 743 ret void 744} 745 746define amdgpu_kernel void @v_ctlz_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 747; SI-LABEL: v_ctlz_i32_sel_ne_neg1: 748; SI: ; %bb.0: 749; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 750; SI-NEXT: s_mov_b32 s3, 0xf000 751; SI-NEXT: s_mov_b32 s6, 0 752; SI-NEXT: s_mov_b32 s7, s3 753; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 754; SI-NEXT: v_mov_b32_e32 v1, 0 755; SI-NEXT: s_waitcnt lgkmcnt(0) 756; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 757; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 758; SI-NEXT: s_mov_b32 s2, -1 759; SI-NEXT: s_waitcnt vmcnt(0) 760; SI-NEXT: v_ffbh_u32_e32 v0, v0 761; SI-NEXT: s_waitcnt lgkmcnt(0) 762; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 763; SI-NEXT: s_endpgm 764; 765; VI-LABEL: v_ctlz_i32_sel_ne_neg1: 766; VI: ; %bb.0: 767; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 768; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 769; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 770; VI-NEXT: s_mov_b32 s7, 0xf000 771; VI-NEXT: s_mov_b32 s6, -1 772; VI-NEXT: s_waitcnt lgkmcnt(0) 773; VI-NEXT: v_mov_b32_e32 v1, s1 774; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 775; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 776; VI-NEXT: flat_load_dword v0, v[0:1] 777; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 778; VI-NEXT: v_ffbh_u32_e32 v0, v0 779; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 780; VI-NEXT: s_endpgm 781; 782; EG-LABEL: v_ctlz_i32_sel_ne_neg1: 783; EG: ; %bb.0: 784; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 785; EG-NEXT: TEX 0 @6 786; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[] 787; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 788; EG-NEXT: CF_END 789; EG-NEXT: PAD 790; EG-NEXT: Fetch clause starting at 6: 791; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 792; EG-NEXT: ALU clause starting at 8: 793; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 794; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 795; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 796; EG-NEXT: ALU clause starting at 11: 797; EG-NEXT: FFBH_UINT * T0.W, T0.X, 798; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W, 799; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 800; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, 801; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 802; EG-NEXT: -1(nan), 2(2.802597e-45) 803 %tid = call i32 @llvm.amdgcn.workitem.id.x() 804 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 805 %val = load i32, i32 addrspace(1)* %in.gep 806 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone 807 %cmp = icmp ne i32 %val, 0 808 %sel = select i1 %cmp, i32 %ctlz, i32 -1 809 store i32 %sel, i32 addrspace(1)* %out 810 ret void 811} 812 813; TODO: Should be able to eliminate select here as well. 814define amdgpu_kernel void @v_ctlz_i32_sel_eq_bitwidth(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 815; SI-LABEL: v_ctlz_i32_sel_eq_bitwidth: 816; SI: ; %bb.0: 817; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 818; SI-NEXT: s_mov_b32 s3, 0xf000 819; SI-NEXT: s_mov_b32 s6, 0 820; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 821; SI-NEXT: v_mov_b32_e32 v1, 0 822; SI-NEXT: s_mov_b32 s7, s3 823; SI-NEXT: s_waitcnt lgkmcnt(0) 824; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 825; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 826; SI-NEXT: s_mov_b32 s2, -1 827; SI-NEXT: s_waitcnt vmcnt(0) 828; SI-NEXT: v_ffbh_u32_e32 v1, v0 829; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 830; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc 831; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 832; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc 833; SI-NEXT: s_waitcnt lgkmcnt(0) 834; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 835; SI-NEXT: s_endpgm 836; 837; VI-LABEL: v_ctlz_i32_sel_eq_bitwidth: 838; VI: ; %bb.0: 839; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 840; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 841; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 842; VI-NEXT: s_mov_b32 s7, 0xf000 843; VI-NEXT: s_mov_b32 s6, -1 844; VI-NEXT: s_waitcnt lgkmcnt(0) 845; VI-NEXT: v_mov_b32_e32 v1, s1 846; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 847; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 848; VI-NEXT: flat_load_dword v0, v[0:1] 849; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 850; VI-NEXT: v_ffbh_u32_e32 v1, v0 851; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 852; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc 853; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 854; VI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc 855; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 856; VI-NEXT: s_endpgm 857; 858; EG-LABEL: v_ctlz_i32_sel_eq_bitwidth: 859; EG: ; %bb.0: 860; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 861; EG-NEXT: TEX 0 @6 862; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[] 863; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 864; EG-NEXT: CF_END 865; EG-NEXT: PAD 866; EG-NEXT: Fetch clause starting at 6: 867; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 868; EG-NEXT: ALU clause starting at 8: 869; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 870; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 871; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 872; EG-NEXT: ALU clause starting at 11: 873; EG-NEXT: FFBH_UINT * T0.W, T0.X, 874; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W, 875; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 876; EG-NEXT: SETE_INT * T1.W, PV.W, literal.x, 877; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 878; EG-NEXT: CNDE_INT T0.X, PV.W, T0.W, literal.x, 879; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 880; EG-NEXT: -1(nan), 2(2.802597e-45) 881 %tid = call i32 @llvm.amdgcn.workitem.id.x() 882 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 883 %val = load i32, i32 addrspace(1)* %in.gep 884 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone 885 %cmp = icmp eq i32 %ctlz, 32 886 %sel = select i1 %cmp, i32 -1, i32 %ctlz 887 store i32 %sel, i32 addrspace(1)* %out 888 ret void 889} 890 891define amdgpu_kernel void @v_ctlz_i32_sel_ne_bitwidth(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { 892; SI-LABEL: v_ctlz_i32_sel_ne_bitwidth: 893; SI: ; %bb.0: 894; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 895; SI-NEXT: s_mov_b32 s3, 0xf000 896; SI-NEXT: s_mov_b32 s6, 0 897; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 898; SI-NEXT: v_mov_b32_e32 v1, 0 899; SI-NEXT: s_mov_b32 s7, s3 900; SI-NEXT: s_waitcnt lgkmcnt(0) 901; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 902; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 903; SI-NEXT: s_mov_b32 s2, -1 904; SI-NEXT: s_waitcnt vmcnt(0) 905; SI-NEXT: v_ffbh_u32_e32 v1, v0 906; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 907; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc 908; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 909; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc 910; SI-NEXT: s_waitcnt lgkmcnt(0) 911; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 912; SI-NEXT: s_endpgm 913; 914; VI-LABEL: v_ctlz_i32_sel_ne_bitwidth: 915; VI: ; %bb.0: 916; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 917; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 918; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 919; VI-NEXT: s_mov_b32 s7, 0xf000 920; VI-NEXT: s_mov_b32 s6, -1 921; VI-NEXT: s_waitcnt lgkmcnt(0) 922; VI-NEXT: v_mov_b32_e32 v1, s1 923; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 924; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 925; VI-NEXT: flat_load_dword v0, v[0:1] 926; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 927; VI-NEXT: v_ffbh_u32_e32 v1, v0 928; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 929; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc 930; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 931; VI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc 932; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 933; VI-NEXT: s_endpgm 934; 935; EG-LABEL: v_ctlz_i32_sel_ne_bitwidth: 936; EG: ; %bb.0: 937; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 938; EG-NEXT: TEX 0 @6 939; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[] 940; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 941; EG-NEXT: CF_END 942; EG-NEXT: PAD 943; EG-NEXT: Fetch clause starting at 6: 944; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 945; EG-NEXT: ALU clause starting at 8: 946; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 947; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 948; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 949; EG-NEXT: ALU clause starting at 11: 950; EG-NEXT: FFBH_UINT * T0.W, T0.X, 951; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W, 952; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 953; EG-NEXT: SETNE_INT * T1.W, PV.W, literal.x, 954; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 955; EG-NEXT: CNDE_INT T0.X, PV.W, literal.x, T0.W, 956; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 957; EG-NEXT: -1(nan), 2(2.802597e-45) 958 %tid = call i32 @llvm.amdgcn.workitem.id.x() 959 %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid 960 %val = load i32, i32 addrspace(1)* %in.gep 961 %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone 962 %cmp = icmp ne i32 %ctlz, 32 963 %sel = select i1 %cmp, i32 %ctlz, i32 -1 964 store i32 %sel, i32 addrspace(1)* %out 965 ret void 966} 967 968 define amdgpu_kernel void @v_ctlz_i8_sel_eq_neg1(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { 969; SI-LABEL: v_ctlz_i8_sel_eq_neg1: 970; SI: ; %bb.0: 971; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 972; SI-NEXT: s_mov_b32 s3, 0xf000 973; SI-NEXT: v_mov_b32_e32 v1, 0 974; SI-NEXT: s_mov_b32 s6, 0 975; SI-NEXT: s_mov_b32 s7, s3 976; SI-NEXT: s_waitcnt lgkmcnt(0) 977; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 978; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 979; SI-NEXT: s_mov_b32 s2, -1 980; SI-NEXT: s_waitcnt vmcnt(0) 981; SI-NEXT: v_ffbh_u32_e32 v0, v0 982; SI-NEXT: s_waitcnt lgkmcnt(0) 983; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 984; SI-NEXT: s_endpgm 985; 986; VI-LABEL: v_ctlz_i8_sel_eq_neg1: 987; VI: ; %bb.0: 988; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 989; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 990; VI-NEXT: s_mov_b32 s7, 0xf000 991; VI-NEXT: s_mov_b32 s6, -1 992; VI-NEXT: s_waitcnt lgkmcnt(0) 993; VI-NEXT: v_mov_b32_e32 v1, s1 994; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 995; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 996; VI-NEXT: flat_load_ubyte v0, v[0:1] 997; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 998; VI-NEXT: v_ffbh_u32_e32 v0, v0 999; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 1000; VI-NEXT: s_endpgm 1001; 1002; EG-LABEL: v_ctlz_i8_sel_eq_neg1: 1003; EG: ; %bb.0: 1004; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1005; EG-NEXT: TEX 0 @6 1006; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] 1007; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 1008; EG-NEXT: CF_END 1009; EG-NEXT: PAD 1010; EG-NEXT: Fetch clause starting at 6: 1011; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 1012; EG-NEXT: ALU clause starting at 8: 1013; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X, 1014; EG-NEXT: ALU clause starting at 9: 1015; EG-NEXT: FFBH_UINT T0.W, T0.X, 1016; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x, 1017; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 1018; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 1019; EG-NEXT: LSHL * T1.W, PS, literal.y, 1020; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45) 1021; EG-NEXT: LSHL T0.X, PV.W, PS, 1022; EG-NEXT: LSHL * T0.W, literal.x, PS, 1023; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) 1024; EG-NEXT: MOV T0.Y, 0.0, 1025; EG-NEXT: MOV * T0.Z, 0.0, 1026; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1027; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1028 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1029 %valptr.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid 1030 %val = load i8, i8 addrspace(1)* %valptr.gep 1031 %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone 1032 %cmp = icmp eq i8 %val, 0 1033 %sel = select i1 %cmp, i8 -1, i8 %ctlz 1034 store i8 %sel, i8 addrspace(1)* %out 1035 ret void 1036} 1037 1038 define amdgpu_kernel void @v_ctlz_i16_sel_eq_neg1(i16 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %valptr) nounwind { 1039; SI-LABEL: v_ctlz_i16_sel_eq_neg1: 1040; SI: ; %bb.0: 1041; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 1042; SI-NEXT: s_mov_b32 s3, 0xf000 1043; SI-NEXT: s_mov_b32 s2, -1 1044; SI-NEXT: s_mov_b32 s6, s2 1045; SI-NEXT: s_mov_b32 s7, s3 1046; SI-NEXT: s_waitcnt lgkmcnt(0) 1047; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 1048; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 1049; SI-NEXT: s_waitcnt vmcnt(0) 1050; SI-NEXT: v_ffbh_u32_e32 v0, v0 1051; SI-NEXT: s_waitcnt lgkmcnt(0) 1052; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1053; SI-NEXT: s_endpgm 1054; 1055; VI-LABEL: v_ctlz_i16_sel_eq_neg1: 1056; VI: ; %bb.0: 1057; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1058; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 1059; VI-NEXT: s_mov_b32 s7, 0xf000 1060; VI-NEXT: s_mov_b32 s6, -1 1061; VI-NEXT: s_mov_b32 s2, s6 1062; VI-NEXT: s_mov_b32 s3, s7 1063; VI-NEXT: s_waitcnt lgkmcnt(0) 1064; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0 1065; VI-NEXT: s_waitcnt vmcnt(0) 1066; VI-NEXT: v_ffbh_u32_e32 v1, v0 1067; VI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0 1068; VI-NEXT: v_cndmask_b32_e64 v0, 32, v1, s[0:1] 1069; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 1070; VI-NEXT: v_mov_b32_e32 v1, 0xffff 1071; VI-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[0:1] 1072; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 1073; VI-NEXT: s_endpgm 1074; 1075; EG-LABEL: v_ctlz_i16_sel_eq_neg1: 1076; EG: ; %bb.0: 1077; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1078; EG-NEXT: TEX 0 @6 1079; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] 1080; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 1081; EG-NEXT: CF_END 1082; EG-NEXT: PAD 1083; EG-NEXT: Fetch clause starting at 6: 1084; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1 1085; EG-NEXT: ALU clause starting at 8: 1086; EG-NEXT: MOV * T0.X, KC0[2].Z, 1087; EG-NEXT: ALU clause starting at 9: 1088; EG-NEXT: FFBH_UINT T0.W, T0.X, 1089; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x, 1090; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 1091; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 1092; EG-NEXT: LSHL * T1.W, PS, literal.y, 1093; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 1094; EG-NEXT: LSHL T0.X, PV.W, PS, 1095; EG-NEXT: LSHL * T0.W, literal.x, PS, 1096; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 1097; EG-NEXT: MOV T0.Y, 0.0, 1098; EG-NEXT: MOV * T0.Z, 0.0, 1099; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1100; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1101 %val = load i16, i16 addrspace(1)* %valptr 1102 %ctlz = call i16 @llvm.ctlz.i16(i16 %val, i1 false) nounwind readnone 1103 %cmp = icmp eq i16 %val, 0 1104 %sel = select i1 %cmp, i16 -1, i16 %ctlz 1105 store i16 %sel, i16 addrspace(1)* %out 1106 ret void 1107} 1108 1109; FIXME: Need to handle non-uniform case for function below (load without gep). 1110define amdgpu_kernel void @v_ctlz_i7_sel_eq_neg1(i7 addrspace(1)* noalias %out, i7 addrspace(1)* noalias %valptr) nounwind { 1111; SI-LABEL: v_ctlz_i7_sel_eq_neg1: 1112; SI: ; %bb.0: 1113; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb 1114; SI-NEXT: s_mov_b32 s3, 0xf000 1115; SI-NEXT: v_mov_b32_e32 v1, 0 1116; SI-NEXT: s_mov_b32 s6, 0 1117; SI-NEXT: s_mov_b32 s7, s3 1118; SI-NEXT: s_waitcnt lgkmcnt(0) 1119; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[4:7], 0 addr64 1120; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 1121; SI-NEXT: s_mov_b32 s2, -1 1122; SI-NEXT: s_waitcnt vmcnt(0) 1123; SI-NEXT: v_ffbh_u32_e32 v0, v0 1124; SI-NEXT: v_and_b32_e32 v0, 0x7f, v0 1125; SI-NEXT: s_waitcnt lgkmcnt(0) 1126; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 1127; SI-NEXT: s_endpgm 1128; 1129; VI-LABEL: v_ctlz_i7_sel_eq_neg1: 1130; VI: ; %bb.0: 1131; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1132; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c 1133; VI-NEXT: s_mov_b32 s7, 0xf000 1134; VI-NEXT: s_mov_b32 s6, -1 1135; VI-NEXT: s_waitcnt lgkmcnt(0) 1136; VI-NEXT: v_mov_b32_e32 v1, s1 1137; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 1138; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1139; VI-NEXT: flat_load_ubyte v0, v[0:1] 1140; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1141; VI-NEXT: v_ffbh_u32_e32 v0, v0 1142; VI-NEXT: v_and_b32_e32 v0, 0x7f, v0 1143; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 1144; VI-NEXT: s_endpgm 1145; 1146; EG-LABEL: v_ctlz_i7_sel_eq_neg1: 1147; EG: ; %bb.0: 1148; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1149; EG-NEXT: TEX 0 @6 1150; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] 1151; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 1152; EG-NEXT: CF_END 1153; EG-NEXT: PAD 1154; EG-NEXT: Fetch clause starting at 6: 1155; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 1156; EG-NEXT: ALU clause starting at 8: 1157; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X, 1158; EG-NEXT: ALU clause starting at 9: 1159; EG-NEXT: FFBH_UINT T0.W, T0.X, 1160; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x, 1161; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 1162; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 1163; EG-NEXT: LSHL * T1.W, PS, literal.y, 1164; EG-NEXT: 127(1.779649e-43), 3(4.203895e-45) 1165; EG-NEXT: LSHL T0.X, PV.W, PS, 1166; EG-NEXT: LSHL * T0.W, literal.x, PS, 1167; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) 1168; EG-NEXT: MOV T0.Y, 0.0, 1169; EG-NEXT: MOV * T0.Z, 0.0, 1170; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1171; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1172 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1173 %valptr.gep = getelementptr i7, i7 addrspace(1)* %valptr, i32 %tid 1174 %val = load i7, i7 addrspace(1)* %valptr.gep 1175 %ctlz = call i7 @llvm.ctlz.i7(i7 %val, i1 false) nounwind readnone 1176 %cmp = icmp eq i7 %val, 0 1177 %sel = select i1 %cmp, i7 -1, i7 %ctlz 1178 store i7 %sel, i7 addrspace(1)* %out 1179 ret void 1180} 1181